JP2009210381A - Method for extracting characteristics of intrinsic element - Google Patents

Abstract

To provide an intrinsic element characteristic extraction method capable of extracting the characteristic of an intrinsic element while the characteristic impedance of a parasitic circuit is unknown.
In step 101, an S parameter S ^(DUT) of a 2-port functional circuit DUT viewed from an external port is measured using a vector network analyzer VNA. Next, in step 102, the S parameter S of the 4-port parasitic circuit PC viewed from the external port and the internal port is calculated using an electromagnetic field simulator. Next, in step 103, the S parameter S calculated in step 102 is converted into a hybrid parameter A of S parameter / Z parameter. Finally, in step 104, the Z parameter Z ^(DEV) of the intrinsic element FET is calculated using the S parameter S and the hybrid parameter A of the functional circuit DUT.
[Selection] Figure 1

Description

  The present invention relates to an intrinsic element characteristic extraction method for extracting intrinsic element characteristics from a functional circuit having a parasitic circuit having an external port and an internal port and an intrinsic element embedded in the parasitic circuit and connected to the internal port of the parasitic circuit. .

  Generally, a semiconductor device is provided with a functional circuit such as a TEG (Test Element Group) circuit. This functional circuit consists of an intrinsic element such as a field effect transistor (FET) and a microstrip line (MSL) or a coplanar line (CPW) connecting the FETs. In this case, the microstrip line or coplanar line constitutes a parasitic circuit. To do. When the semiconductor device is a high-frequency microwave monolithic integrated circuit (MMIC), it is necessary to accurately grasp the characteristics of the FET in order to design the MMIC with high accuracy.

  8A and 8B are diagrams illustrating an example of a functional circuit, where FIG. 8A is a plan view and FIG. 8B is a cross-sectional view taken along line BB in FIG. In the functional circuit DUT of FIG. 8, two FET1 and FET2 having the same characteristics are provided symmetrically. Here, G1 and G2 are the gates of FET1 and FET2, S1 and S2 are the sources of FET1 and FET2, D is a common drain of FET1 and FET2, and these are composed of coplanar lines. Construct a parasitic circuit PC against. P1 and P2 are external ports of the functional circuit DUT, that is, the parasitic circuit PC, and P3 and P4 are internal ports of the parasitic circuit PC.

  FIG. 9 is a plan view functionally showing the functional circuit DUT of FIG. 8. For simplification, FET1 and FET2 in FIG. 8 are set as one FET, and two internal ports P3 are set as one internal port P3. It is a thing.

The first conventional intrinsic element characteristic extraction method for extracting the characteristics of the FET of FIG. 9 such as the Z parameter Z _{2 × 2} ^(DUT) assumes the equivalent circuit of the functional circuit DUT of FIG. 8 as shown in FIG. Then, using the functional circuit DUT in the open state shown in FIG. 11A and the functional circuit DUT in the short circuit state shown in FIG. 11B, the admittances Y _p1 , Y _p2 , Y _p3 in the equivalent circuit of FIG. This is performed by calculating impedances Z _s1 , Z _s2 , and Z _s3 (see Non-Patent Document 1).

However, the above-described first conventional intrinsic element characteristic extraction method has the following problems.
(1) Although the characteristic of the parasitic circuit PC is assumed in the equivalent circuit of FIG. 10, this assumption does not hold strictly.
(2) The pattern of the functional circuit DUT in FIGS. 11A and 11B is assumed to be in an open state and a short circuit state in terms of lumped constants, but this assumption does not hold strictly at high frequencies.
Therefore, the extracted Z parameter of the FET has a large error, and in order to improve accuracy, it must be prototyped a plurality of times. As a result, the manufacturing cost of the semiconductor device increases.

  The second conventional intrinsic element characteristic extraction method measures the S parameter of the functional circuit DUT as viewed from the external port using a vector network analyzer, and the parasitic circuit as viewed from the external port and the internal port using an electromagnetic field simulator. The S parameter is calculated, and the Z parameter of the intrinsic element is calculated using the S parameter of the functional circuit DUT and the S parameter of the parasitic circuit (see Non-Patent Document 2).

According to the second conventional intrinsic element characteristic extraction method, the assumption of the equivalent circuit of the parasitic circuit is unnecessary, and the error of the Z parameter of the parasitic circuit PC is correspondingly reduced.
MCAM Koolen, JAM Geelen, MPJG Versleijen, “An improved de-embedding technique for on-wafer high-frequency characterization,” Proceedings of the 1991 Bipolar Circuits and Technology Meeting, pp.188-191, 9-10 Sept. 1991 S. Bousnina, C. Falt, P. Mandeville, AB Kouki, FM Ghannouchi, “An accurate on-wafer deembedding technique with application to HBT devices characterization,” IEEE Trans. MTT, Vol.50, No.2, pp.420 -424, Feb. 2002

  However, in the above-described second conventional intrinsic element characteristic extraction method, it is necessary to obtain the characteristic impedance of the parasitic circuit. As a result, the input parameter of the user increases and the extraction is performed based on the error of the parameter. Thus, the accuracy of the Z parameter of the intrinsic circuit is lowered, and therefore, in order to increase the accuracy, it is necessary to make a prototype several times. As a result, there is a problem that the manufacturing cost of the semiconductor device increases.

In order to solve the above-mentioned problem, an intrinsic characteristic for extracting the characteristic of an intrinsic element from a functional circuit having a parasitic circuit having an external port and an intrinsic element embedded in the parasitic circuit and connected to the internal port of the parasitic circuit In the element characteristic extraction method, the S parameter measurement step measures the S parameter of the functional circuit as seen from the external port using a vector network analyzer, and the S parameter calculation step looks at the external port and the internal port using an electromagnetic field simulator. The S parameter of the parasitic circuit is calculated, and in the hybrid parameter conversion step, the S parameter of the parasitic circuit is expressed by the current and voltage only for the internal port portion of the S parameter of the parasitic circuit, and the S parameter, the Z parameter, and the Y parameter. High with one of the hybrid parameters of Z and Y parameters Into a lid parameter, Z parameter calculating step calculates the Z parameter of the intrinsic device using S-parameters and hybrid parameters of the functional circuit ^{(Z (DEV)).} As a result, the characteristic impedance of the parasitic circuit can be handled as unknown.

  Since the characteristic impedance of the parasitic circuit can be handled without being known, the input parameters are reduced, and the accuracy of the extracted intrinsic element Z parameter can be improved.

  FIG. 1 is a flowchart showing an embodiment of an intrinsic element characteristic extraction method according to the present invention, in which the characteristic of an intrinsic element FET, that is, a Z parameter is extracted from the functional circuit DUT of FIG.

であり、a₁,b₁は外部ポートP1での寄生回路PCへの進行波、寄生回路PCからの反射波を表し、a₂,b₂は外部ポートP2での寄生回路PCへの進行波、寄生回路PCからの反射波を表す。 First, in step 101, the S parameter S ^(DUT) of the 2-port functional circuit DUT viewed from the external ports P1 and P2 is calculated using the vector network analyzer VNA. That is, as shown in FIG. 2, the vector network analyzer VNA is connected to the external ports P1 and P2 of the functional circuit DUT, and the S parameter S ^(DUT) of the 2-port functional circuit DUT is measured. in this case,

A ₁ and b ₁ represent the traveling wave to the parasitic circuit PC at the external port P1 and the reflected wave from the parasitic circuit PC, and a ₂ and b ₂ represent the traveling wave to the parasitic circuit PC at the external port P2. Represents the reflected wave from the parasitic circuit PC.

であり、a₃,b₃は内部ポートP3での寄生回路PCへの進行波、寄生回路PCからの反射波を表し、a₄,b₄は内部ポートP4での寄生回路PCへの進行波、寄生回路PCからの反射波を表す。 Next, in step 102, the S parameter S of the parasitic circuit PC viewed from the external ports P1 and P2 and the internal ports P3 and P4 is calculated using an electromagnetic field simulator. That is, as shown in FIG. 3, the S parameter of the 4-port parasitic circuit PC obtained by removing the intrinsic element FET from the 2-port functional circuit DUT is calculated. in this case,

A ₃ and b ₃ represent the traveling wave to the parasitic circuit PC at the internal port P3 and the reflected wave from the parasitic circuit PC, and a ₄ and b ₄ represent the traveling wave to the parasitic circuit PC at the internal port P4. Represents the reflected wave from the parasitic circuit PC.

と表現したいので、

と小行列を表現すると、A_{ij}はS_{ij}を用いて

で与えられる。ここで、Iは2 x 2の単位行列、Z_iは内部ポートi（i=3,4）の内部インピーダンス、diag（a,b）は対角成分を左上から右下に向かってa,bとする対角行列を表わす。 Next, in step 103, the S parameter S calculated in step 102 is converted into a hybrid parameter A of S parameter / Z parameter. In this case, the external ports P1 and P2 are represented by S parameters (no characteristic impedance is required), and the internal ports P3 and P4 are represented by Z parameters.

I want to express

A _{ij} can be expressed using S _{ij}

Given in. Where I is a 2 x 2 identity matrix, Z _i is the internal impedance of the internal port i (i = 3, 4), and diag (a, b) is the diagonal component from upper left to lower right a, b Represents a diagonal matrix.

である。負号が付いているのは、電流は寄生回路PCに入る向きに定義されているから、言い換えると真性素子FETから出る向きに定義されているからである。数３の式より、

数６の式と数７の第２式から[V₃ V₄]^tを消去し、[I₃ I₄]^tを[a₁ a₂]^tで表すと、

数８の式を数７の第１式に代入し、数６の式と比較すると、真性素子FETのZパラメータZ^(DEV)は

となる。 Finally, in step 104, the Z parameter Z ^(DEV) of the intrinsic element FET is calculated using the S parameter S and the hybrid parameter A of the functional circuit DUT. Here, the Z parameter Z ^(DEV) of the intrinsic element FET is

It is. The reason why the negative sign is attached is that the current is defined in the direction of entering the parasitic circuit PC, in other words, in the direction of exiting from the intrinsic element FET. From Equation 3,

If [V ₃ V ₄ ] ^t is deleted from Equation 6 and Equation 2 and [I ₃ I ₄ ] ^t is represented by [a ₁ a ₂ ] ^t ,

Substituting Equation 8 into Equation 1 and comparing it with Equation 6, Z parameter Z ^(DEV) of intrinsic element FET is

It becomes.

As described above, according to the intrinsic element characteristic extraction method of FIG. 1, the characteristic impedance of the parasitic circuit PC is not required to obtain the Z parameter Z ^(DEV) of the intrinsic element FET. As a result, the Z parameter of the intrinsic element FET is obtained. The accuracy of Z ^(DEV) is improved.

Next, simulation results according to the present invention will be described with reference to FIGS. Assuming that FET1 and FET2 in FIG. 8 are connected to elements having the same characteristics, the analysis area can be halved by assuming a magnetic wall (PMC) as shown in FIG. 4 from the symmetry of structure and excitation. In this structure, R1 = 50Ω, C1 = 0.1pF is connected in parallel to the internal port P3, R2 = 75Ω, L2 = 1nH is connected in parallel to the internal port P4, and commercial software HFSS based on the finite element method as an electromagnetic field simulator. The S parameter S ^(DUT) was analyzed, and it was confirmed whether the element parameters inside the FET could be extracted. FIG. 5 shows a result of extracting element parameters loaded to the internal ports P3 and P4 from the Z parameter Z ^(DEV) extracted according to the present invention. The value of the internal lumped element is obtained with high accuracy. In addition, it turns out that the result extracted by the 1st conventional intrinsic element characteristic extraction method is also shown. Thus, it was confirmed that the intrinsic element characteristic extraction method according to the present invention has not only high versatility but also higher accuracy than the first conventional intrinsic element characteristic extraction method.

  In order to confirm the reliability of the electromagnetic field simulator, as shown in FIGS. 6 and 7, the function circuit in the open state ((A) in FIG. 11) and the function circuit in the short-circuit state ((B) in FIG. 11). The calculated value (HFSS) is compared with the experimental value (EXP), and a good agreement between the two is confirmed.

Note that the hybrid parameter A in step 103 of FIG. 1 may be a hybrid parameter of S parameter and Y parameter. That is, Y = Z ⁻¹ can be converted. The hybrid parameter A can also be a hybrid parameter of the S parameter and the Y and Z parameters. That is, a part of the internal port can be expressed as a Z parameter and the other as a Y parameter.

  In the above embodiment, the parasitic circuit has two external ports and two internal ports, but the parasitic circuit has N (N = 1, 2, 3, 4,...) External ports and N or less. Can have internal ports. The intrinsic circuit may be an active element other than an FET, such as a bipolar transistor.

  When an analog chip is packaged, the operation characteristics of the internal analog chip can be extracted by measuring and calculating characteristics from the outside of the package by applying the present invention. As a result, the present invention is also effective for predicting the effects of packaging, designing for reducing interference between analog chips, and the like.

  Furthermore, the semiconductor device in the above-described embodiment includes a device using a compound semiconductor substrate such as a silicon substrate, GaAs, or GaN. In addition to the semiconductor device, the present invention can also be applied to a ceramic substrate, an organic substrate, a diamond substrate, or the like, or a multilayer substrate.

It is a flowchart which shows embodiment of the intrinsic element characteristic extraction method which concerns on this invention. FIG. 2 is a diagram for supplementarily explaining an S parameter measurement step in FIG. 1. FIG. 2 is a diagram for supplementarily explaining an S parameter calculation step in FIG. 1. It is a figure which shows the functional circuit for demonstrating the simulation result of this invention, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). It is a graph which shows the element value inside FET extracted from the simulation result of this invention. It is a graph for confirming the reliability of an electromagnetic field simulator. It is a graph for confirming the reliability of an electromagnetic field simulator. It is a figure which shows a general functional circuit, (A) is a top view, (B) is the BB sectional drawing of (A). FIG. 9 is a plan view functionally showing the functional circuit of FIG. 8. It is an equivalent circuit diagram for demonstrating the 1st conventional intrinsic element characteristic extraction method. It is a top view of the functional circuit for demonstrating the element value of FIG. 10, Comprising: (A) shows an open state, (B) shows a short circuit state.

Explanation of symbols

DUT: Functional circuit
PC: Parasitic circuit
FET: Intrinsic element
P1, P2: External port
P3, P4: Internal ports

Claims (3)

From the functional circuit (DUT) comprising a parasitic circuit (PC) having an external port (P1, P2) and an intrinsic element embedded in the parasitic circuit and connected to the internal port (P3, P4) of the parasitic circuit An intrinsic element characteristic extraction method for extracting the characteristic of an intrinsic element,
Measuring an S parameter (S ^(DUT) ) of the functional circuit viewed from the external port using a vector network analyzer;
Calculating an S parameter (S) of the parasitic circuit viewed from the external port and the internal port using an electromagnetic simulator;
Of the S parameters of the parasitic circuit, only the internal port portion is expressed by current and voltage so that the S parameter of the parasitic circuit is an S parameter, a Z parameter, a Y parameter, and one of the hybrid parameters of the Z and Y parameters. Converting to hybrid parameter (A);
And a step of calculating a Z parameter (Z ^(DEV) ) of the intrinsic element using the S parameter of the functional circuit and the hybrid parameter.   2. The intrinsic element characteristic extraction method according to claim 1, wherein the number of external ports is N (= 1, 2, 3,...), And the number of internal ports is N or less. A parasitic circuit (PC) having first and second external ports (P1, P2) and an authenticity embedded in the parasitic circuit and connected to the first and second internal ports (P3, P4) of the parasitic circuit An intrinsic element characteristic extraction method for extracting the characteristic of the intrinsic element from a functional circuit (DUT) comprising the element,
The S parameter S ^(DUT) of the functional circuit as seen from the first and second external ports using a vector network analyzer,

Where a ₁ and b ₁ represent traveling waves to the parasitic circuit at the first external port and reflected waves from the parasitic circuit, and a ₂ and b ₂ represent the parasitic waves at the second external port. Measuring with a traveling wave to the circuit, a reflected wave from the parasitic circuit;
S parameter S of the parasitic circuit viewed from the external port and the internal port using an electromagnetic simulator,

Where a ₃ and b ₃ represent traveling waves to the parasitic circuit at the first internal port and reflected waves from the parasitic circuit, and a ₄ and b ₄ represent the parasitic waves at the second internal port. A step of calculating by a traveling wave to the circuit and a reflected wave from the parasitic circuit;
Of the S parameters of the parasitic circuit, only the first and second internal port portions are expressed by current and voltage, whereby the S parameter of the parasitic circuit is expressed by the following S parameter and Z parameter hybrid parameter A

However,

A _{ij} can be expressed using S _{ij}

I is a 2 × 2 unit matrix, Z _i is the internal impedance of the first and second internal ports, and diag (a, b) is a diagonal with diagonal components a, b from upper left to lower right Converting to a matrix,
Using the S parameter of the functional circuit and the hybrid parameter, the intrinsic parameter Z parameter Z ^(DEV) ,

A method of extracting characteristics of an intrinsic element, comprising the step of:

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