JP2009206402A - Method for designing semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To design a semiconductor device with high voltage resistance as to a semiconductor device having a protection circuit and a design method of the semiconductor device. <P>SOLUTION: A design apparatus calculates a parasitic capacity between power supply pads 44a, 44b to which an inner circuit 32 is connected in the design processing of the semiconductor device provided with the inner circuit 32 corresponding to a function and compares the parasitic capacity value with a capacity threshold stored in a library. When the parasitic capacity value is within the capacity threshold, the design apparatus separates the inner circuit 32 having the parasitic capacity value from a power supply. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a protection circuit and a design method thereof.

  In general semiconductor devices (LSIs), power supply clamps are used to protect fine semiconductor elements that make up internal circuits from surge currents (overcurrents) caused by external ESD (Electro Static Discharge). A circuit is provided as a protection circuit.

  As shown in FIG. 10A, the internal circuit 91 formed on the LSI is connected between power supply lines 93a and 93b connected to the power supply pad 92a and the power supply pad 92b formed on the periphery of the LSI, respectively. Yes. The internal circuit 91 is supplied with the high potential power VDD from the outside of the LSI through the power supply pad 92a and the power supply wiring 93a, and is supplied with the low potential power supply VSS from the outside of the LSI through the power supply pad 92b and the power supply wiring 93b. .

  The internal circuit 91 has a parasitic capacitance C91 connected between the power supply wirings 93a and 93b. The capacitance value of the parasitic capacitance C91 is the total value of the capacitances such as the parasitic capacitance of the elements constituting the internal circuit 91 and the parasitic capacitance between the power supply wirings that supply power to the elements. A protection circuit 94 that protects the internal circuit 91 from surge current is connected between the power supply wires 93a and 93b.

  As shown in FIG. 10B, the protection circuit 94 includes an NMOS transistor T91. The NMOS transistor T91 has a gate and a source connected to the power supply wiring 93b and a drain connected to the power supply wiring 93a. The NMOS transistor T91 connected as described above is normally off.

  When a surge voltage is applied to the power supply pad 92a, the surge voltage is applied to the base of the parasitic bipolar transistor T92 formed between the drain and source of the NMOS transistor T91 and the parasitic capacitance C91. The parasitic bipolar transistor T92 is turned on by a surge current applied to its base, and a current flows between the collector and emitter of the parasitic bipolar transistor T92.

  In addition, the charge accumulated in the parasitic capacitance C91 due to the surge voltage flows to the power supply wiring 93b through the parasitic bipolar transistor T92 that is turned on. In this way, the surge current flows through the parasitic bipolar transistor T92, thereby preventing the surge current from flowing through the internal circuit 91 and protecting the internal circuit 91 from the surge current caused by ESD or the like.

As this type of semiconductor device, for example, Patent Document 1 discloses that a power supply wiring layer is electrically divided into a plurality of parts, and a capacitance formed between the surface of the semiconductor device and the power supply wiring layer is reduced to reduce static electricity due to charging. A semiconductor device for preventing failure due to electric breakdown is disclosed.
Japanese Patent Laid-Open No. 8-116026

  However, the breakdown voltage of the power supply ESD in the semiconductor device may be low depending on the combination of the circuit configuration of the protection circuit 94 and the capacitance value of the parasitic capacitance C91. The relationship between the breakdown voltage of the power supply ESD and the capacitance value of the parasitic capacitance C91 in the semiconductor device will be described below.

  As shown in FIG. 10B, when a surge voltage is applied to the power supply pad 92a, the potential of the drain region of the NMOS transistor T91 rises, an avalanche breakdown occurs at the substrate and the pn junction surface, and the parasitic bipolar transistor T92 An avalanche current flows between the collector and the base. The avalanche current at this time is equivalently shown as a current flowing from the current source 95, and the substrate resistance is equivalently shown as a resistor R91. As the avalanche current flows through the substrate resistance, the potential of the substrate locally rises, and the parasitic bipolar transistor T92 becomes conductive. In FIG. 10B, a capacitor C92 indicates a parasitic capacitance between the drain region of the NMOS transistor T91 and the substrate. At this time, a current flows from the parasitic capacitance C91 to the parasitic bipolar transistor T92 depending on the capacitance value of the parasitic capacitance C91, and the current flowing between the collector and the emitter of the parasitic bipolar transistor T92 increases. As a result, the PN junction of the parasitic bipolar transistor T92, that is, the PN junction between the drain region of the NMOS transistor T91 and the p-type diffusion region is broken. That is, the protection circuit 94 does not function as a power clamp circuit, that is, the withstand voltage of the power ESD is lowered.

The purpose of this semiconductor device design method is to design a semiconductor device with a high protection circuit withstand voltage.
The purpose of this semiconductor device is to increase the breakdown voltage of the protection circuit and protect the internal circuit.

  In this method of designing a semiconductor device, a first power supply voltage is supplied via a first power supply wiring connected between a first power supply terminal and a second power supply terminal, and connected to the first power supply terminal. An internal circuit to which a second power supply voltage is supplied via a second power supply wiring connected to a terminal, and an internal circuit connected in parallel with the internal circuit, and conducting when an electrostatic discharge occurs with respect to the internal circuit. A protection circuit for protecting the internal circuit from current), a parasitic capacitance value between the first power supply terminal and the second power supply terminal is calculated, and the parasitic capacitance is calculated. The internal circuit is separated from the power supply so that the value becomes smaller than a predetermined capacity threshold value.

  According to this method for designing a semiconductor device, the internal circuit is separated from the power supply so that the parasitic capacitance between the first power supply terminal and the second power supply terminal is smaller than a predetermined capacitance threshold value. The resulting withstand voltage of the protection circuit is increased.

  In this method of designing a semiconductor device, a first power supply voltage is supplied via a first power supply wiring connected between a first power supply terminal and a second power supply terminal, and connected to the first power supply terminal. An internal circuit to which a second power supply voltage is supplied via a second power supply wiring connected to a terminal; and an internal circuit connected in parallel with the internal circuit, and conducting when an electrostatic discharge occurs with respect to the internal circuit; A design method for a semiconductor device comprising a protection circuit for protecting an internal circuit, wherein a parasitic capacitance value between the first power supply terminal and the second power supply terminal is calculated, and the parasitic capacitance value and the capacitance are calculated. The internal circuit of the parasitic capacitance value within the range set by the capacitance threshold is separated from the power source based on the comparison result.

  According to this semiconductor device design method, by separating the internal circuit from the power supply so that there is no parasitic capacitance value within the range set by the capacitance threshold, the parasitic capacitance within that range has no effect on the protection circuit. And the withstand voltage of the protection circuit is increased.

  Further, in this semiconductor device design method, the protection circuit is connected to a power supply wiring in which a source and a drain are connected to the first power supply wiring and the second power supply wiring, respectively, and a low potential voltage is supplied to the gate. The capacitance threshold value flows in the parasitic bipolar transistor of the N channel MOS transistor due to a surge current applied to the first power supply terminal and the second power supply terminal. It is set based on the amount of current and the characteristics of the parasitic bipolar transistor.

  According to this method for designing a semiconductor device, the internal circuit is protected when a surge current is applied by a power supply clamp circuit composed of an N-channel MOS transistor, and the parasitic capacitance value of the internal circuit and the current flowing through the transistor constituting the power supply clamp circuit The internal circuit is power-separated according to the value and the characteristics of the transistors constituting the power clamp circuit.

  The semiconductor device is connected between a first power supply terminal and a second power supply terminal, supplied with a first power supply voltage via a first power supply line connected to the first power supply terminal, and connected to the second power supply terminal. An internal circuit to which a second power supply voltage is supplied via the second power supply wiring connected to the internal circuit and connected in parallel with the internal circuit, and conducts when an electrostatic discharge occurs to the internal circuit to protect the internal circuit from a surge current A protection circuit configured to prevent a parasitic capacitance value between the first power supply terminal and the second power supply terminal from being lower than a predetermined capacitance threshold value. The power supply is separated.

  According to this semiconductor device, the internal circuit is separated from the power supply so that the parasitic capacitance between the first power supply terminal and the second power supply terminal is smaller than a predetermined capacitance threshold, thereby protecting the parasitic capacitance. The withstand voltage of the circuit is increased and the internal circuit is protected.

  The semiconductor device is connected between a first power supply terminal and a second power supply terminal, supplied with a first power supply voltage via a first power supply line connected to the first power supply terminal, and connected to the second power supply terminal. An internal circuit to which a second power supply voltage is supplied via the second power supply wiring connected to the internal circuit and connected in parallel with the internal circuit, and conducts when an electrostatic discharge occurs to the internal circuit to protect the internal circuit from a surge current The internal circuit is configured so that a parasitic capacitance value between the first power supply terminal and the second power supply terminal is lower than a first threshold value. Or a value higher than a second threshold value higher than the first threshold value.

  According to this semiconductor device, an internal circuit whose parasitic capacitance value is lower than the first threshold value or an internal circuit whose parasitic capacitance value is higher than the second threshold value is formed, and the influence from the internal circuit on the protection circuit is increased. As a result, the withstand voltage of the protection circuit increases and the internal circuit is protected.

  The semiconductor device is connected between a first power supply terminal and a second power supply terminal, supplied with a first power supply voltage via a first power supply line connected to the first power supply terminal, and connected to the second power supply terminal. An internal circuit to which a second power supply voltage is supplied via the second power supply wiring connected to the internal circuit and connected in parallel with the internal circuit, and conducts when an electrostatic discharge occurs to the internal circuit to protect the internal circuit from a surge current And a protection circuit that has a parasitic capacitance value between the first power supply terminal and the second power supply terminal that is different between the first threshold value and the second threshold value. The configuration of the internal circuit is set so as not to include the value of.

  Since this semiconductor device does not include the internal circuit of the parasitic capacitance value between the first threshold value and the second threshold value, the influence of the parasitic capacitance of the internal circuit on the protection circuit is reduced, and the protection circuit The withstand voltage is increased, and the internal circuit is protected.

  The protection circuit of the semiconductor device includes an N-channel MOS transistor connected to a power supply wiring in which a source and a drain are connected to the first power supply wiring and the second power supply wiring, respectively, and a low potential voltage is supplied to a gate. In this semiconductor device, the internal circuit is protected from a surge current caused by ESD or the like by the power clamp circuit made of an N-channel MOS transistor.

  The capacitance threshold value of the semiconductor device includes the amount of current flowing through the parasitic bipolar transistor of the N-channel MOS transistor due to a surge voltage applied to the first power supply terminal and the second power supply terminal, and the characteristics of the parasitic bipolar transistor. It is set based on. In this semiconductor device, the power supply of the internal circuit is separated according to the parasitic capacitance value of the internal circuit, the current value flowing through the transistor, and the characteristics of the transistor.

According to the disclosed semiconductor device design method, it is possible to design a semiconductor device with a high breakdown voltage of the protection circuit.
According to the disclosed semiconductor device, the internal circuit can be protected by the protection circuit having a high breakdown voltage.

Hereinafter, an embodiment will be described with reference to the drawings.
As shown in FIG. 2, a design device 11 for designing a semiconductor device is composed of a general CAD (Computer Aided Design) device, and includes a central processing unit (hereinafter referred to as CPU) 12, a memory 13, a storage device 14, and a display device 15. The input device 16 and the drive device 17 are connected to each other via a bus 18.

  The CPU 12 executes a program using the memory 13 to realize necessary processing such as wiring design. The memory 13 stores programs and data necessary for providing various processes. The memory 13 usually includes a cache memory, a system memory, and a display memory.

  The display device 15 is used for displaying processing results, displaying a parameter input screen, and the like, and for this, a CRT, LCD, PDP or the like is used. The input device 16 is used for inputting requests, instructions, and parameters from the user, and for this, a keyboard and a mouse device (not shown) are used.

  The storage device 14 usually includes a magnetic disk device, an optical disk device, and a magneto-optical disk device. The storage device 14 stores program data and files 26 to 30 for the semiconductor device design process comprising steps 21 to 25 shown in FIG. 1, and the CPU 12 is a program responding to an instruction from the input device 16; Data is transferred to the memory 13 and executed.

  Program data executed by the CPU 12 is provided on the recording medium 19. The drive device 17 drives the recording medium 19 and accesses the stored contents. The CPU 12 reads program data from the recording medium 19 via the drive device 17 and installs it in the storage device 14.

  As the recording medium 19, any computer-readable recording such as magnetic tape (MT), memory card, flexible disk, optical disk (CD-ROM, DVD-ROM,...), Magneto-optical disk (MO, MD,...) Media can be used. The program and data described above can be stored in this recording medium 19 and loaded into the memory 13 for use as required.

  The recording medium 19 includes a medium and a disk device that record program data uploaded or downloaded via a communication medium. Furthermore, not only a recording medium that records a program that can be directly executed by a computer, but also a recording medium that records a program that can be executed once installed on another recording medium (such as a hard disk), or an encrypted program In addition, a recording medium on which a compressed program is recorded is also included.

Next, the design method implemented in the design apparatus 11 is demonstrated according to the flowchart of FIG.
The CPU 12 functions as means for designing a semiconductor device having a high withstand voltage of the power supply ESD by executing the processes of steps 21 to 25 shown in FIG.

  First, in step 21 (logic synthesis process), the CPU 12 stores the net list 28 created based on the library 26 and the design data 27 in the storage device 14 shown in FIG. The library 26 includes a database including a parasitic capacitance threshold value (hereinafter, a capacitance threshold value) of an internal circuit that lowers the breakdown voltage of the power supply ESD based on information of a plurality of macro cells and standard cells and a result calculated by simulation. It is. This capacitance threshold defines an upper limit (second threshold) and a lower limit (first threshold) of the range of the parasitic capacitance value of the internal circuit that lowers the breakdown voltage of the power supply ESD. This macro cell and standard cell information includes size, configuration, terminal location, and electrical characteristics. In addition, since the element characteristic parameters are different for each process technology, the range of the parasitic capacitance value that affects the withstand voltage of the power supply ESD corresponding to the process technology is different. Accordingly, the library 26 stores a capacity threshold value corresponding to each of the plurality of process technologies.

  The design data 27 describes circuit operations using, for example, a hardware description language. The net list 28 includes macro cells and standard cells constituting the circuit, and net information for connecting them. If the net list 28 has already been created, the process is executed from the next step 22.

  In step 22 (layout processing), the CPU 12 creates layout data 29 based on the layout conditions input from the input device 16, the net list 28 created in step 21, and the library 26. The layout data 29 reflects layout conditions such as LSI size, wiring width, wiring spacing, and the like. The layout position where the macro cell included in the library 26 is arranged, and the layout position of the wiring connecting the macro cell according to the net list 28. Is included.

An LSI formed by the layout data 29 is shown in FIG.
The LSI 30 is formed in a rectangular shape, and internal circuits 31 to 33 are formed in the center. A boundary between the internal circuits 31 to 33 is indicated by a one-dot chain line. That is, elements such as cells constituting the internal circuits 31 to 33 are formed in the region surrounded by the solid line and the alternate long and short dash line. In the present embodiment, the internal circuits 31 to 33 have different circuit scales (number of elements constituting the circuit), and the number of elements decreases in the order of the internal circuits 31, 32, and 33. The peripheral area of the LSI 30 is divided into areas 31 a to 33 a corresponding to the internal circuits 31 to 33.

  In the region 31 a, a plurality of pads 34 corresponding to the internal circuit 31 are formed along the periphery of the LSI 30. An I / O cell 35 is arranged in the I / O cell region between the internal circuit 31 and the pad 34. These I / O cells 35 are configured to be able to transmit signals between corresponding pads 34 and elements (not shown) constituting the internal circuit 31.

  Further, in the region 31a, a power supply pad serving as a first power supply terminal and a second power supply terminal is used to supply a high potential voltage and a low potential voltage as the first power supply voltage and the second power supply voltage to the elements of the internal circuit 31 and the like. 41 a and 41 b are formed around the LSI 30. The number of power supply pads 41a and 41b is set according to the power consumption of the internal circuit 31, and three sets of power supply pads 41a and 41b are formed in this embodiment. In the wiring layer above the I / O cell 35, power supply lines 42a and 42b as first power supply lines and second power supply lines for supplying a power supply voltage to the elements of the internal circuit 31 and the like along the periphery of the LSI 30. It is formed to extend. Each power supply wiring 42a, 42b is connected to a corresponding power supply pad 41a, 41b. In the I / O cell region, a plurality of protection circuits 43 connected to the power supply wirings 42a and 42b are formed. The protection circuit 43 is provided to protect the internal circuit 31 from a surge voltage caused by a power supply ESD or the like. In the present embodiment, the protection circuit 43 is a circuit having the same configuration as the protection circuit 94 of the conventional example shown in FIG.

  Similarly, a plurality of pads 36 and I / O cells 37 corresponding to the internal circuit 32 are formed in the region 32a. In addition, in the region 32a, the power supply pads 44a and 44b as the first power supply terminal and the second power supply terminal, the first power supply wiring, Power supply lines 45a and 45b as two power supply lines and a protection circuit 46 for protecting the internal circuit 32 are formed.

  Similarly, a plurality of pads 38 and I / O cells 39 corresponding to the internal circuit 33 are formed in the region 33a. In addition, in the region 33a, in order to supply a high potential voltage and a low potential voltage to the elements of the internal circuit 33, the power supply pads 47a and 47b as the first power supply terminal and the second power supply terminal, the first power supply wiring, Power supply wirings 48a and 48b as two power supply wirings and a protection circuit 49 for protecting the internal circuit 33 are formed.

  The regions 31a to 33a indicate correspondence between the internal circuits 31, 32, and 33 and the pads 34, 36, and 38. The regions 31a to 33a are shifted due to the configuration of the internal circuits 31, 32, and 33. Sometimes it is.

  In the wiring layer above the internal circuit 32, internal power supply wires 51a and 52a as first power supply wires electrically connected to the power supply wire 45a via contacts (not shown), and power supply wires 45b and contacts (not shown) are connected. Internal power supply wirings 51b and 52b are formed as second power supply wirings that are electrically connected to each other. The internal power supply wirings 51a and 51b represented by solid lines and the internal power supply wirings 52a and 52b represented by broken lines are formed in different wiring layers and are formed so as to extend along directions orthogonal to each other. The wirings 51a, 51b, 52a, 52b are electrically connected through contacts (not shown).

  Similarly, an internal power supply line (not shown) connected to the power supply lines 42a and 42b is formed in the wiring layer above the internal circuit 31, and the power supply lines 48a and 48b are connected to the wiring layer above the internal circuit 33. An internal power supply wiring (not shown) is formed.

  In step 23 (capacitance extraction process), the CPU 12 calculates a parasitic capacitance value of the semiconductor device 30 created from the layout data 29 created in step 22 based on the library 26. The parasitic capacitance value is a value of a capacitance existing between the power supply pads 41a and 41b, the power supply pads 44a and 44b, and the power supply pads 47a and 47b. The design apparatus 11 calculates the total value of the capacitance value between the power supply pads 41a and 41b, that is, the parasitic capacitance of the I / O cell 35 included in the internal circuit 31 and the region 31a and the parasitic capacitance between the power supply wirings 42a and 42b. calculate.

  Similarly, the design apparatus 11 determines the capacitance between the power supply pads 41a and 41b, that is, the capacitance value of the parasitic capacitance between the internal circuit 32 and the I / O cell 37 included in the region 32a and the parasitic capacitance between the power supply wirings 45a and 45b. Calculate the total value. Similarly, the design device 11 determines the capacitance between the power supply pads 41a and 41b, that is, the parasitic capacitance of the I / O cell 39 included in the internal circuit 33 and the region 33a and the parasitic capacitance between the power supply wirings 48a and 48b. Calculate the total value. Then, the design device 11 stores the calculated total value, that is, the parasitic capacitance value in the memory 13 or the storage device 14. The total value includes the parasitic capacitance between the power supply wirings on the internal circuits 31 to 33.

  In step 24 (separation determination process), the CPU 12 compares the parasitic capacitance value calculated in step 23 with the capacitance threshold value read from the library 26, and each of the power pads 41a, 41b, 44a, 44b, 47a, 47b. It is determined whether or not the power supply separation is necessary for the internal circuits 31, 32, 33 connected to. When the parasitic capacitance value does not fall within the capacitance threshold range, that is, when the parasitic capacitance value is not less than the upper limit of the capacitance threshold value or the parasitic capacitance value is not more than the lower limit of the capacitance threshold value, the design device 11 The internal circuit corresponding to the parasitic capacitance value is determined not to require power source separation, and the process is terminated.

  On the other hand, when the parasitic capacitance value is between the upper limit and the lower limit of the capacitance threshold value, the design apparatus 11 determines that power supply separation is necessary for the internal circuit corresponding to the parasitic capacitance value, and proceeds to step 25.

  In step 25 (separation layout process), the CPU 12 separates the power source of the block of the internal circuit determined to be required to be separated in step 24. At this time, the design apparatus 11 includes a first internal sub-circuit in which a predetermined number of elements (separation set number) are connected to the first sub power supply wiring, and a first internal circuit as a target internal circuit. Elements other than the sub circuit are separated from the power source to the second internal sub circuit connected to the second sub power source wiring. The number of separation settings is set in advance so that the parasitic capacitance value in the notified first internal subcircuit is smaller than the lower limit of the capacitance threshold value. The design apparatus 11 generates arrangement information of internal circuits (first internal subcircuit and second internal subcircuit) separated from each other. Furthermore, the design apparatus 11 generates arrangement information for arranging the protection circuits so that at least one protection circuit is connected in parallel to the internal circuit separated from the power source. The design apparatus 11 stores the generated arrangement information in the layout data 29.

  Then, the design apparatus 11 proceeds from step 24 to step 23, calculates the parasitic capacitance value for the second internal subcircuit in the same manner as described above (step 24), and determines the necessity of power source separation.

  In other words, when there is an internal circuit having a parasitic capacitance value corresponding to the capacitance threshold, the design apparatus 11 repeatedly executes steps 23 to 25 so that the internal circuit is less than the lower limit of the capacitance threshold. The power supply is separated into an internal sub-circuit having a small parasitic capacitance value. The capacitance threshold is set according to the breakdown voltage of the protection circuit, and an internal circuit having a parasitic capacitance value between the lower limit and the upper limit of the capacitance threshold lowers the breakdown voltage of the protection circuit. Therefore, the internal circuit is connected to each internal sub circuit rather than the protection circuit connected to the target internal circuit by separating the power source into the internal sub circuit having a parasitic capacitance value smaller than the lower limit of the capacitance threshold. Increase the breakdown voltage of the protection circuit.

Next, details of each step will be described.
First, the setting of the capacity threshold value will be described.
For the semiconductor device as shown in FIG. 10A, the capacitance value of the parasitic capacitance C91 of the internal circuit 91 of a predetermined technology is changed in a predetermined step from a predetermined range (for example, 1 pF to 40 nF), and the layout of the respective capacitance values. A simulation (for example, a mixed mode of H-Spice Simulation) is performed on the data, and a current value flowing between the power supply pads 92a and 92b is calculated. 6 to 8 show simulation results in the internal circuit 91 of 130 nm technology.

  FIG. 6A shows the IV characteristics when ESD (for example, 2000 V under the conditions of the human body model) is applied between the power supply pads 92a and 92b for the internal circuit 91 whose capacitance value is set to 1 pF. FIG. 6B shows a change in current over time, the solid line indicates the amount of current flowing through the transistor T92, the alternate long and short dash line indicates the amount of current flowing through the parasitic capacitance C91, and the broken line indicates the total amount of current. In FIG. 6B, since the total amount of current and the amount of current flowing through the transistor T92 are substantially equal, the broken line is superimposed on the solid line.

  FIGS. 7A and 7B show characteristics in the internal circuit 91 in which the capacitance value is set to 100 pF, and FIGS. 8A and 8B show characteristics in the internal circuit 91 in which the capacitance value is set to 40 nF. In FIG. 8B, since the total amount of current and the amount of current flowing through the parasitic capacitance C91 are substantially equal, only the broken line is shown.

  In FIG. 7B, a one-dot chain line above the reference line indicates the amount of current flowing from the power supply pads 92a and 92b toward the parasitic capacitance C91, and a one-dot chain line below the reference line is from the parasitic capacitance C91. Indicates the amount of current that flows backward. Due to the current flowing backward from the parasitic capacitance C91, the amount of change in the current flowing through the transistor T92 is large, that is, a large inrush current flows through the transistor T92.

  FIG. 9 shows the result of device simulation, and shows temporal changes in the current flowing through the transistor T92 when the parasitic capacitance value is changed. Curves 71, 72, 73, and 74 show temporal changes when the parasitic capacitance values are 10 pF, 100 pF, 1 nF, and 10 nF, respectively. For example, the maximum value (peak value) of the current amount in the curve 74 is about 7 amperes (A). A capacitance value range in which the peak value of the amount of current flowing through the transistor T92 is a predetermined value (for example, about 1.8 A) or less is defined as a capacitance threshold value. A predetermined value (about 1.8 A) for setting this range is set according to the characteristics of the parasitic bipolar transistor T92. The PN junction of the transistor T92 is thermally destroyed by a current of about 1.8 A or more. Accordingly, the predetermined value is set so that the amount of current does not damage the transistor T92. The above shows an example of the setting in the 130 nm technology, and it goes without saying that the setting value varies depending on the circuit configuration of the protection circuit, the shape (technology) of the transistor T92, and the like.

Next, the power source separation process in step 25 shown in FIG. 1 will be described.
As an example, processing in the semiconductor device 30 shown in FIG. 3 when the parasitic capacitance value between the power supply pads 44a and 44b is within the capacitance threshold range will be described. Here, only the parasitic capacitance of the internal circuit 32 is targeted in order to simplify the description.

  First, the design apparatus 11 divides the internal circuit 32 into a first internal subcircuit 32a and a second internal subcircuit 32b as shown in FIG. 4A based on a predetermined separation setting value. . FIG. 4A shows a boundary between the first internal sub-circuit 32a and the second internal sub-circuit 32b by an alternate long and short dash line Lb. The first internal subcircuit 32a includes a predetermined number of elements, and the second internal subcircuit 32b includes elements other than elements included in the first internal subcircuit 32a among elements constituting the internal circuit 32. Including.

  Next, the design apparatus 11 divides the power supply wiring corresponding to the first and second internal subcircuits 32a and 32b. That is, as shown in FIG. 4A, the design apparatus 11 supplies power supply wirings 45a and 45b for supplying a power supply voltage to the internal circuit 32, as shown in FIG. 4B, and the first internal subcircuit 32a. Are divided into power supply wirings 81a and 81b corresponding to, and power supply wirings 82a and 82b corresponding to the second internal subcircuit 32b. Furthermore, as shown in FIG. 4A, the design apparatus 11 converts the internal power supply wirings 51a and 52a extending over the two internal sub circuits 32a and 32b to the first internal sub circuit as shown in FIG. The internal power supply lines 83a and 84a on the circuit 32a and the internal power supply lines 83b and 84b on the second internal subcircuit 32b are divided.

  Next, the design apparatus 11 arranges a power supply pad and a protection circuit as necessary. That is, as shown in FIG. 4A, the power supply pads 44a and 44b for supplying the power supply voltage to the internal circuit 32 are connected to the power supply wirings 81a and 81b after the power supply separation as shown in FIG. 4B. ing. Further, a protection circuit 46 formed below these wirings is connected to both the power supply wirings 81a and 81b. On the other hand, the divided power supply wirings 82a and 82b are not connected to the power supply pad and are not connected to the protection circuit. For this reason, the second internal sub-circuit 32b to which the power supply wirings 82a and 82b are connected does not operate.

  Therefore, as shown in FIG. 5B, the design apparatus 11 arranges the power supply pads 85a and 85b in the vacant area and connects to the power supply wirings 82a and 82b with respect to these power supply wirings 82a and 82b. Furthermore, the design apparatus 11 arranges a protection circuit 86 connected between the power supply wires 82a and 82b.

  The above processing is represented as a circuit block as shown in FIG. That is, as shown in FIG. 5A, the design apparatus 11 includes an internal circuit 32 between the power supply wires 45a and 45b connected to the power supply pads 44a and 44b, as shown in FIG. Dividing into one internal sub-circuit 32a and second internal sub-circuit 32b. Furthermore, the design apparatus 11 divides the power supply wires 45a and 45b into power supply wires 81a and 81b corresponding to the internal sub circuit 32a and power supply wires 82a and 82b corresponding to the internal sub circuit 32b.

  Next, the design apparatus 11 calculates a parasitic capacitance value in step 23 shown in FIG. 1 for the divided second internal sub-circuit 32b, and compares it with a capacitance threshold value. The design device 11 calculates a parasitic capacitance value between the power supply pads 85a and 85b, and compares the parasitic capacitance value with a capacitance threshold value. Since the parasitic capacitance value of the second internal subcircuit 32b is smaller than that of the first internal subcircuit 32a, the design apparatus 11 determines that the second internal subcircuit 32b does not need to be divided and ends the process. To do.

As described above, according to the present embodiment, the following effects can be obtained.
(1) In the design process of the semiconductor device including the internal circuits 31 to 33 corresponding to the functions, the design apparatus 11 includes power supply pads 41a, 41b, 44a, 44b, 47a, and 47b to which the internal circuits 31 to 33 are connected. The parasitic capacitance value is calculated, and this parasitic capacitance value is compared with the capacitance threshold value stored in the library 26. Then, when the parasitic capacitance value is within the capacitance threshold range, the design device 11 separates the power source of the internal circuit 32 having the parasitic capacitance value. As a result, by reducing the amount of current that flows back from the parasitic capacitance to the protection circuit 46 due to the parasitic capacitance of the internal circuit 32, the protection circuit 46 is less likely to be damaged and the breakdown voltage of the protection circuit 46 against surge voltage is increased. be able to.

It is a flowchart which shows the outline of a design method. It is a schematic block diagram of a design apparatus. 1 is a schematic plan view of an LSI (semiconductor device). (A) (b) is explanatory drawing of a power supply isolation | separation process. (A) (b) is explanatory drawing of a power supply isolation | separation process. (A) (b) is explanatory drawing which shows the result of simulation. (A) (b) is explanatory drawing which shows the result of simulation. (A) (b) is explanatory drawing which shows the result of simulation. It is explanatory drawing which shows the result of device simulation. (A) is explanatory drawing of a semiconductor device, (b) is a circuit diagram of a protection circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Design apparatus 26 Library 30 Semiconductor device 31-33 Internal circuit 44a 1st power supply pad 44b 2nd power supply pad 45a 1st power supply wiring 45b 2nd power supply wiring 46 Protection circuit

Claims (8)

A second power supply connected between the first power supply terminal and the second power supply terminal, supplied with a first power supply voltage via a first power supply wiring connected to the first power supply terminal, and connected to the second power supply terminal. An internal circuit to which a second power supply voltage is supplied via wiring; and a protection circuit that is connected in parallel with the internal circuit and that conducts when an electrostatic discharge occurs on the internal circuit and protects the internal circuit from a surge current; A method for designing a semiconductor device comprising:
Calculating a parasitic capacitance value between the first power supply terminal and the second power supply terminal;
The power supply is separated from the internal circuit so that the parasitic capacitance value is smaller than a predetermined capacitance threshold value.
A method for designing a semiconductor device. A second power supply connected between the first power supply terminal and the second power supply terminal, supplied with a first power supply voltage via a first power supply wiring connected to the first power supply terminal, and connected to the second power supply terminal. An internal circuit to which a second power supply voltage is supplied via wiring; and a protection circuit that is connected in parallel with the internal circuit and that conducts when an electrostatic discharge occurs on the internal circuit and protects the internal circuit from a surge current; A method for designing a semiconductor device comprising:
Calculating a parasitic capacitance value between the first power supply terminal and the second power supply terminal;
Comparing the parasitic capacitance value with a capacitance threshold;
Based on the comparison result, the internal circuit of the parasitic capacitance value within the range set by the capacitance threshold is separated from the power source.
A method for designing a semiconductor device. The protection circuit includes a power clamp formed of an N-channel MOS transistor having a source and a drain connected to the first power supply wiring and the second power supply wiring, respectively, and a gate connected to a power supply wiring to which a low potential voltage is supplied. Circuit,
The capacitance threshold is based on the amount of current flowing through the parasitic bipolar transistor of the N-channel MOS transistor due to the surge current applied to the first power supply terminal and the second power supply terminal, and the characteristics of the parasitic bipolar transistor. Is set,
The method for designing a semiconductor device according to claim 1, wherein: A second power supply connected between the first power supply terminal and the second power supply terminal, supplied with a first power supply voltage via a first power supply wiring connected to the first power supply terminal, and connected to the second power supply terminal. An internal circuit to which the second power supply voltage is supplied via the wiring;
A protection circuit that is connected in parallel with the internal circuit and that conducts when an electrostatic discharge occurs on the internal circuit and protects the internal circuit from surge current;
A semiconductor device comprising:
The internal circuit is power-separated so that a parasitic capacitance value between the first power supply terminal and the second power supply terminal is smaller than a predetermined capacitance threshold value.
A semiconductor device. A second power supply connected between the first power supply terminal and the second power supply terminal, supplied with a first power supply voltage via a first power supply wiring connected to the first power supply terminal, and connected to the second power supply terminal. An internal circuit to which the second power supply voltage is supplied via the wiring;
A protection circuit that is connected in parallel with the internal circuit and that conducts when an electrostatic discharge occurs on the internal circuit and protects the internal circuit from surge current;
A semiconductor device comprising:
The internal circuit has a second parasitic capacitance value between the first power supply terminal and the second power supply terminal that is lower than a first threshold value or higher than the first threshold value. Is higher than the threshold of
A semiconductor device. A second power supply connected between the first power supply terminal and the second power supply terminal, supplied with a first power supply voltage via a first power supply wiring connected to the first power supply terminal, and connected to the second power supply terminal. An internal circuit to which the second power supply voltage is supplied via the wiring;
A protection circuit that is connected in parallel with the internal circuit and that conducts when an electrostatic discharge occurs on the internal circuit and protects the internal circuit from surge current;
A semiconductor device comprising:
The configuration of the internal circuit is set so that the parasitic capacitance value between the first power supply terminal and the second power supply terminal does not include a value between the first threshold value and the second threshold value which are different from each other. Become,
A semiconductor device. The protection circuit includes a power clamp formed of an N-channel MOS transistor having a source and a drain connected to the first power supply wiring and the second power supply wiring, respectively, and a gate connected to a power supply wiring to which a low potential voltage is supplied. Circuit,
The semiconductor device according to claim 4, wherein the semiconductor device is a semiconductor device. The capacitance threshold is based on the amount of current flowing through the parasitic bipolar transistor of the N-channel MOS transistor due to the surge current applied to the first power supply terminal and the second power supply terminal, and the characteristics of the parasitic bipolar transistor. Is set,
The semiconductor device according to claim 7.

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