JP2009200690A - Design method of semiconductor integrated circuit and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a design method of a semiconductor integrated circuit, minimizing the time and labor required for a through current measure and reducing power consumption. <P>SOLUTION: In a step S1, among a plurality of cells inside a power interruption object unit 11, a first power interruption requiring cell which requires power interruption is recognized. Then, in a step S2, a power interruption requiring signal route reaching the first power interruption requiring cell, tracing back in an input direction from a D flip-flop 1 is searched. Thereafter, in a step S3, a cell on the power interruption requiring signal route searched in the step S2 other than the first power interruption requiring cell recognized in the step S1 is set as a second power interruption requiring cell. Finally, in a step S4, a control circuit for interruption for the first and second power interruption requiring cells is generated. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for designing a semiconductor integrated circuit including a cell having a power cutoff function, and a semiconductor integrated circuit.

  When designing a semiconductor integrated circuit composed of a plurality of cells, a method of adopting a fine grain type power shut-off method can be considered in order to reduce leakage current during standby of the cells. Note that the fine-grain type power supply cutoff means that a single power supply cutoff switch is provided for each cell (logic gate). However, when the fine grain type power supply cutoff method is adopted, there is a problem that the number of control elements for power supply cutoff increases.

  In contrast to the fine grain type power shutdown method, there is a coarse grain type power shutdown method that performs power shutdown in units of circuit blocks including a predetermined number of cells. This method has the characteristics that the standby power is smaller and the circuit area is easily reduced as compared with the fine-grain type. Note that the coarse-grain type power cutoff method is disclosed in Non-Patent Document 1, for example.

  However, in the case of the coarse grain type power shut-off method, there is a problem in that power shut-off control cannot be performed for individual cells.

  Non-Patent Document 2 discloses a technique proposed as one method for solving these problems. This technique is based on an approach of making redundant circuits as unnecessary as possible by making the control circuit into a hierarchical structure.

  In addition, in the case of adopting either the fine particle size type or the coarse particle size type power cut-off method, when a certain block (cell) is considered, a structure in which a power cut-off structure is added to all cells is adopted.

[DAC 2006] “TSMC and ARM collaborate on 65nm test chip, power consumption is halved during operation, 1/10 during standby”, Internet <URL: http://techon.nikkeibp.co.jp/ article / NEWS / 20060726/119518 /> Yusuke Ogino et al., "Hierarchical multi-division power cutoff circuit technology that realizes low power for 90nm mobile SoC", IEICE technical report. ICD, Integrated Circuits Vol.106, No.71 (20060518) pp. 25-30

  Since the dynamic charge / discharge power can be reduced by not operating the cell, the purpose of the power shutoff method is mainly to reduce the leakage power. For this reason, it is necessary to solve the trade-off between the power generated in the circuit required for controlling the power shutdown and the leakage power that can be reduced by shutting off the power. For this purpose, power-off control in a fine granularity type is conceivable in which power is shut down only for cells having a large leak current, and power is not shut off for cells having a small leak current.

  In this case, the first type cell having the power cutoff function and the second type cell not having the power cutoff function coexist, and signal exchange from the first type cell to the second type cell is performed. Will increase. Considering signal propagation from the first type cell to the second type cell in the situation where the first type cell is shutting off the power, the output signal of the first type cell at the time of power off is indefinite. Therefore, there is a problem that the through current flows in the second type cell, and a countermeasure for the through current is required to avoid this problem.

  FIG. 13 is a circuit diagram showing a circuit configuration that requires countermeasures for through current. As shown in FIG. 5A, this circuit includes inverters G50 and G60 connected in series.

  As shown in FIG. 5B, the inverter G50 is composed of a PMOS transistor Q51, NMOS transistors Q52 and Q53 connected in series between the power supply voltage Vdd and the ground level. The gate electrodes (input portions) of the PMOS transistor Q51 and the NMOS transistor Q52 are connected in common, and the drain of the PMOS transistor Q51 (Q52) is the output portion.

  NMOS transistor Q53 is interposed between the source of NMOS transistor Q52 and the ground level, and receives a control signal SC10 from the outside at its gate electrode. Therefore, by applying the “L” control signal SC10, the NMOS transistor Q53 is turned off, so that the inverter G50 can be forcibly set to the power-off state. As described above, since the NMOS transistor Q53 functions as the power cutoff switch SW11, the inverter G50 is a first type cell having a power cutoff function.

  On the other hand, the inverter G60 includes a PMOS transistor Q61 and an NMOS transistor Q62 connected in series between the power supply voltage Vdd and the ground level. The node N60 which is the gate electrode (input part) of the PMOS transistor Q61 and the NMOS transistor Q62 is commonly connected to the node N50 which is the drain of the PMOS transistor Q51 (the output part of the inverter G50), and the drain of the PMOS transistor Q61 (Q62) is connected. Output section. Since the inverter G60 does not have a transistor corresponding to the NMOS transistor Q53, the inverter G60 is a second type cell having no power cutoff function.

  As shown in FIG. 13, consider a circuit configuration in which an input part of an inverter G60 without a power shutoff function is connected to an output part of an inverter G50 having a power shutoff function. In this circuit configuration, when the inverter G50 is in a power cutoff state (NMOS transistor Q53 is in an off state), the node N50 is in a floating state, and its potential is indefinite.

  Therefore, an indefinite potential of the node N50 appears at the node N60, which is the input part of the inverter G60, and both the PMOS transistor Q61 and the NMOS transistor Q62 become conductive, and a through current may flow through the inverter G60. Therefore, it is necessary to take measures against through current to avoid the through current. Thus, when there is a combination of the first type cell having the power cutoff function and the second type cell not having the power cutoff function for receiving the output of the first type cell, the second type of the latter stage is provided. This cell becomes a cell requiring a through current.

  Although countermeasures for shoot-through current are necessary in any case, the ratio of cells requiring shoot-through current increases is high if the power shut-off function is selectively applied only to cells with high leakage current. As a result, there is a problem in that the effort for countermeasures for the through current becomes enormous.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a method for designing a semiconductor integrated circuit that minimizes the effort of measures against through current and reduces power consumption. .

  According to one embodiment of the present invention, there is provided a design method of a semiconductor integrated circuit including a flip-flop and a power shut-off target unit having a plurality of cells arranged in the preceding stage of the flip-flop.

  In this design method, first, a required power shutoff signal path is selected from at least one signal path having a flip-flop as an end point in the power shutoff target section. A predetermined number of cells arranged continuously from the flip-flop among the cells existing on the power-required power-off signal path are set as power-required cells that require power-off. After that, a shutoff control circuit is set for enabling the power shutoff cell to be forcibly shut off by an external signal.

  According to the method for designing a semiconductor integrated circuit according to this embodiment, a power-off signal path is selected from at least one signal path having a flip-flop as an end point in a power-off target unit, and exists on the power-off signal path Among the cells to be operated, a predetermined number of cells arranged continuously from the flip-flop are set as power-off required cells that require power-off.

  Therefore, according to this embodiment, the first type cell having the power cutoff function and the second type cell not having the power cutoff function are mixed in the power cutoff target unit, and the first type cell and the relevant type A semiconductor integrated circuit having no combination with the second type cell that receives the output of the first type cell at the input can be obtained.

  As a result, this embodiment has an effect that it is possible to design a semiconductor integrated circuit that minimizes the effort of countermeasures for through current and reduces power consumption.

<Embodiment 1>
A method for designing a semiconductor integrated circuit according to the first embodiment is a method for designing a semiconductor integrated circuit including a sequential circuit and a power cutoff target portion having a plurality of cells (logic gates). It is assumed that it exists.

  FIG. 1 is a flowchart showing a method for designing a semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing a circuit example of the power shutoff target unit 11 designed by the design method of the first embodiment.

  As shown in FIG. 2, a D flip-flop 1 that is a sequential circuit and a plurality of cells (NAND gate G1, inverter G11, NAND gate G12, inverter G13, NAND gate G21, inverter G22) provided in the preceding stage of the D flip-flop 1 And G23) become the power shutoff target unit 11.

  The output of the NAND gate G1 is connected to the D input of the D flip-flop 1. The D flip-flop 1 has a Q output and a clock input clk. The output of the inverter G11 is connected to the first input of the NAND gate G1, the output of the NAND gate G12 is connected to the second input, and the inverter G13 is connected to the third input. The output of the NAND gate G21 is connected to one input of the NAND gate G12, and the output of the inverter G22 is connected to the other input. The output of the inverter G23 is connected to the input of the inverter G13.

  Hereinafter, the processing procedure of the design method according to the first embodiment for the power shutoff target unit 11 shown in FIG. 2 will be described with reference to FIG.

  First, in step S <b> 1, a first power-required cell that needs to be powered off among a plurality of cells in the power-off target unit 11 is recognized. In the circuit example shown in FIG. 2, the inverter G <b> 13 and the inverter G <b> 22 are recognized as the first power-required cutoff cell (hatched hatching) in the power cutoff target unit 11. For example, a high-speed operation cell with a large leakage current is selected as the first power-supply cutoff cell.

  Next, in step S2, a power required cutoff signal path is searched from the D flip-flop 1 that is a sequential circuit back to the first power required cutoff cell in the input direction. In the circuit example shown in FIG. 2, the signal path R1 from the inverter G22 to the D input of the D flip-flop 1 through the NAND gate G12 and the NAND gate G1, and the D flip-flop 1 from the inverter G23 through the inverter G13 and the NAND gate G1. The signal path R2 leading to the D input becomes a power-required cutoff signal path.

  After that, in step S3, cells other than the first power-source cutoff cell recognized in step S1 among the cells on the power-source cutoff signal path searched in step S2 are set as second power source cutoff cells. In the circuit example shown in FIG. 2, the NAND gate G12 and the NAND gate G1 on the signal path R1 are set as the second power source cutoff cell, and the NAND gate G1 on the signal path R2 is the second power source cutoff cell. Set as (sandy hatching). Since the NAND gate G1 exists on the signal paths R1 and R2, it is set as a second power-required cell that overlaps.

  Finally, in step S4, a cutoff control circuit is generated for the first and second power source cutoff cells.

  FIG. 3 is a circuit diagram showing a first configuration example of the cutoff control circuit designed by the semiconductor integrated circuit design method of the first embodiment. As shown in the figure, a shut-off control circuit is provided for inverters G41 to G43, which are power source shut-off cells.

  As shown in the figure, the inverter G41 includes a PMOS transistor Q1, NMOS transistors Q2 and Q3 connected in series between the power supply voltage Vdd and the ground level. The gate electrodes (input portions) of the PMOS transistor Q1 and the NMOS transistor Q2 are connected in common, and the drain of the PMOS transistor Q1 (Q2) is the output portion.

  An NMOS transistor Q3 provided as a cutoff control circuit is inserted between the source of the NMOS transistor Q2 and the ground level, and receives a control signal SC1 from the outside via the buffer gate G31 at the gate electrode.

  The inverter G42 includes a PMOS transistor Q4 and NMOS transistors Q5 and Q6 connected in series between the power supply voltage Vdd and the ground level. The gate electrodes (input parts) of the PMOS transistor Q4 and the NMOS transistor Q5 are connected in common, and the drain of the PMOS transistor Q4 (Q5) serves as the output part.

  An NMOS transistor Q6 provided as a cutoff control circuit is interposed between the source of the NMOS transistor Q5 and the ground level, and receives a control signal SC1 from the outside via the buffer gate G31 at the gate electrode.

  Further, the inverter G43 includes a PMOS transistor Q7 and NMOS transistors Q8 and Q9 connected in series between the power supply voltage Vdd and the ground level. The gate electrodes (input portions) of the PMOS transistor Q7 and the NMOS transistor Q8 are connected in common, and the drain of the PMOS transistor Q7 (Q8) is the output portion.

  An NMOS transistor Q9 provided as a cutoff control circuit is inserted between the source of the NMOS transistor Q8 and the ground level, and receives a control signal SC1 from the outside via the buffer gate G32 at the gate electrode.

  Therefore, the inverters G41 to G43 can be forcibly set to the power cut-off state by applying the “L” control signal SC1 and turning off all the NMOS transistors Q3, Q6, and Q9. Thus, since the NMOS transistors Q3, Q6 and Q9 function as the power cutoff switches SW1, SW2 and SW3, the inverters G41 to G43 are cells having a power cutoff function.

  As described above, in the circuit example shown in FIG. 3, for the inverters G41 to G43 which are power source cutoff cells, a process for generating a cutoff control circuit including NMOS transistors Q3, Q6, Q9 and buffer gates G31, G32 is performed. The process is step S4. As described above, the cutoff control circuit can forcibly put the inverters G41 to G43, which are power cutoff cells, into a power cutoff state by the control signal SC1.

  FIG. 4 is a circuit diagram showing a second configuration example of the cutoff control circuit designed by the semiconductor integrated circuit design method of the first embodiment. As shown in the figure, a shutoff control circuit is provided for the inverters G41 to G43.

  NMOS transistor Q9 provided as a cutoff control circuit receives the output of AND gate G34 at its gate electrode, and AND gate G34 receives control signal SC1 at one input and control signal SC2 at the other input. Other configurations are the same as the configurations shown in FIG.

  In such a configuration, the control signal SC1 of “L” is applied, the output of the AND gate G34 is set to “L”, and all of the NMOS transistors Q3, Q6 and Q9 are turned off, whereby each of the inverters G41 to G43 is turned on. It can be forcibly set to the power-off state.

  Further, the control signal SC1 of “H” and the control signal SC2 of “L” are applied, the output of the AND gate G34 is selectively set to “L”, and among the NMOS transistors Q3, Q6, Q9, the NMOS transistor Q9. By selectively turning off only, it is possible to forcibly set only the inverter G43 among the inverters G41 to G43 to the power-off state.

  As described above, in the circuit example shown in FIG. 4, for the inverters G41 to G43 that are power source cutoff cells, a cutoff control circuit composed of NMOS transistors Q3, Q6, Q9, buffer gate G31, and AND gate G34 is generated. The process is the process of step S4.

  Note that it is not necessary to provide a power cutoff function in the D flip-flop 1 itself, which is a sequential circuit. Hereinafter, this point will be described in detail.

  FIG. 5 is an explanatory circuit diagram showing that it is not necessary to provide a power shut-off function in the sequential circuit itself. Consider a configuration in which a latch cell 20, which is one of the sequential circuits of an inverter G50, which is a power-requiring cell, is connected as shown in FIG.

  The latch cell 20 includes NMOS transistors Q71 and Q72 and inverters G60 and 61, and constitutes a latch unit by loop connection by the inverters G60 and G61. The NMOS transistor Q71 functions as an input switch, and the NMOS transistor Q72 functions as an output switch.

  As shown in FIG. 13 (b), the internal configuration of the inverter G50 is composed of a PMOS transistor Q51, NMOS transistors Q52 and Q53 connected in series between the power supply voltage Vdd and the ground level, as in the configuration shown in FIG. The NMOS transistor Q53 functions as the power cutoff switch SW11.

  On the other hand, the internal configuration of the inverter G60 includes a PMOS transistor Q61 and an NMOS transistor Q62 connected in series between the power supply voltage Vdd and the ground level, as in the configuration shown in FIG.

  However, in the latch cell 20, an NMOS transistor Q71 is interposed between the node N50 of the inverter G50 and the input part of the inverter G60, and functions as an inter-cell cutoff switch SW12. In FIG. 5B, the internal configuration of the inverter G61 and the NMOS transistor Q72 shown in FIG. 5A are not shown.

  Therefore, when the NMOS transistor Q53 is in the OFF state, the NMOS transistor Q71 is set in the OFF state at the same time, thereby reliably preventing the potential of the indefinite state of the node N50 from being applied to the node N60 that is the input part of the inverter G60. can do.

  On the other hand, since the node N60 has a stable potential set by the loop connection of the inverters G60 and G61, the potential of the node N60 does not become unstable even when the NMOS transistor Q71 is turned off.

  As described above, since the sequential circuit such as the D flip-flop 1 can originally take measures against the through current, it is not necessary to provide a special power cutoff function.

  As described above, the semiconductor integrated circuit design method according to the first embodiment has the signal path that requires the signal path starting from the first power source cutoff cell and the sequential circuit that does not require any through-current countermeasures as the end point. All of the cells other than the first required cell that are selected as the path and exist on the required power cutoff signal path are set as second required power cutoff cells.

  That is, in the semiconductor integrated circuit design method of the first embodiment, the power cutoff target unit 11 selects a power required cutoff signal path from at least one signal path having the D flip-flop 1 as an end point, and a plurality of cells require a power supply required. Among the cells existing on the cutoff signal path, a predetermined number of cells arranged continuously from the D flip-flop 1 are set as the power cutoff cells that require power shutdown.

  As a result, according to the design method of the semiconductor integrated circuit of the first embodiment, the first type cell having the power cutoff function and the second type cell not having the power cutoff function are mixed in the power cutoff target unit 11. In addition, a semiconductor integrated circuit having no combination of the first type cell and the second type cell receiving the output of the first type cell at the input can be obtained. That is, the semiconductor integrated circuit designed by the design method of the first embodiment eliminates the above combinations that cause a through current, and does not have the power shutoff function with the first type cell having the power shutoff function. This is a semiconductor integrated circuit in which the second type cell is mixed in the power cutoff target unit 11.

  As described above, according to the semiconductor integrated circuit design method of the first embodiment, only the first and second power-required cells that are highly required to be shut down are selectively selected from the plurality of cells in the power shut-off target unit. By setting the power supply to be cut off, there is an effect that it is possible to obtain a semiconductor integrated circuit that minimizes the trouble of measures against through current and reduces power consumption.

<Embodiment 2>
The design method of the semiconductor integrated circuit according to the second embodiment is a design method of a semiconductor integrated circuit including a sequential circuit and a power-off target part having a plurality of cells (logic gates), as in the design method according to the first embodiment. It is assumed that the sequential circuit exists in the subsequent stage of a plurality of cells.

  FIG. 6 is a flowchart showing a method for designing a semiconductor integrated circuit according to the second embodiment of the present invention. FIG. 7 is a circuit diagram showing a circuit example of the power shutoff target unit 12 designed by the design method of the second embodiment.

  As shown in FIG. 7, a D flip-flop 2 that is a sequential circuit and a plurality of cells (NAND gate G2, inverter G14, NAND gate G15, inverter G16, NAND gate G24, inverter G25) provided in the preceding stage of the D flip-flop 2 And G26), the combinational circuit group 15 and the input unit 10 become the power cutoff target unit 12.

  The output of the NAND gate G2 is connected to the D input of the D flip-flop 2. The D flip-flop 2 has a Q output and a clock input clk. The output of the inverter G14 is connected to the first input of the NAND gate G2, the output of the NAND gate G15 is connected to the second input, and the inverter G16 is connected to the third input. The output of the NAND gate G24 is connected to one input of the NAND gate G15, and the output of the inverter G25 is connected to the other input. The output of the inverter G26 is connected to the input of the inverter G16.

  Further, a combinational circuit group 15 is provided in the preceding stage of the inverter G14, NAND gate G24, inverter G25, and inverter G26, and the combinational circuit group 15 is connected to the input unit 10.

  Hereinafter, the design method of the second embodiment for the power shutoff target unit 12 shown in FIG. 7 will be described with reference to FIG.

  First, in step S11, all the cells in the power shutdown target unit 12 are temporarily set as temporary power shutdown unnecessary cells that do not require power shutdown. In the circuit example shown in FIG. 7, NAND gates G2, G15, G24, inverters G14, G16, G25, G26 and all cells (not shown) in the combinational circuit group 15 are provisionally set as temporary power supply unnecessary cutoff cells. . A temporary power supply unnecessary cutoff cell corresponds to a cell having a relatively low speed and a relatively small leakage current during standby.

  Next, in step S12, it is necessary to increase the speed of the signal path that is recognized as the timing critical path by the timing verification among the signal paths from the sequential circuit D flip-flop 2 to the input unit 10 in the input direction. Recognized as a power cutoff signal path. The timing critical path corresponds to a signal path that needs to be speeded up, such as a signal path in which a timing error occurs due to timing verification, or a signal path that is determined to be difficult to satisfy timing due to insufficient margin.

  In the circuit example shown in FIG. 7, the signal path R3 from the input unit 10 to the D input of the D flip-flop 2 through the combinational circuit group 15, the inverter G25, the inverter G15, and the NAND gate G2, and the combinational circuit group from the input unit 10 15, a signal path R4 that reaches the D input of the D flip-flop 2 through the inverter G26, the inverter G16, and the NAND gate G2 is a power-off signal path.

  After that, in step S13, each power source cutoff signal path is traced back from the D flip-flop 2, and cells on the power source cutoff signal path are sequentially supplied to the temporary power source until the power source cutoff signal path satisfies a predetermined speed-up requirement. Set by replacing the cell that does not need to be shut down with the cell that requires power shutoff. Note that the predetermined speed-up requirement in the second embodiment may be a condition such that the signal propagation time of the power cutoff signal path can be speeded up until it is determined that it does not correspond to the timing critical path. Further, the power-required cell requires a cell that operates at a higher speed than the temporary power supply unnecessary cutoff cell and has a larger leakage current during standby than the temporary power supply unnecessary cutoff cell when the power supply is not shut down.

  Then, when the predetermined speed-up requirement is satisfied, the sequential setting of the power cutoff cells is finished. With the completion of step S13, the temporary power source unnecessary cutoff cell that has not been replaced with the power source cutoff cell is finally determined as the determined power source unnecessary cutoff cell.

  In the circuit example shown in FIG. 7, the NAND gate G2, the NAND gate G15, and the NAND gate G15 on the signal path R3 are sequentially set as the power-source cutoff cells (sandy hatching). It shows that the sequential setting process has been completed.

  On the other hand, the NAND gate G2 and the inverter G16 on the signal path R4 are set as the power-off cells. At the stage of the inverter G26, the sequential setting process of the power cutoff cells is completed. Therefore, the power shutoff function is not set for the cells in the combination circuit group 15 on the signal path R4 arranged upstream of the inverter G26 and the inverter G26. Note that the NAND gate G2 is redundantly set as a second power-off cell.

  Finally, in step S14, a shutoff control circuit for the power shutoff cell is generated. The shutoff control circuit process is performed in the same manner as the process in step S4 of the first embodiment.

  As described above, in the semiconductor integrated circuit design method of the second embodiment, the timing critical path that needs to be speeded up is required among the signal paths that end in the sequential circuit that does not require countermeasures for through current. The cells that are selected as the cutoff signal path and are present on the required power cutoff signal path are sequentially set as the required power cutoff cells until a predetermined speed-up requirement is satisfied.

  That is, in the semiconductor integrated circuit design method of the second embodiment, the power cutoff target unit 12 selects a power cutoff signal path from at least one signal path having the D flip-flop 2 as an end point, and a plurality of cells require a power supply. Among the cells existing on the cutoff signal path, a predetermined number of cells arranged continuously from the D flip-flop 2 are set as the power cutoff cells that require power shutdown.

  As a result, according to the semiconductor integrated circuit design method of the second embodiment, the first type cell having the power cutoff function and the first type cell having the power cutoff function are eliminated as in the case of the first embodiment. A semiconductor integrated circuit in which two types of cells are mixed in the power cutoff target unit 12 can be obtained.

  As described above, according to the semiconductor integrated circuit design method of the second embodiment, among the plurality of cells of the power cutoff target part, the cells selectively on the power cutoff signal path that is highly required to shut off the power are selected. By setting the power supply to be able to be cut off, it is possible to obtain a semiconductor integrated circuit in which the effort for countermeasures for through current is minimized and the power consumption is reduced.

<Embodiment 3>
The design method of the semiconductor integrated circuit according to the third embodiment is similar to the design method according to the first and second embodiments. The semiconductor integrated circuit includes a sequential circuit and a power cutoff target unit having a plurality of cells (logic gates). In this design method, it is assumed that the sequential circuit exists in the subsequent stage of a plurality of cells.

  FIG. 8 is a flowchart showing a method for designing a semiconductor integrated circuit according to the third embodiment of the present invention. 9 and 10 are circuit diagrams showing circuit examples of the power shutoff target unit 13 designed by the design method of the third embodiment.

  As shown in FIGS. 9 and 10, a D flip-flop 3 that is a sequential circuit and a plurality of cells (NAND gate G2, inverter G14, NAND gate G15, inverter G16, NAND gate G24) provided in the preceding stage of the D flip-flop 3 are used. The inverters G25 and G26), the combinational circuit group 15 and the input unit 10 become the power cutoff target unit 13.

  The output of the NAND gate G2 is connected to the D input of the D flip-flop 3. The D flip-flop 3 has a Q output and a clock input clk. Further, since the other configuration is the same as that of the power shutoff target unit 12 shown in FIG. 7, the same reference numerals are given and description thereof is omitted.

  Hereinafter, the design method of the third embodiment for the power shutoff target unit 13 shown in FIGS. 9 and 10 will be described with reference to FIG.

  First, in step S21, all the cells in the power cutoff target unit 13 are temporarily set as temporary power cutoff cells that require power cutoff. In the circuit example shown in FIG. 9, the NAND gates G2, G15, G24, the inverters G14, G16, G25, G26 and all the cells (not shown) in the combinational circuit group 15 are temporary power cutoff cells (sandy hatching). Temporarily set. As a temporary power cut-off cell, a cell having a relatively small leakage current during standby when power is not cut off at a relatively high speed is applicable.

  Next, in step S22, a signal path that needs to be speeded up is recognized as a required power cut-off signal path among signal paths from the D flip-flop 3 that is a sequential circuit back to the input unit 10 in the input direction. That is, when all the temporary power-off cells on the signal path are replaced with lower-speed power-off cells, the timing critical path is recognized by the timing verification, and it is necessary to use the temporary power-off cells. The signal path is recognized as a power cutoff signal path. Conversely, a signal path that has a margin in timing and is assumed not to be a timing critical path even if all temporary power-off cells are replaced with power-off cells is recognized as a power-off signal path. Absent.

  In the circuit example shown in FIG. 9, the signal path R5 from the input unit 10 to the D input of the D flip-flop 3 through the combinational circuit group 15, the inverter G25, the inverter G15, and the NAND gate G2, and the combinational circuit group from the input unit 10 15, a signal path R6 that reaches the D input of the D flip-flop 3 through the inverter G26, the inverter G16, and the NAND gate G2 is a power-off signal path.

  Thereafter, in step S23, the power-off signal path is traced back from the D flip-flop 3 which is a sequential circuit, and the cells on the power-off signal path are sequentially arranged until the power-off signal path satisfies a predetermined speed-up requirement. The final setting is made as a power-off cell requiring determination. Then, when the predetermined speed-up requirement is satisfied, the sequential setting of the determination-necessary power-off cells is finished. The predetermined speed-up requirement in the third embodiment corresponds to a timing critical path even if all temporary power-off cells other than the determined power-off cell set on the power-off signal path are replaced with power-off cells There may be a condition such that the signal propagation time of the required power cut-off signal path can be increased to a level determined to not.

  In the circuit example shown in FIG. 9, the NAND gate G2, the NAND gate G15, and the inverter G25 on the signal path R5 are sequentially set as the determined power cutoff cells, and the final setting process of the power cutoff cells in the combinational circuit group 15 is performed. Assume that it has finished.

  On the other hand, it is assumed that the NAND gate G2 and the inverter G16 on the signal path R6 are set as the power-off cells, and that the sequential setting process of the power-off cells is completed at the stage of the inverter G26.

  In step S24, all the cells (temporary power cutoff cells) other than the determined power cutoff cell finally set in step S23 are replaced with determined power cutoff unnecessary cells and finally set. That is, all the cells on the signal path other than the power-off signal path and all cells on the power-off signal path that have not been finally set as the determined power-off cell are from the temporary power-off cell. It is replaced with a cell that does not need to be turned off. Note that the determined power cutoff unnecessary cell corresponds to a cell that operates at a lower speed than the temporary power cutoff cell but has a smaller leakage current during standby when the power cutoff is not performed than the temporary power unnecessary cutoff cell.

  In the circuit example shown in FIG. 10, all of the signals except the NAND gate G2, NAND gate G15 and NAND gate G15 on the signal path R5, and NAND gate G2 and the inverter G16 on the signal path R6, which are finally set as the power cutoff cells to be determined. The cell is finally set as the determined power cutoff unnecessary cell (white cell).

  Therefore, the power cutoff function is not set to the cells in the inverter circuit G26 and the combinational circuit group 15 on the signal path R6 arranged in front of the inverter G26 on the signal path R6.

  Finally, in step S25, a cutoff control circuit for the power cutoff cell is generated. The interruption control circuit generation process is performed in the same manner as the process in step S4 of the first embodiment.

  As described above, the semiconductor integrated circuit design method according to the third embodiment uses a timing critical path that needs to be speeded up among signal paths that end in a sequential circuit that does not require measures against through current. The cells that are selected as the cut-off signal path and exist on the power-supply cut-off signal path are finally set as determined power cut-off cells until a predetermined speed-up requirement is satisfied.

  As a result, according to the semiconductor integrated circuit design method of the third embodiment, as in the first and second embodiments, the first-type cell and the power shut-off function having no power source cut-off function are eliminated. Thus, it is possible to obtain a semiconductor integrated circuit in which the second type cell not having the signal is mixed in the power cutoff target unit 13.

  As described above, according to the semiconductor integrated circuit design method of the second embodiment, among the plurality of cells in the power shutoff target unit 13, the cells that are present on the power shutoff signal path that is highly necessary to shut off the power are selected. By selectively setting the power supply to be cut off, there is an effect that it is possible to obtain a semiconductor integrated circuit in which the effort for countermeasures for through current is minimized and power consumption is reduced.

<Embodiment 4>
A method for designing a semiconductor integrated circuit according to a fourth embodiment is a method for designing a semiconductor integrated circuit including a target cell that is a combinational circuit such as a logic gate and a power shut-off target unit having a plurality of cells. It is assumed that it exists in the latter stage of the cell.

  FIG. 11 is a flowchart showing a method for designing a semiconductor integrated circuit according to the fourth embodiment of the present invention. FIG. 12 is a circuit diagram showing a circuit example including the power shutoff target unit 14 designed by the design method of the fourth embodiment.

  As shown in FIG. 12, the output of the inverter G6 is connected to the D input of the D flip-flop 4 which is a sequential circuit. The input of the inverter G6 is connected to the combinational circuit group 16, and the output part of the NAND gate G5 is connected to one input part of the combinational circuit group 16. The D flip-flop 4 has a Q output and a clock input clk.

  The NAND gate G5, which is the target cell, receives the external control signal ctrl as one input and receives the output of the NAND gate G1 at the other input RY. The NAND gate G5 and a plurality of cells (NAND gate G1, inverter G11, NAND gate G12, inverter G13, NAND gate G21, inverters G22 and G23) provided in the preceding stage serve as the power cutoff target unit 14.

  The output of the inverter G11 is connected to the first input of the NAND gate G1, the output of the NAND gate G12 is connected to the second input, and the inverter G13 is connected to the third input. The output of the NAND gate G21 is connected to one input of the NAND gate G12, and the output of the inverter G22 is connected to the other input. The output of the inverter G23 is connected to the input of the inverter G13.

  Hereinafter, the design method of the fourth embodiment for the power shutoff target unit 14 shown in FIG. 12 will be described with reference to FIG.

  First, in step S31, a combinational circuit that can originally take measures against through current in a semiconductor integrated circuit to be designed is recognized as a target cell.

  In the circuit example shown in FIG. 12, the NAND gate G5, which is one of the combinational circuits, inputs the external control signal ctrl. Therefore, even if the preceding-stage NAND gate G1 has a power cutoff function, the power supply of the NAND gate G1 By inputting the “L” external control signal ctrl at the time of shut-off, the output of the NAND gate G5 can be fixed to “H”, and generation of a through current in the NAND gate G5 can be surely avoided.

  That is, since the NAND gate G5 can originally take measures against through current, it is not necessary to provide a special power-off function like the sequential circuit. Therefore, the NAND gate G5 is similar to the sequential circuit such as the D flip-flop. Recognize as an attention cell. As a result, the target cell and a plurality of cells (G1, G11 to G13, G21 to G23) positioned in the preceding stage of the target cell are the power shutoff target unit 14.

  Next, in step S <b> 32, the power cutoff cell in the power cutoff target unit 14 is recognized. In the circuit example shown in FIG. 12, the inverter G13 and the inverter G22 are recognized as the first power-required cutoff cell (hatched hatching) in the power cutoff target unit 14 shown in FIG. For example, a high-speed operation cell with a large leakage current is selected as the first power-supply cutoff cell.

  Next, in step S23, a power-required power cut-off signal path is searched from the NAND gate G5, which is the cell of interest, back to the input power cut-off cell. In the circuit example shown in FIG. 12, the signal path R7 from the inverter G22 through the NAND gate G12 and the NAND gate G1 to the input of the NAND gate G5, and the inverter G23 through the inverter G13 and the NAND gate G1, the NAND gate G5 The signal path R8 leading to the input is a power cutoff signal path.

  After that, in step S24, cells other than the first power-required cell recognized in step S22 among the cells on the power-required power-off signal path are set as second power-required cells. In the circuit example shown in FIG. 12, the NAND gate G12 and the NAND gate G1 on the signal path R7 are set as the second power source cutoff cell, and the NAND gate G1 on the signal path R8 is the second power source cutoff cell. Set as (sandy hatching). The NAND gate G1 is redundantly set as a second power-off cell.

  Finally, in step S25, a cutoff control circuit is generated for the first and second power source cutoff cells. The process for generating the control circuit for interruption is performed in the same manner as the process in step S4 of the first embodiment.

  As described above, in the semiconductor integrated circuit design method of the fourth embodiment, the signal path that requires the first power source cutoff cell as the starting point and the target cell that does not require through current countermeasures as the end point is the power source cutoff signal path. And all of the cells other than the first required cell that are present on the required power cutoff signal path are set as second required power cutoff cells.

  As a result, according to the semiconductor integrated circuit design method of the fourth embodiment, as in the first to third embodiments, the first-type cell and the power shut-off function having no power source cut-off function are eliminated. Thus, it is possible to obtain a semiconductor integrated circuit in which the second type cell not having the signal is mixed in the power cutoff target unit 14.

  As described above, according to the design method of the semiconductor integrated circuit of the second embodiment, the first and second elements that are highly required to shut off the power in the target cell and the power cutoff target portion including the plurality of cells preceding the target cell. By setting only the power shut-off cells so that the power can be shut off selectively, it is possible to obtain a semiconductor integrated circuit that minimizes the effort for measures against through current and reduces power consumption.

  The design method of the fourth embodiment is the same design method as that of the first embodiment except that the sequential circuit is mainly replaced with the target cell. It is also conceivable to adopt a design method similar to the design method 3.

  That is, as an improvement of the design method of the fourth embodiment, a design method similar to the design method of the second embodiment may be used except that the sequential circuit is mainly replaced with the target cell. A design method similar to the design method of Embodiment 3 may be used except for the point replaced with.

  The present invention is applicable to all products (semiconductor integrated circuits) that require reduction of leakage power, such as mobile phones.

3 is a flowchart showing a method for designing a semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 3 is a circuit diagram showing a circuit example of a power shutoff target unit designed by the design method of the first embodiment. FIG. 3 is a circuit diagram illustrating a first configuration example of a cutoff control circuit designed by the design method according to the first embodiment. FIG. 6 is a circuit diagram showing a second configuration example of the cutoff control circuit designed by the design method of the first embodiment. It is an explanatory circuit diagram showing that there is no need to provide a power shutoff function in the sequential circuit itself. It is a flowchart which shows the design method of the semiconductor integrated circuit which is Embodiment 2 of this invention. FIG. 10 is a circuit diagram illustrating a circuit example of a power shut-off target unit designed by the design method of the second embodiment. It is a flowchart which shows the design method of the semiconductor integrated circuit which is Embodiment 3 of this invention. FIG. 10 is a circuit diagram showing a circuit example of a power shut-off target unit designed by the design method of the third embodiment. FIG. 10 is a circuit diagram showing a circuit example of a power shut-off target unit designed by the design method of the third embodiment. It is a flowchart which shows the design method of the semiconductor integrated circuit which is Embodiment 4 of this invention. FIG. 10 is a circuit diagram illustrating a circuit example including a power shut-off target unit designed by the design method of the fourth embodiment. It is a circuit diagram which shows one circuit structure which requires a through-current countermeasure.

Explanation of symbols

  1-4 D flip-flop, 11-14 power-off target part, G5 NAND gate (target cell).

Claims (9)

A method for designing a semiconductor integrated circuit including a predetermined cell and a power shut-off target unit having a plurality of cells arranged in a preceding stage of the predetermined cell,
(a) selecting a required power cut-off signal path from at least one signal path having the predetermined cell as an end point in the power cut target unit, and among the cells existing on the power required cut-off signal path in the plurality of cells A step of setting a predetermined number of cells arranged continuously from the predetermined cells as power-off cells that require power-off,
(b) setting a shut-off control circuit that allows the power shut-off cell to be forcibly shut off by an external signal;
A method for designing a semiconductor integrated circuit comprising: A method for designing a semiconductor integrated circuit according to claim 1, comprising:
The power source cutoff cell includes first and second power source cutoff cells,
Step (a) includes
(a-1) recognizing a cell that needs to be turned off among the plurality of cells as the first power-off cell;
(a-2) selecting a signal path starting from the first required power cutoff cell and ending at the predetermined cell as the required power cutoff signal path in the power cutoff target unit;
(a-3) setting all the cells other than the first required cell that are present on the required power cutoff signal path among the plurality of cells as the second required power cutoff cell; Including,
A method for designing a semiconductor integrated circuit. A method for designing a semiconductor integrated circuit according to claim 1, comprising:
Step (a) includes
(a-1) selecting a signal path that needs to be speeded up as the power cutoff signal path among the at least one signal path having the predetermined cell as an end point in the power cutoff target unit;
(a-2) In the required power cut-off signal path, the cells existing on the required power cut-off signal path from the plurality of cells in the input direction satisfy the predetermined speed-up requirement. Including sequentially setting as the power-off cell,
A method for designing a semiconductor integrated circuit. A method of designing a semiconductor integrated circuit according to claim 3,
(c) further comprising the step of performing temporary setting as a temporary power-off unnecessary cell that is executed prior to the step (a) and that does not require power-off.
The step (a-2) includes a process of replacing the temporary power cutoff cell with the temporary power cutoff unnecessary cell and setting it,
A method for designing a semiconductor integrated circuit. A method of designing a semiconductor integrated circuit according to claim 3,
(c) a step that is executed prior to the step (a) and temporarily sets the plurality of cells as temporary power-off cells that require power-off;
(d) After the step (a), and before the step (b), the cells other than the power-required power-off cells are replaced from the temporary power-off cells with the power-off unnecessary cells. And further comprising a step,
A method for designing a semiconductor integrated circuit. A method for designing a semiconductor integrated circuit according to any one of claims 1 to 5, comprising:
The predetermined cell includes a sequential circuit;
A method for designing a semiconductor integrated circuit. A method for designing a semiconductor integrated circuit according to any one of claims 1 to 5, comprising:
The predetermined cell includes a combinational circuit;
A method for designing a semiconductor integrated circuit.   A semiconductor integrated circuit designed by the method for designing a semiconductor integrated circuit according to claim 1. A semiconductor integrated circuit including a predetermined sequential circuit and a power shut-off target unit having a plurality of cells arranged in a preceding stage of the predetermined sequential circuit,
The plurality of cells include a first type cell having a power cutoff function and a second type cell not having a power cutoff function,
Between the plurality of cells, there is no combination of the first type cell and the second type cell receiving the output of the first type cell as an input,
Semiconductor integrated circuit.

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