JP2009296311A - Semiconductor device and solid-state imaging apparatus - Google Patents

Abstract

In a CMOS sensor using a column ADC system, the problem of parasitic capacitance of a horizontal signal line is improved and high-speed data transfer can be performed more reliably.
A six-input sub-selector 302A that handles six latches 257 is provided between a data storage unit 256 and a horizontal transfer driver 308. Six latches 257 are connected to one 6-input sub-selector 302A, one 6-input sub-selector 302A is connected to one horizontal transfer driver 308, and one horizontal transfer driver 308 is connected to the horizontal signal line 18. . The horizontal transfer driver 308 connected to the horizontal signal line 18 is reduced to 1/6, and the parasitic capacitance of the horizontal signal line 18 due to the horizontal transfer driver 308 is reduced. Regardless of the configuration of the 6-input sub-selector 302A, the horizontal transfer driver 308 may be a single stage, and the series resistance when driving the horizontal signal line 18 does not increase, and high-speed data transfer can be performed reliably and faster than before. Become.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device and a solid-state imaging device. More specifically, the present invention relates to a semiconductor device having a signal selection function for selecting and outputting any one of a plurality of signals and a solid-state imaging device using the signal selection function.

  In various electronic devices and semiconductor devices such as an image processing device, an imaging device, and a solid-state imaging device, a signal selection circuit that selects one of a plurality of signals and outputs one signal may be used.

  For example, a physical quantity distribution detecting semiconductor device in which a plurality of unit components (for example, pixels) that are sensitive to electromagnetic waves input from outside such as light and radiation are arranged in a line or matrix form in various fields. It is used. For example, in the field of video equipment, a complementary metal-oxide semiconductor (CMOS) type solid-state imaging device may be used. In a CMOS type solid-state imaging device, for example, a plurality of pixel transistors are arranged in a two-dimensional matrix to form a pixel unit, and accumulation of signal charges corresponding to incident light is started for each line (row) or for each pixel, A current or voltage signal based on the accumulated signal charge is sequentially read from each pixel by addressing.

  In this case, as an example of address control, a column readout method (column parallel output method) in which one row is accessed simultaneously and a pixel signal is read from the pixel unit in units of rows is often used (for example, Patent Document 1, Patent Document 1). 2).

JP 2006-148509 A JP 2006-074436 A

  The pixel signal read from the pixel unit is subjected to signal processing such as CDS (Correlated Double Sampling) and is sequentially output to the outside using a horizontal transfer system. Generally, the signal processing circuit of each column is connected to a signal line of a horizontal transfer system via a horizontal readout switch (horizontal selection switch).

  The analog pixel signal read from the pixel unit is converted into digital data simultaneously for all the columns for one row by an analog-digital converter (AD converter / ADC: Analog Digital Converter) as necessary. The digital data of each column is once held in a data holding circuit (latch), and the digital data is sequentially output to the outside using a horizontal transfer system. This is referred to as a column ADC system. In this case, horizontal transfer drivers for all columns that output data of each column are connected to the horizontal transfer system signal lines. For horizontal transfer, transfer using a current signal (current transfer) may be employed instead of transfer using a voltage signal (voltage transfer).

  However, in such a system, the number of switches and horizontal transfer drivers connected to the signal line of the horizontal transfer system becomes enormous, the parasitic capacitance of the horizontal transfer line becomes large, and the transfer takes time. is there.

  As a technique for solving this problem, a mechanism for dividing the horizontal transfer system into a plurality of channels is conceivable. However, when performing the thinning mode in which data transfer is performed by thinning out columns as described in Patent Document 2, all horizontal transfers are performed. The channel cannot be used effectively, and the efficiency at the time of thinning is deteriorated.

  On the other hand, the mechanism described in Patent Document 1 attempts to solve the problem of parasitic capacitance of the horizontal transfer line by hierarchizing the horizontal transfer system. In the mechanism of Patent Document 1, the number of switches connected to the horizontal signal lines is reduced by interposing a horizontal switch circuit having a plurality of stages between the signal processing circuits of each column and the horizontal signal lines, thereby increasing the speed. The signal charge can be read out.

  By the way, the mechanism described in Patent Documents 1 and 2 is an application example in an analog column reading system instead of a column ADC system, and AD conversion is performed after horizontal transfer. Although it is conceivable to apply the mechanisms described in Patent Documents 1 and 2 to the column ADC system, there are the following problems.

  For example, when the mechanism of Patent Document 1 is applied to the column ADC system, it is considered that a plurality of (several) latches and a horizontal transfer driver are connected to the horizontal transfer channel via one latch group selection circuit. . This reduces the parasitic capacitance of the horizontal transfer channel that the horizontal transfer driver must drive.

  However, in this method, when driving the signal line, the series resistance during driving increases because the latch group selection circuit enters the drive current path. Therefore, while the parasitic capacitance is reduced, the series resistance with the signal line is increased during current transfer, and the speed-up effect is limited.

  When the mechanism of Patent Document 2 is applied to the column ADC system, it is conceivable that the horizontal transfer system is hierarchized and a function of skipping latches at the time of thinning is incorporated in the child hierarchy. Effective use of all horizontal transfer channels at the time of decimation to improve efficiency at the time of decimation. However, there is no description about the circuit, and it is considered that the same circuit system as in Patent Document 1 is used. Therefore, the effect of speeding up is limited.

  The present invention has been made in view of the above circumstances, and provides a mechanism that improves the problem of parasitic capacitance of the horizontal signal line and enables more reliable high-speed data transfer when the column ADC system is adopted. The purpose is to do. Preferably, an object is to provide a mechanism for performing high-speed data transfer even when thinning is not performed, and effectively using all horizontal transfer channels during thinning and improving efficiency during thinning.

  In one embodiment of the present invention, a selection unit including a plurality of signal selection units for selecting any of data in a plurality of data holding circuits (latches), and data transfer based on the data selected by the signal selection unit It is assumed that there is provided a drive unit provided with a transfer drive unit (horizontal transfer driver) for driving a signal line for each of the plurality of signal selection units. Data selection in each signal selection unit of the selection unit is controlled by the selection control unit, and data transfer by each transfer drive unit of the drive unit is controlled by the scanning unit.

  In such a mechanism, a plurality (k pieces) of data holding circuits (referred to as latch groups) are connected to one signal selection unit, and one signal selection unit is connected to one transfer driving unit. One transfer driver is connected to the signal line. Such a relationship is repeated for the same number of signal selectors and transfer drivers. Each latch group has one signal selection unit and one transfer driving unit including a transfer transistor and a selection transistor. As a result, the transfer driver connected to the signal line is reduced to 1 / k compared to the case where the present invention is not applied.

  Further, preferably, the transfer driving unit selects one of a plurality of signal selection units based on an instruction from a transfer transistor that drives a signal line based on data selected by the signal selection unit and a scanning unit. The selection transistor is provided. The transfer transistor performs horizontal transfer by current transfer. In order to increase the speed, an inverter that logically inverts the data selected by the signal selection unit (non-inverted data) is further provided, and a transfer transistor and a selection transistor are provided for each of the non-inverted data and the inverted data that is logically inverted by the inverter. Alternatively, current transfer by a complementary (differential) signal line pair may be performed.

  When both the transfer transistor and the selection transistor are turned on, the data selected by the signal selection unit is transferred to the subsequent circuit through the signal line. As an example, it is a simple configuration that a transfer transistor and a selection transistor are connected in series.

  Since the transfer driver operates according to data from the signal selection unit, the signal selection unit does not intervene in the drive current path when driving the signal line. Only the transistors constituting the transfer driver are present in the drive current path. Regardless of the configuration of the signal selection unit, the transfer driving unit may be one stage.

  In the solid-state imaging device, when the selection control unit and the horizontal scanning unit can select a mode in which data transfer is performed by thinning out columns, the reciprocal number corresponding to the thinning rate is input to each of the plurality of signal selection units. Try to use a number. For example, when it is possible to select a thinning operation mode in which data transfer is performed by thinning a column to 1 / K, a K input-1 output type is used for each of a plurality of signal selection units. . By aligning the number of inputs handled by one signal selection unit to the reciprocal (K) of 1 / K, which is the rate of decimation, the number of uses of each transfer drive unit is equalized even during the decimation operation. As a result, the usage state of the signal lines connected to the transfer driver is balanced even during the thinning operation. Even when a plurality of signal lines are used, the degree of use of each signal line is balanced.

  This is the same in the case of dealing with a plurality of thinning modes having different thinning levels. In this case, if the number of inputs handled by one signal selection unit is aligned with the least common multiple of the reciprocal of the proportion of each thinning. Good. For example, when a mode in which data is transferred by thinning a column to 1 / K1 and a mode in which data transfer is performed by thinning to 1 / K2 can be selected, the least common multiple of K1 and K2 is set in each of the plurality of signal selection units. A K_1,2 input-1 output type having the number of inputs (denoted as K_1,2) may be used.

  According to one aspect of the present invention, the number of transfer driving units connected to a signal line is reduced to one-tenth of the number of inputs handled by one signal selection unit, compared with the case where the present invention is not applied. The parasitic capacitance of the signal line due to the drive unit is reduced. Regardless of the configuration of the signal selection unit, the transfer driving unit may be one stage, and the series resistance when driving the signal line does not increase. As a result, it is possible to reliably transfer data at a higher speed than before.

  If each of the plurality of signal selection units has a reciprocal number of inputs corresponding to the thinning rate in the solid-state imaging device, it is possible to balance the usage of each transfer drive unit and signal line. Each channel can be effectively used even when thinning a signal line into a plurality of channels, and the transfer efficiency during thinning can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. When distinguishing each functional element according to the embodiment, an uppercase English reference such as A, B, C,... Is added and described. Omitted and listed. The same applies to the drawings.

  In the following, a case where a CMOS type solid-state imaging device, which is an example of an XY address type solid-state imaging device, is used as a device will be described as an example. Unless otherwise specified, the CMOS type solid-state imaging device will be described on the assumption that all unit pixels are composed of nMOSs (n-channel type MOS transistors) and the signal charges are negative charges (electrons). However, this is merely an example, and the target device is not limited to a MOS type solid-state imaging device. The unit pixel may be composed of a pMOS (p-channel type MOS transistor), and the signal charge is a positive charge ( Hole).

  For all semiconductor devices for physical quantity distribution detection that read out signals by address control by arranging a plurality of unit pixels that are sensitive to electromagnetic waves input from outside such as light and radiation in a line or matrix form All embodiments to be described later can be similarly applied.

<Solid-state imaging device: basic configuration>
FIG. 1 is a basic configuration diagram of a CMOS type solid-state imaging device (CMOS image sensor) which is an embodiment of a solid-state imaging device according to the present invention. A solid-state imaging device is also an example of a semiconductor device.

  The solid-state imaging device 1 includes a pixel array unit 10 in which a plurality of unit pixels 3 are arranged in a two-dimensional matrix. The solid-state imaging device 1 can make the pixel array unit 10 compatible with color imaging by using a color separation (color separation) filter in which, for example, R, G, and B color filters are arranged in a Bayer array.

  In FIG. 1, some of the rows and columns are omitted for the sake of simplicity, but in reality, tens to thousands of unit pixels 3 are arranged in each row and each column. As will be described later, the unit pixel 3 includes, for example, three or four transistors for charge transfer, reset, and amplification in addition to a photodiode as a light receiving element (charge generation unit) which is an example of a detection unit. It has an in-pixel amplifier. A pixel signal voltage Vx is output from the unit pixel 3 via the vertical signal line 19 for each column. The pixel signal voltage Vx includes a reset level Srst (P phase component) and a signal level Ssig (D phase component).

  The solid-state imaging device 1 further includes a column AD conversion unit 26 in which an AD conversion unit 250 having a CDS (Correlated Double Sampling) processing function and a digital conversion function is provided in parallel. “Column parallel” means that a plurality of CDS processing function units and digital conversion units (AD conversion units) are provided substantially in parallel with vertical signal lines 19 (an example of column signal lines) in a vertical column. Means that. Such a reading method is called a column reading method.

  The solid-state imaging device 1 further includes a drive control unit 7, a read current source unit 24 that supplies an operation current (read current) for reading pixel signals to the unit pixel 3, and a reference signal SLP_ADC for AD conversion to the column AD conversion unit 26. Is provided with a reference signal generation unit 27, an output unit 28, and a data selector unit 300.

  The drive control unit 7 includes a horizontal scanning unit 12 (column scanning circuit), a vertical scanning unit 14 (row scanning circuit), and a communication / timing control unit for realizing a control circuit function for sequentially reading signals from the pixel array unit 10. 20 is provided. The horizontal scanning unit 12 instructs the column position of data to be read out during the data transfer operation in the data selector unit 300.

  The horizontal scanning unit 12 includes a horizontal address setting unit 12a and a horizontal driving unit 12b that control column addresses and column scanning. The vertical scanning unit 14 includes a vertical address setting unit 14a and a vertical driving unit 14b that control row addresses and row scanning. The horizontal scanning unit 12 and the vertical scanning unit 14 start the row / column selection operation (scanning) in response to the control signals CN1 and CN2 given from the communication / timing control unit 20.

  The data selector unit 300 selects the horizontal position (column position) of the column AD conversion unit 26 based on the control signal CN9 from the communication / timing control unit 20 and the instruction from the horizontal scanning unit 12, and the selected column position Is transferred to the output unit 28 side. Although details will be described later, the data selector unit 300 is responsible for the latches 257 for two or more columns and selects one of the data of each latch 257, and a horizontal signal based on the data selected by the subselector 302 There are a plurality of pairs of horizontal transfer drivers 308 that drive the lines 18. The sub-selector 302 performs a data selection operation based on a selection control signal from the communication / timing control unit 20, and the horizontal transfer driver 308 performs a transfer operation based on a selection control signal from the horizontal scanning unit 12.

  The communication / timing control unit 20 is a timing generator (reading address control) that supplies a clock synchronized with the master clock CLK0 input via the terminal 5a to each unit (scanning units 12, 14 and column AD conversion unit 26) in the device. A functional block of an example of the apparatus. Further, the master clock CLK0 supplied from the external main control unit is received via the terminal 5a, and the data for instructing the operation mode supplied from the external main control unit is received via the terminal 5b. A function block of a communication interface that outputs data including information of the device 1 to an external main control unit is provided.

  For example, the communication / timing control unit 20 includes a clock conversion unit 20a having a function of a clock conversion unit that generates an internal clock, and a system control unit 20b having a communication function and a function of controlling each unit. The clock conversion unit 20a has a built-in multiplier circuit that generates a pulse having a higher frequency than the master clock CLK0 based on the master clock CLK0 input via the terminal 5a. The clock conversion unit 20a includes an internal count clock CKcnt1 and count clock CKdac1. Generate a clock.

  The output unit 28 includes a sense amplifier 28a (S · A) that detects a signal (digital data but small amplitude) on the horizontal signal line 18 that is a signal line (transfer wiring) for data transfer, and the solid-state imaging device 1. And an interface unit 28b (IF unit) that functions as an interface with the outside. The output of the interface unit 28b is connected to the output terminal 5c, and the video data is output to the subsequent circuit. The output unit 28 may also be provided with a digital arithmetic unit that performs various digital arithmetic processes between the sense amplifier 28a and the interface unit 28b.

  The unit pixel 3 includes a vertical scanning unit 14 via a row control line 15 for row selection, and an AD conversion unit 250 provided for each vertical column of the column AD conversion unit 26 via a vertical signal line 19. , Each connected. Here, the row control line 15 indicates the entire wiring that enters the pixel from the vertical scanning unit 14.

  The vertical scanning unit 14 selects a row of the pixel array unit 10 and supplies a necessary pulse to the row. The vertical address setting unit 14a selects not only a row from which a signal is read (reading row: also referred to as a selected row or a signal output row) but also a row for an electronic shutter.

  Various methods are considered as an AD conversion method in the AD conversion unit 250 from the viewpoint of circuit scale, processing speed (high speed), resolution, and the like. As an example, a reference signal comparison type, a slope integration type, or a ramp An AD conversion method called a signal comparison type is adopted. In the reference signal comparison type AD conversion, the count operation valid period is determined based on the time from the conversion start (comparison process start) to the conversion end (comparison process end), and the count enable signal EN indicating the period is used. Based on this, the analog processing target signal is converted into digital data.

  For this reason, the reference signal generation unit 27 includes a DA conversion unit 270 (DAC; Digital Analog Converter), and synchronizes with the count clock CKdac1 from the initial value indicated by the control data CN4 from the communication / timing control unit 20, A reference signal SLP_ADC having a slope (change rate) indicated by the control data CN4 is generated. The count clock CKdac1 may be the same as the count clock CKcnt1 for the counter unit 254.

  The AD conversion unit 250 includes a comparison unit 252 (COMP) and a counter unit 254 that can switch between an up-count mode and a down-count mode. In this example, a data storage unit 256 incorporating a horizontal transfer latch 257 (memory) is further provided downstream of the counter unit 254. The comparison unit 252 generates the reference signal SLP_ADC generated by the reference signal generation unit 27 and the analog pixel signal voltage Vx obtained from the unit pixel 3 in the selected row via the vertical signal lines 19 (H1, H2,..., Hh). Compare The counter unit 254 counts the active period of the count enable signal EN having a fixed relationship with the comparison output Co of the comparison unit 252 using the count clock CKcnt1, and holds the count result.

  From the communication / timing control unit 20 to the counter unit 254 of each AD conversion unit 250, whether the counter unit 254 operates in the down-count mode or the up-count mode for the P-phase / D-phase counting process, A control signal CN5 for instructing other control information such as setting of the initial value Dini and reset processing in the counting process is input.

  One input terminal (+) of the comparison unit 252 receives the reference signal SLP_ADC generated by the reference signal generation unit 27 in common with the input terminal (+) of the other comparison unit 252 and the other input terminal (− ) Are connected to the vertical signal lines 19 in the corresponding vertical columns, and the pixel signal voltages Vx from the pixel array unit 10 are individually input thereto.

  The count clock CKcnt1 from the communication / timing control unit 20 is input to the clock terminal CK of the counter unit 254 in common with the clock terminals CK of the other counter units 254. When the data storage unit 256 is not provided, a control pulse is input to the counter unit 254 from the horizontal scanning unit 12 via the control line 12c. The counter unit 254 has a latch function for holding the count result, and holds the counter output value until an instruction by a control pulse through the control line 12c is given.

  In this embodiment, the ADS 250 completes the CDS process. However, the P-phase data at the reset level Srst and the D-phase data at the signal level Ssig are individually transferred to the output unit 28, and the AD converter 250. The CDS process may be performed by a subsequent digital calculation unit. The present applicant has proposed various reference signal comparison type AD conversion methods in which the AD conversion unit 250 performs AD conversion and CDS processing, and these can basically be adopted in each embodiment.

  The elements of the drive control unit 7 such as the horizontal scanning unit 12 and the vertical scanning unit 14 are formed integrally with the pixel array unit 10 in a semiconductor region such as single crystal silicon using a technique similar to the semiconductor integrated circuit manufacturing technique. The solid-state imaging device 1 of the present embodiment is configured as a so-called one-chip product (provided on the same semiconductor substrate).

  As described above, the solid-state imaging device 1 may be formed as a single chip in which each unit is integrally formed in the semiconductor region. Although not illustrated, the pixel array unit 10, the drive control unit 7, In addition to various signal processing units such as the column AD conversion unit 26, an imaging function in which these are collectively packaged in a state including an optical system such as a photographing lens, an optical low-pass filter, or an infrared light cut filter It is good also as the modular form which has.

  For example, the output side of each AD conversion unit 250 can connect the output of the counter unit 254 to the horizontal signal line 18 via the data selector unit 300. Alternatively, as shown in the figure, it is possible to adopt a configuration in which a data storage unit 256 as a memory device including a latch that holds the count result held by the counter unit 254 is provided at the subsequent stage of the counter unit 254. In the present embodiment, a data selector unit 300 is further provided after the data storage unit 256, and the data storage unit 256 and the data selector unit 300 constitute a horizontal transfer system Htrans. The data storage unit 256 holds and stores the count data output from the counter unit 254 at a predetermined timing.

  The horizontal scanning unit 12 reads the count value held by each data storage unit 256 in parallel with each comparison unit 252 and counter unit 254 of the column AD conversion unit 26 performing the processing that they are responsible for. It has the function of a readout scanning unit. The output of the data storage unit 256 is connected to the horizontal signal line 18 via the data selector unit 300. The horizontal signal line 18 has a signal line corresponding to the bit width of the AD conversion unit 250 or a double width thereof (for example, complementary output), and an output unit 28 having a sense amplifier 28a corresponding to each output line. Connected to. The number of horizontal transfer channels of the horizontal signal line 18 is not limited to one, and data transfer may be performed by grouping a plurality of channels into a plurality of columns. Note that each of the counter unit 254, the data storage unit 256, the data selector unit 300, and the horizontal signal line 18 has a configuration corresponding to n bits.

<Problems of horizontal data transfer>
Here, when the data held in the latches 257 of each column is sequentially transferred to the output unit 28 side via the horizontal signal line 18 which is a bus line, the parasitic capacitance is added to the horizontal signal line 18 connected to the output unit 28. Because of the presence of parasitic capacitance, there are various factors due to the presence of parasitic capacitance, such as transfer speed degradation and the increase in chip size that requires increasing the wiring width (Metal width) used for the horizontal signal line 18 in order to suppress parasitic capacitance. Problems arise.

For example, the value of parasitic capacitance is
(1) Capacity due to the horizontal signal line 18,
(2) Capacity due to the input stage of the output unit 28,
(3) Capacitance due to output stage of latch 257 × total number of latches 257,
(4) capacitance of wiring connecting the horizontal signal line 18 and the output stage of one latch 257 × total number of latches 257,
It is the total value.

  Accordingly, when the data held in the latches 257 in each column is sequentially selected and read out to the horizontal signal line 18 by the latches 257, data transfer is hindered due to the parasitic capacitance of the horizontal signal line 18. In particular, if the capacitance value of the parasitic capacitance is increased, it causes signal delay and hinders speeding up of data transfer.

  For example, when high-speed operation is performed for reasons such as increasing the frame rate, operations such as row scanning, AD conversion, and horizontal data transfer must be performed at high speed. Of these, when it is desired to speed up the horizontal data transfer, the horizontal signal line 18 is driven based on the output data of the latch 257 selected by the horizontal scanning unit 12 and the time until the signal reaches the output unit 28 is reached. Become dominant.

  In the case of the pixel array section 10 having the horizontal pixels, for example, 2000 columns of unit pixels 3, 2000 latches 257 are connected to the horizontal signal line 18, and the parasitic capacitance of each output stage of the latch 257 Are combined, and the selected latch 257 is driven with its large capacity as a load. In recent years, since there is a demand for increasing the number of pixels, the number of latches 257 connected to the horizontal signal line 18 tends to increase, and in recent years, there is a restriction on high speed operation that is particularly required.

  Even when horizontal transfer is performed by complementary (differential) signal line pairs for speeding up, if the number of horizontal transfer drivers 308 connected to the horizontal signal line 18 increases, the parasitic capacitance of the horizontal signal line 18 increases and the current flows. Even if the transfer is performed, the transfer takes time.

  As a method for solving such a problem, a method of widening the wiring width used for the horizontal signal line 18 in order to suppress the parasitic capacitance is conceivable, but bit-specific data is transferred by the horizontal signal line 18 as a bus line. In some cases, the chip size becomes large.

  As another method for solving such a problem, a method of processing in parallel for each number of columns as in JP-A-2000-32344 can be considered. However, the mechanism is an application example in the case where analog information is output to the outside of the solid-state imaging device 1, and the mechanism is particularly applied to a mechanism for digitally converting a pixel signal and outputting the digital signal to the outside of the solid-state imaging device 1. If it is attempted to be applied, the number of output terminals increases, and there is a problem that multiplexing processing of the output part is necessary.

  Therefore, in the present embodiment, in the mechanism in which the pixel signal is digitally converted and output to the outside of the solid-state imaging device 1, the column processing unit 26 and the horizontal scanning unit 12 are caused to have a problem caused by the parasitic capacitance of the horizontal signal line 18. Make it a mechanism that can be improved.

  The basic mechanism is that when the reference signal comparison type column ADC system in which the horizontal transfer latch 257 of the counter unit 254 and the data storage unit 256 is separated is adopted, the horizontal transfer driver is set to M (M is a positive value of 3 or more). The M input-1 output type selector is used to determine which latch is connected to the input of the horizontal transfer driver. By doing so, the horizontal transfer system Htrans is hierarchized to improve efficiency. The adjacent M column has the same structure, but is connected to different horizontal transfer channels. Therefore, when the number of horizontal transfer channels is J, the circuit configuration has a J × M column period.

  One sub-selector is arranged for M columns and one horizontal transfer driver is provided for each sub-selector. However, the number of columns corresponding to one sub-selector is arbitrary as long as there are a plurality of columns. There are various configuration examples of the sub-selector, and it may be realized by a one-stage configuration for the M input-1 output type, or M is a prime number M_k (k as “M = M_1 × M_2 × M_3 ×...”. May be prime factorized into a form of multiplication of 1 or more positive integers), and the M_k input-1 output type sub-selector may be hierarchized (in a multistage configuration). In addition, when M is a prime number, it may be hierarchized so that prime factorization can be performed by adding an appropriate numerical value α, and the unnecessary numerical value α in the layer may not be used for a predetermined stage. . This will be specifically described below.

<Horizontal data transfer system; basics of the first embodiment>
2 to 2B are diagrams for explaining the first embodiment of the horizontal data transfer system of the solid-state imaging device 1. Here, FIG. 2 is a diagram showing a basic configuration of the first embodiment of the horizontal data transfer system of the solid-state imaging device 1. 2A and 2B are diagrams showing a comparative example with respect to the first embodiment shown in FIG. 2 and 2A show the case where there are four horizontal transfer channels, and FIG. 2B shows the case where there is one horizontal transfer channel.

  In the solid-state imaging device 1 of the present embodiment, as a mechanism for reducing the parasitic capacitance of the horizontal signal line 18, the data in each data storage unit 256 is directly output to the horizontal signal line 18 via the output driver for each column. Instead, a configuration is employed in which the output is made to the horizontal signal line 18 via a smaller number of output drivers than the total number of columns in the data storage unit 256.

  Various mechanisms are conceivable for this purpose. In this embodiment, the data selector method is used to output data to the horizontal signal line 18. The data storage unit 256 has a number of latches 257 that hold data for each column (vertical signal line 19). The data selector unit 300 includes a selector unit 301 having a plurality of sub-selectors 302 and a driver unit 307 having a plurality of horizontal transfer drivers 308 (horizontal transfer DR). The sub-selector 302 is an example of a signal selection unit that selects one of the data of the latches 257 in a plurality of columns. The horizontal transfer driver 308 is an example of a transfer driver that drives the horizontal signal line 18 based on the data selected by the sub-selector 302.

  All columns of the data storage unit 256 are divided into a plurality of blocks each including M columns (M is a positive integer of 2 or more), and one horizontal transfer driver 308 is provided for each block. For each block, an M input-1 output type sub-selector 302 is provided between the horizontal transfer driver 308 and each of the M columns of latches 257. The output of the horizontal transfer driver 308 is connected to the output unit 28 (not shown) via the horizontal signal line 18 that is a bus line. The mode shown in FIG. 2 shows a case where horizontal transfer channels are provided for four channels, and also shows a case where data transfer is performed in a complementary data format, and the above-described configuration is adopted for each channel.

  The horizontal transfer system is hierarchized using the sub-selector 302, the parent hierarchy is selected by a selection transistor (details will be described later) in the horizontal transfer driver 308 controlled by the horizontal scanning unit 12, and the child hierarchy is not shown. Selection is made by the sub-selector 302 controlled by the communication / timing control unit 20.

  The first embodiment shows an example in which M = 6, and six latches 257 (latch group) are commonly input to one 6-input type sub-selector 302 (referred to as a 6-input sub-selector 302A). The output of the 6-input sub-selector 302A controls the transfer transistor of the horizontal transfer driver 308, and the horizontal transfer driver 308 drives the horizontal transfer channel. The horizontal scanning unit 12 selects a specific latch group by turning on a selection transistor in a specific horizontal transfer driver 308. The transfer transistor and the selection transistor will be described later. One horizontal transfer system Htrans0 includes six latches 257, one 6-input sub-selector 302A, and one horizontal transfer driver 308. Each 6-input sub-selector 302A is controlled by a common control wiring from the communication / timing control unit 20. That is, the communication / timing control unit 20 has a function of a selection control unit that controls each sub-selector 302 (here, 6-input sub-selector 302A) of the selector unit 301 to select data.

  There are four horizontal transfer channels, each of which has a horizontal transfer system Htrans0, and the four horizontal transfer systems Htrans0 constitute one horizontal transfer system Htrans1. Four adjacent horizontal transfer drivers 308 drive the horizontal signal lines 18_0 to 18_3 of different horizontal transfer channels. The contents of the horizontal transfer channel (horizontal signal lines 18_0 to 18_3) are read by the sense amplifier 28a of the output unit 28 (not shown), and are read out of the chip after digital processing as necessary.

  As described above, the horizontal transfer system Htrans according to the first embodiment includes the data storage unit 256 including the counter unit 254 and the horizontal transfer latch 257, and the horizontal transfer driver 308 of the data selector unit 300 is connected to the M column ( In this example, a horizontal transfer system Htrans0_k shared by 6 columns) is used, and a 6-input sub-selector 302A that determines which latch 257 is connected to the input of the horizontal transfer driver 308 is used. By sharing the horizontal transfer driver 308 in several columns, the horizontal transfer system Htrans can be hierarchized, and the efficiency of horizontal transfer can be improved. The adjacent six-column horizontal transfer system Htrans0_k has the same structure, but is connected to different horizontal transfer channels (four in this example). Therefore, in the case of the 4-channel configuration, the circuit configuration has a 24-column cycle.

  That is, horizontal signal lines 18 for four channels are provided, and each sub-selector 302 (six-input sub-selector 302A) of the selector unit 301 and each horizontal transfer driver 308 of the driver unit 307 have four channel horizontal signal lines 18_1˜. 18_4 is evenly distributed. This is for the purpose of balancing the usage states of the horizontal transfer drivers 308 and the horizontal signal lines 18_1 to 18_4 regardless of the thinning operation. This relationship is also maintained for all the vertical columns of the pixel array unit 10 (see FIG. 3A).

  The same applies when the number of inputs of the sub-selector 302 is other than 6 or when the number of channels is other than 4. When the horizontal signal lines 18 for J channels are provided, each sub-selector 302 and driver unit of the selector unit 301 are provided. The horizontal transfer drivers 308 of 307 are evenly distributed to the horizontal signal lines 18 of the J channel, and this relationship is also maintained for all the vertical columns of the pixel array unit 10.

  On the other hand, in the comparative example shown in FIGS. 2A and 2B, the output data of each latch 257 is transmitted to the horizontal signal line 18 by the individual horizontal transfer driver 308Z. As shown in FIG. 2B, the horizontal transfer driver 308Z includes a pair (two) of transfer transistors 332 and 334 and a pair (two) of selection transistors 336 and 338. Each of the transistors 332, 334, 336, 338 is an nMOS. One horizontal transfer driver 308 uses four transistors. The output data of the latch 257 is input to the gate of the transfer transistor 334, and the output data of the inverter 296 of the latch 257 is input to the gate of the transfer transistor 332.

  In the relationship between the horizontal transfer driver 308 and the horizontal signal line 18 that is a bus line connected to the output side of the horizontal transfer driver 308, the horizontal transfer system Htrans of this embodiment has M columns (6 in the first embodiment). Book) each group. The number of horizontal transfer drivers 308 connected to the horizontal signal line 18 can be reduced to 1 / M compared to the case where the horizontal transfer driver 308 is provided for each column as in the comparative example shown in FIGS. 2A and 2B. As a result, the parasitic capacitance of the horizontal transfer channel that the horizontal transfer driver 308 must drive can be reduced, and as a result, high-speed operation is realized.

  Further, the horizontal transfer driver 308 is not connected in multiple stages, no additional transistor is required on the current path that flows when the horizontal transfer driver 308 drives, and the series resistance does not increase. Regardless of the configuration of the sub-selector 302, the number of horizontal transfer drivers 308 may be one, and the series resistance when driving the horizontal signal line 18 does not increase. As a result, it is possible to reliably transfer data at a higher speed than before.

  In consideration of the number of transistors and the number of control wirings (hereinafter also referred to as CN numbers), there is almost no difference in the case of sharing one horizontal transfer driver 308 with two columns, and one horizontal transfer driver 308 with three or more columns. Sharing will be effective.

<Details of Horizontal Data Transfer System: First Embodiment>
3 to 3B are diagrams for explaining a detailed configuration example of the horizontal transfer system of the first embodiment shown in FIG. FIG. 3 shows one block (portion handled by one 6-input sub-selector 302A), and FIG. 3A shows four horizontal transfer channels in a simplified manner. FIG. 3B is a diagram illustrating a configuration example of a clocked inverter used for the latch 257.

  As shown in FIG. 3, the latch 257 includes two clocked inverters 292 and 294 and one ordinary inverter 296. “Normal” is a CMOS inverter in which a pMOS and an nMOS are cascade-connected like the inverter 409 described above. For example, as shown in FIGS. 3B (1) and (2), the clocked inverters 292 and 294 are composed of two pMOSs 290_p1 and 290_p2 and two nMOSs 290_n1 and 290_n2 connected in cascade, and four transistors are used. The Therefore, one latch 257 uses 10 transistors.

  In the clocked inverter, the connection point of each drain of the intermediate pMOS 290_p2 and nMOS 290_n1 is used as the data output terminal OUT. Here, as a usage of the clocked inverter, as shown in FIG. 3B (1), the gates of the intermediate pMOS 290_p2 and nMOS 290_n1 are connected in common to serve as the data input terminal IN, and the gate of the pMOS 290_p1 on the positive power supply side is the inverted clock. There is a first example in which the terminal XCK, the gate of the ground or negative power supply side nMOS 290_n2 is the non-inverted clock terminal CK. When the H level is input to the inverted clock terminal XCK and the L level is input to the non-inverted clock terminal CK, the pMOS 290_p1 and the nMOS 290_n2 are turned off (shut off), and the data output terminal OUT becomes a high impedance so that data passing is shut off. On the other hand, when the L level is input to the inverted clock terminal XCK and the H level is input to the non-inverted clock terminal CK, the pMOS 290_p1 and the nMOS 290_n2 are turned on (conducted), so that the data input to the data input terminal IN is inverted by the pMOS 290_p2 And output from the data output terminal OUT.

  Further, as shown in FIG. 3B (2), the gates of pMOS 290_p1 and nMOS 290_n2 on both sides are connected in common to serve as the data input IN, the gate of pMOS 290_p2 is the inverted clock terminal XCK, and the gate of nMOS 290_n1 is the non-inverted clock terminal CK. There is a second example. When the H level is input to the inverted clock terminal XCK and the L level is input to the non-inverted clock terminal CK, the pMOS 290_p2 and the nMOS 290_n1 are turned off (shut off), and the data output terminal OUT becomes a high impedance so that data passing is shut off. On the other hand, when the L level is input to the inverted clock terminal XCK and the H level is input to the non-inverted clock terminal CK, the pMOS 290_p2 and the nMOS 290_n1 are turned on (conducted). And output from the data output terminal OUT.

  The outputs of the clocked inverters 292 and 294 are connected in common and become the input of the inverter 296 and also the input of the 6-input sub-selector 302A. Data DATA <K> of the counter unit 254 is input to the clocked inverter 292, and output data of the inverter 296 is input to the clocked inverter 294.

  The load signal CRDL included in the control signal CN9 from the communication / timing control unit 20 is input to the non-inverted clock terminal CK of the clocked inverter 292 and the inverted clock terminal XCK of the clocked inverter 294. The load signal XCRDL included in the control signal CN9 from the communication / timing control unit 20 is input to the inverted clock terminal XCK of the clocked inverter 292 and the non-inverted clock terminal CK of the clocked inverter 294. The load signal CRDL and the load signal XCRDL have a logic inversion (complementary relationship) relationship.

  In this configuration, each data DATA <K> of the counter unit 254 is logically inverted (complementary) by the clocked inverter 292 of the latch 257 so that the data XDATA <K> is supplied to the 6-input sub-selector 302A. Become.

  The 6-input sub-selector 302A has six transfer gates having a CMOS configuration that function as an analog switch in which an nMOS 322 and a pMOS 324 are connected in parallel in a CMOS type. This transfer gate having a CMOS structure is formed by connecting an nMOS 322 and a pMOS 324 in a complementary connection in parallel. A transfer gate having a CMOS structure is also called a transmission gate or a transmission switch. Hereinafter, a pair of nMOS 322 and pMOS 324 is referred to as a CMOS switch 326.

  Each gate of each nMOS 322 receives a subselect signal SUBSEL included in the control signal CN9 from the communication / timing control unit 20, and each gate of each pMOS 324 is included in the control signal CN9 from the communication / timing control unit 20. Subselect signal XSUBSEL is input separately. The sub-select signal SUBSEL and the sub-select signal XSUBSEL have a logic inversion (complementary relationship) relationship. That is, the 6-input sub-selector 302A is controlled by 12 control wires. These 12 control wirings are common to all the 6-input sub-selectors 302A. Even when a large number of sub-selectors 302 (6-input sub-selectors 302A) are used, it can be said that there is no significant increase in the number of control wirings from the communication / timing control unit 20.

  When the gate of the nMOS 322 is high and the gate of the pMOS 324 is low, the transmission gate, that is, the CMOS switch 326 outputs the input data as it is. The analog switch may be a transistor switch using only one of the nMOS 322 and the pMOS 324, but in this case, there are problems of on-resistance and threshold voltage Vth although the number of elements is small. In addition, although related to the threshold voltage Vth, when used as a switch for digital data, the nMOS can pass the L level but cannot pass the H level, and the pMOS can pass the H level but cannot pass the L level. appear. Therefore, in this example, although the number of elements increases, a transmission gate that functions as an ideal switch that can pass both the L level and the H level by connecting the nMOS 322 and the pMOS 324 in parallel in a complementary connection form is adopted. .

  Output data is input from the corresponding latch 257 to each input of each of the nMOS 322 and pMOS 324 of the six CMOS switches 326_0 to 326_5. The outputs of the six nMOSs 322 and pMOS 324 are connected in common, and the output data is input to the horizontal transfer driver 308. The output of the 6-input sub-selector 302A is not complementary (differential) but single-ended.

  The horizontal transfer driver 308 has a configuration in which one inverter 331 is added to the horizontal transfer driver 308Z shown in FIG. 2B. The inverter 331 is a CMOS inverter in which pMOS and nMOS are connected in cascade. Therefore, one horizontal transfer driver 308 uses six transistors. The input terminal of the inverter 331 and the gate of the transfer transistor 334 are connected in common, and output data from the six nMOSs 322 and pMOS 324 constituting the six-input sub-selector 302A is input. The output data of the inverter 331 is input to the gate of the transfer transistor 332.

  Each source of the transfer transistors 332 and 334 is grounded. The drain of the transfer transistor 332 is connected to the source of the selection transistor 336, and the drain of the transfer transistor 334 is connected to the source of the selection transistor 338. The drain of the selection transistor 336 is connected to the horizontal signal line 18a for non-inverted data (D0), and the drain of the selection transistor 338 is connected to the horizontal signal line 18b for inverted data (XD0). The gates of the selection transistors 336 and 338 are connected in common and the selection control signal MSEL from the horizontal scanning unit 12 is input. In order to increase the speed, horizontal transfer employs current transfer using a differential signal line pair.

  Transfer transistors 332 and 334 for driving the horizontal signal line 18 are provided for each 6-input sub-selector 302A (that is, a latch group), and the selection transistors 336 and 338 perform selection of a large number of 6-input sub-selectors 302A. A configuration for transferring is used. This can be easily realized by each series circuit of the transfer transistor 332 and the selection transistor 336 or the transfer transistor 334 and the selection transistor 338. Note that the order of arrangement of the transfer transistor 332 and the selection transistor 336 or the transfer transistor 334 and the selection transistor 338 connected in series may be reversed.

  When the gates of the transfer transistor 332 and the selection transistor 336 are at the H level, the transistors 332 and 336 are turned on, and a current is supplied from the sense amplifier 28a not shown through the horizontal signal line 18a for non-inverted data. Flows to the ground side. Similarly, when the gates of the transfer transistor 334 and the selection transistor 338 are at the H level, the transistors 334 and 338 are turned on, and the sense amplifier 28a (not shown) is connected via the horizontal signal line 18b for inverted data. Current flows to the ground side. For example, when the sense amplifier 28a is on the left in the figure, the direction in which current flows from left to right is positive.

  That is, the horizontal transfer driver 308 senses the non-inverted data of the latch 257 based on the selection by the 6-input sub-selector 302A via the horizontal signal line 18a when both the transfer transistor 332 and the selection transistor 336 are turned on. Operate to forward to 28a. Further, when both the transfer transistor 334 and the selection transistor 338 are turned on, the horizontal transfer driver 308 transmits the inverted data of the latch 257 based on the selection by the 6-input sub-selector 302A via the horizontal signal line 18b. Operate to transfer to.

  The horizontal scanning unit 12 has a large number of DFFs 12X (delay flip-flops), but there is one DFF 12X for each of the 6-input sub-selectors 302A. The DFF 12X supplies an active H selection control signal MSEL to the gates of the selection transistors 336 and 338.

  The data DATA <K> of the counter unit 254 is held as data XDATA <K> which is held in six latches 257 and logically inverted (complementary), and one is selected by the single-ended 6-input sub-selector 302A and horizontal. Input to the transfer driver 308. One data XDATA <K> selected by the 6-input sub-selector 302A is input to the inverter 331 of the horizontal transfer driver 308 and inverted.

  Here, one data selected by the 6-input sub-selector 302A drives one selection transistor 338 among the selection transistors 336 and 338 in the horizontal transfer driver 308, and the data inverted by the inverter 331 is horizontal The other selection transistor 336 among the selection transistors 336 and 338 in the transfer driver 308 is driven.

  The horizontal transfer driver 308 supplies an active H selection control signal MSEL to the gates of the selection transistors 336 and 338 in one set of four horizontal transfer driver sets. That is, the output of the DFF 12X of the horizontal scanning unit 12 selects the selection transistors 336 and 338 in the horizontal transfer driver 308.

  By making the 6-input sub-selector 302A single-ended, the number of transistors (hereinafter also referred to as TR number) can be saved. The output data of the 6-input sub-selector 302A is converted into complementary data (differential signal) by the inverter 331 in relation to the input of the inverter 331, and the complementary (differential) type horizontal transfer channel (two horizontal signal lines 18a). , 18b). In this case, the sense amplifier 28a reproduces data with a differential amplifier circuit.

  If digital data is transferred as complementary data and is reproduced by a differential amplifier circuit provided in a subsequent sense amplifier 28a, the influence can be canceled even if noise is mixed in the horizontal signal lines 18a and 18b. Further, an amplifier circuit is further interposed between the complementary horizontal signal lines 18a and 18b and the sense amplifier 28a to reduce the amplitude on the horizontal signal lines 18a and 18b side and increase the amplitude on the input side of the sense amplifier 28a. By doing so, the problem caused by the parasitic capacitance on the horizontal signal lines 18a and 18b which are bus lines can be improved. This is because a transfer with small amplitude information consumes less power and a high-speed transfer operation is possible than a transfer with large amplitude information.

  Of course, it is not essential to transfer data in a complementary manner as described above, and data transfer using only one of the horizontal signal lines 18a and 18b may be used. When only the horizontal signal line 18 a side is used, the transfer transistor 334 and the selection transistor 338 can be removed from the horizontal transfer driver 308. When only the horizontal signal line 18 b side is used, the inverter 331, the transfer transistor 332, and the selection transistor 336 can be removed from the horizontal transfer driver 308.

  By making the 6-input sub-selector 302A single-ended, the number of transistors can be saved. The output of the 6-input selector is converted into a differential signal by an inverter and drives a differential transfer channel composed of two wires.

  In FIG. 3A, 96 columns of the horizontal transfer system are shown in a simplified manner. However, the horizontal transfer system Htrans0 having the configuration shown in FIG. 3 is prepared for four horizontal transfer channels, and the configuration shown in FIG. The horizontal transfer system Htrans1 is configured. In FIG. 3A, four horizontal transfer systems Htrans1 are arranged. The horizontal transfer driver 308 is selected in units of four. The four horizontal transfer drivers 308 of each group (horizontal transfer system Htrans1) are collectively referred to as a horizontal transfer driver set 309. A selection control signal MSEL is commonly supplied from the DFF 12X of the horizontal scanning unit 12 to the horizontal transfer driver set 309 (four horizontal transfer drivers 308 in the same horizontal transfer system Htrans1).

<Basic Operation Example of Horizontal Transfer System: First Embodiment>
FIG. 4 and FIG. 4A are diagrams for explaining the basic operation of the horizontal transfer system Htrans of the first embodiment with specific data examples. 4 shows a data example of the horizontal transfer system Htrans0, and FIG. 4A is a timing chart for explaining a basic operation of the horizontal transfer system Htrans1 (four horizontal transfer systems Htrans0) in the data example of FIG.

  In FIG. 4, a data example of a predetermined bit position (for example, the 0th bit) held by the latch 257 is shown in the latch 257 portion. In the latch 257, “0” or “1” is stored based on the result of AD conversion performed on the pixel information detected by the unit pixel 3 of the pixel array unit 10 by the AD conversion unit 250. For example, in the horizontal transfer system Htrans0_0, “010101” appears from the upstream side in the horizontal scanning direction, and this appears as output data D0 <0>, which is logically inverted (complementary) and output as output data XD0 <0>. Appear.

  In the horizontal transfer system Htrans0_1, “101011” is obtained from the upstream side in the horizontal scanning direction, and this appears as output data D0 <1>, which is logically inverted (complementary) and appears as output data XD0 <1>. In the horizontal transfer system Htrans0_2, “000011” appears from the upstream side in the horizontal scanning direction, and this appears as output data D0 <2>, which is logically inverted (complementary) and appears as output data XD0 <2>. In the horizontal transfer system Htrans0_3, “101110” appears from the upstream side in the horizontal scanning direction, and this appears as output data D0 <3>, which is logically inverted (complementary) and appears as output data XD0 <3>.

  As shown in FIG. 4A, the DFF 12X of the horizontal scanning unit 12 sequentially sets the selection control signal MSEL to active H sequentially one by one. Accordingly, one set of four horizontal transfer driver sets 309 among the horizontal transfer drivers 308 is sequentially selected.

  During the period when the specific selection control signal MSEL is active H, the communication / timing control unit 20 sequentially turns the six subselect signals SUBSEL <K> to active H and the six subselect signals XSUBSEL < K> is sequentially set to active L. As a result, a specific latch 257 in the latch group (six latches 257) of the horizontal transfer system Htrans0 is selected.

  The four portions of D0 <k> and XD0 <k> are charts showing whether or not current flows through the horizontal signal lines 18a and 18b. The current flows at the H level and represents the potential. Absent.

<Modified Operation Example of Horizontal Transfer System: First Embodiment>
FIG. 5 is a diagram for explaining a deformation operation of the horizontal transfer system Htrans of the first embodiment in the solid-state imaging device 1 of the present embodiment using the 6-input sub-selector 302A. Here, FIG. 5 (1) is a diagram for explaining the 1/2 thinning-out operation. FIG. 5B is a diagram for explaining the 1/3 thinning-out operation. In the figure, the hatched latch 257 has “latch data” and is a transfer target at the time of the thinning operation, and the non-hatched latch 257 has “latch data not” and is a non-transfer target. This also applies to the thinning-out operation of other embodiments described later.

  As shown in FIG. 5A, at the time of 1/2 thinning, every other data of the latch 257 is horizontally transferred. The data in every other latch 257 to be transferred is input to the odd three input terminals of the 6-input sub-selector 302A, for example, and sent to the horizontal transfer driver 308. At this time, for every other 6-input sub-selector 302A, the odd-numbered three input terminals with respect to the 6-input terminals are used in the same relationship, and all the 6-input sub-selectors 302A and 302A A horizontal transfer driver 308 is used. In the figure, all the horizontal transfer drivers 308 are shaded to indicate this. Therefore, at the time of 1/2 decimation, the usage state of the horizontal transfer channel is balanced, so that the horizontal transfer channel can be used efficiently.

  Further, as shown in FIG. 5B, at the time of 1/3 thinning, the data of the latch 257 is horizontally transferred every two. The data of every second latch 257 to be transferred is input to the two input terminals of the kth and k + 3th (k is any one of 1 to 3) of the 6-input sub-selector 302A and sent to the horizontal transfer driver 308, for example. It is done. At this time, for every other 6-input sub-selector 302A, the k-th and k + 3-th two input terminals are used in the same relationship with respect to the 6-input terminals, and all 6-inputs are used. A sub-selector 302A and a horizontal transfer driver 308 are used. In the figure, all the horizontal transfer drivers 308 are shaded to indicate this. Accordingly, the horizontal transfer channel usage state is balanced even during 1/3 decimation, so that the horizontal transfer channel can be used efficiently.

  As described above, by using the 6-input sub-selector 302A, the horizontal transfer channel can be efficiently used for both 1/2 thinning and 1/3 thinning. Even during thinning, all horizontal transfer channels can be used effectively, and the efficiency during thinning can be improved. The frame rate can be improved without increasing the number of horizontal transfer channels.

  Here, it is shown that the horizontal transfer channel can be efficiently used for both 1/2 thinning and 1/3 thinning in the case of 6 inputs. However, the number of inputs of the sub-selector 302 is 6 (= 2 × 3). The horizontal transfer channel can be efficiently used for both 1/2 thinning and 1/3 thinning as long as there is a relationship of multiples of). In this example, the term “multiple of 6” is used because both 1/2 decimation and 1/3 decimation are taken into account. Each decimation ratio is 1/2 or 1/3. Based on “6” which is the least common multiple of the reciprocal (2, 3).

  It goes without saying that if the ratio of each thinning is different from that in this example, the optimum number of inputs to the sub-selector 302 will be different accordingly. In other words, when dealing with a plurality of thinning modes having different thinning levels, it is not sufficient to use each of the sub-selectors 302 with an input number having a reciprocal number corresponding to any thinning ratio. The number of inputs handled by one sub-selector 302 may be aligned with the least common multiple of the reciprocal of each thinning rate. This point will be described in detail in the later-described 2-input sub-selector and 3-input sub-selector.

<Summary: First Embodiment>
6 and 6A are tables summarizing the effects of the horizontal transfer system Htrans of the first embodiment in the solid-state imaging device 1 of the present embodiment in comparison with the prior art. FIG. 6 is a diagram comparing the operational effects of the horizontal transfer system Htrans disclosed in the first embodiment and Japanese Patent Laid-Open No. 2006-148509. FIG. 6A is a chart summarizing the effects of the horizontal transfer system Htrans of the first embodiment in comparison with the comparative example (hereinafter referred to as a comparative example) shown in FIGS. 2A and 2B.

  As shown in FIG. 6 (1), in the horizontal transfer system Htrans of Japanese Patent Application Laid-Open No. 2006-148509, the horizontal transfer driver 308 is connected in multiple stages. Additional transistors are required, increasing the series resistance. On the other hand, as shown in FIG. 6 (2), in the horizontal transfer system Htrans of the first embodiment, data is selected in the preceding stage of the horizontal transfer driver 308, and the horizontal transfer driver 308 is 1 level. A step may be used. No additional transistors are required on the current path that flows when the horizontal transfer driver 308 drives, and the series resistance does not increase. Compared with the comparative example, the horizontal transfer driver 308 can be reduced to 1/6, and since there is no cascade connection of the horizontal transfer driver 308, high-speed operation can be realized with certainty.

  Further, as shown in FIG. 6A, the horizontal transfer system Htrans of the first embodiment has various other advantages. For example, when the number of transistors connected in series to the horizontal signal line 18 is compared between the comparative example 1 and the horizontal transfer system Htrans of the first embodiment, the number of transistors in series in the first embodiment is smaller. There are few, and it operates faster. According to the horizontal transfer simulation, it was found that the speed was increased by about 16% compared to the general case such as the comparative example.

  Also, the pair of transfer transistors 332 and 334 and the pair of selection transistors 336 and 338 in the horizontal transfer driver 308 are all doubled in gate width, and the same current flows through these transistors 332, 334, 336, and 338. It has been found that by doubling the gate width of some of the transistors in the sense amplifier 28a through which current flows, the speed is increased by about 32% compared to a general case like the comparative example.

  As described above, at the time of 1/2 thinning or 1/3 thinning, only the control wiring of the 6-input sub-selector 302A, which is a child hierarchy, is skipped and output, so that all horizontal transfers are also performed at 1/2 thinning and 1/3 thinning. The system Htrans can be used effectively and horizontal transfer can be performed efficiently.

  In addition, the portion of the horizontal transfer system Htrans of this embodiment that does not include the horizontal scanning unit 12 includes six latches 257 (TR number = 10), one 6-input sub-selector 302A (TR number = 12), and the like. One horizontal transfer driver 308 (the number of TRs = 6) uses 78 (= 10 × 6 + 12 + 6) transistors per 6 columns and 1 digit. On the other hand, the parts not including the horizontal scanning unit 12 of the horizontal transfer system Htrans of the comparative example are six latches 257 (TR number = 10) and six horizontal transfer drivers 308Z (TR number = 4). 84 (= 10 × 6 + 4 × 6) transistors are used per column. Therefore, in the horizontal transfer system Htrans of the first embodiment, the number of transistors per digit of 6 columns can be reduced by 6 compared to the comparative example.

  This is because the horizontal transfer driver 308 is shared and reduced by the six latches 257. Therefore, even if the pair of transfer transistors 332 and 334 and the pair of selection transistors 336 and 338 in the horizontal transfer driver 308 are all doubled in gate width, the increase in area is limited. Further, the number of horizontal transfer drivers 308 to be controlled is reduced to 1/6, so that the scale of the horizontal scanning unit 12 can be reduced to about 1/6.

  However, 12 control wires for controlling the 6-input sub-selector 302A are required. These twelve control lines transmit a long-distance signal along the data storage unit 256 or the horizontal scanning unit 12, and need to be thickened in some cases.

  As described above, the horizontal transfer system Htrans of the first embodiment can perform transfer at a higher speed than the comparative example even when thinning is not performed, and the degree of increase in speed is 16 in the simulation as compared with the comparative example. % To about 32%. In addition, all horizontal transfer channels can be effectively used even during thinning, and a horizontal transfer system that improves the efficiency during thinning can be achieved. The frame rate can be improved without increasing the number of horizontal transfer channels, and the number of transistors can be reduced.

  Note that, ultimately, all the latches 257 of the data storage unit 256 are selected by one sub-selector 302 so that only one horizontal transfer driver 308 is connected to the horizontal signal line 18. Conceivable. However, in this case, the number of control wirings from the communication / timing control unit 20 that controls the number of transistors constituting the sub-selector 302 and the data selection operation of the sub-selector 302 is not good. It is considered realistic that the number of columns (number of latches 257) that one sub-selector 302 is responsible for is about several to several tens.

  In other words, the selector unit 301 includes a plurality of sub-selectors 302, and the driver unit 307 includes one horizontal transfer driver 308 for each of the plurality of sub-selectors 302. Then, the sub-selector 302 is selected by the selection operation of the selection transistors 336 and 338 of the horizontal transfer driver 308, and the sub-selector 302 specifies a latch group (for example, latches 257 for six columns) in charge of the sub-selector 302. The latch 257 is selected. It is possible to balance the number of transistors and control wirings of the sub-selector 302 and the number of horizontal transfer drivers 308 connected to the horizontal signal line 18 (the resulting load capacitance and parasitic capacitance).

<Horizontal Data Transfer System; Second Embodiment>
FIG. 7 is a diagram for explaining a second embodiment of the horizontal data transfer system of the solid-state imaging device 1. The second embodiment is a modification focusing on the fact that the sub-select signal SUBSEL and the sub-select signal XSUBSEL for controlling the gates of the nMOS 322 and pMOS 324 of the sub-selector 302 have a logic inversion (complementary relationship) relationship. Each of the second to seventh embodiments is characterized by the configuration of the sub-selector 302 and is the same as the first embodiment except for the other points. Therefore, in each drawing, only the sub-selector 302 is shown. . A plurality of sub-selectors 302 are arranged in the selector unit 301, and a common control wiring from the communication / timing control unit 20 is used for them, and it is also controlled by a common control signal in the first implementation. It is the same as the form.

  Specifically, the second embodiment also shows an example in which M = 6, and six latches 257 are commonly input to one 6-input sub-selector 302B. Here, the 6-input sub-selector 302B of the second embodiment has an inverter 328 on the gate side of each pMOS 324 to which the sub-select signal XSUBSEL is input. A sub-select signal SUBSEL is input to each inverter 328 in common with the gate of each nMOS 322. Although illustration is omitted, an inverter 328 may be provided on the gate side of each nMOS 322 to which the subselect signal SUBSEL is input, and the subselect signal XSUBSEL may be input to each inverter 328 in common with the gate of each pMOS 324. .

  Thus, in the second embodiment, one of the sub-select signal SUBSEL and the sub-select signal XSUBSEL is not included in the control signal CN9 from the communication / timing controller 20, but the other is logically inverted (complementary) by the inverter 328. ) To generate the corresponding signal by itself. In this way, the 6-input sub-selector 302B is controlled by the 6 control wirings from the communication / timing control unit 20. The 6-input sub-selector 302B is larger than the 6-input sub-selector 302A of the first embodiment by the addition of the inverter 328, but there is an advantage that the number of control wirings from the communication / timing control unit 20 can be reduced.

  As the number of corresponding input terminals of the sub-selector 302 increases, the control wiring for the sub-select signal SUBSEL and sub-select signal XSUBSEL for controlling the gates of the nMOS 322 and the pMOS 324 increases, and the control wiring bus needs to be thickened. By adopting the mechanism of the second embodiment, the number of control wirings can be halved, which is advantageous in terms of layout.

  The other basic matters are the same as those of the 6-input sub-selector 302A of the first embodiment, and there is no cascade connection of the horizontal transfer driver 308 regardless of the presence or absence of thinning, and the series resistance does not increase. In addition, it is possible to enjoy the same effect that, for example, all horizontal transfer channels can be used effectively at the time of thinning and the efficiency at the time of thinning can be improved.

<Horizontal Data Transfer System; Third Embodiment>
FIG. 8 is a diagram for explaining a third embodiment of the horizontal data transfer system of the solid-state imaging device 1. In the third embodiment, all columns of the data storage unit 256 are divided into a plurality of blocks each including two columns, and one horizontal transfer driver 308 is provided for each block. For each block, a 2-input / 1-output type sub-selector 302 (referred to as a 2-input sub-selector 302C) is provided between the horizontal transfer driver 308 and each of the two rows of latches 257. There are four horizontal transfer channels. As in the first embodiment, the case of transferring data in a complementary data format is shown, and the above-described configuration is adopted for each channel. The 2-input sub-selector 302C may use a 2-input selector 502V described later.

  The reduction effect of the horizontal transfer driver 308 is inferior to that of the first and second embodiments using the 6-input sub-selectors 302A and 302B. Since there is no cascade connection of the transfer driver 308, high-speed operation can be reliably realized.

  FIG. 8A is a diagram for explaining the operation of the horizontal transfer system Htrans of the third embodiment using the 2-input sub-selector 302C. Here, FIG. 8A (1) is a diagram for explaining an operation of 1/2 decimation, and FIG. 8A (2) is a diagram for explaining an operation of 1/3 decimation.

  As shown in FIG. 8A (1), at the time of 1/2 thinning, every other data of the latch 257 is horizontally transferred. The data of every other latch 257 to be transferred is input to one input terminal of the 2-input sub-selector 302C and sent to the horizontal transfer driver 308. At this time, all the two-input sub-selectors 302C and the horizontal transfer driver 308 are used for every other one. In the figure, the horizontal transfer driver 308 is shaded to indicate this. Therefore, at the time of 1/2 decimation, the usage state of the horizontal transfer channel is balanced, so that the horizontal transfer channel can be used efficiently.

  On the other hand, as shown in FIG. 8A (2), at the time of 1/3 decimation, the data of the latch 257 is horizontally transferred every two. The data of every second latch 257 to be transferred is input to one input terminal of the 2-input sub-selector 302C or the other input terminal of the 2-input sub-selector 302C and sent to the horizontal transfer driver 308. At this time, the 2-input sub-selector 302C and the horizontal transfer driver 308 that are not used for every other two are generated, and when data is sequentially transferred, a horizontal transfer channel that is skipped without being used is generated. In the drawing, in order to show this, the horizontal transfer driver 308 that is used is indicated by shading, and the horizontal transfer driver 308 that is not used is indicated without shading. Therefore, at the time of 1/3 decimation, the horizontal transfer channel usage state becomes unbalanced, and the horizontal transfer channel cannot be used efficiently.

  This is different from the case where the horizontal transfer channel can be efficiently used for both 1/2 thinning and 1/3 thinning in the first and second embodiments using the 6-input sub-selectors 302A and 302B. .

  Other basic matters are the same as those of the 6-input sub-selectors 302A and 302B of the first and second embodiments, and there is no cascade connection of the horizontal transfer driver 308, and the series resistance does not increase. You can enjoy the effect of being able to.

<Horizontal Data Transfer System; Fourth Embodiment>
FIG. 9 is a diagram for explaining a fourth embodiment of the horizontal data transfer system of the solid-state imaging device 1. In the fourth embodiment, all columns of the data storage unit 256 are divided into a plurality of blocks each including three columns, and one horizontal transfer driver 308 is provided for each block. For each block, a 3-input / 1-output type sub-selector 302 (referred to as a 3-input sub-selector 302D) is provided between the horizontal transfer driver 308 and each of the three rows of latches 257. There are four horizontal transfer channels. As in the first embodiment, the case of transferring data in a complementary data format is shown, and the above-described configuration is adopted for each channel.

  In the mechanism of the fourth embodiment, the reduction effect of the horizontal transfer driver 308 is inferior to that of the first and second embodiments using the 6-input sub-selectors 302A and 302B, but the third embodiment using the 2-input sub-selector 302C. Better than. The horizontal transfer driver 308 can be reduced to 1/3 compared to the first comparative example, and since there is no cascade connection of the horizontal transfer driver 308, high-speed operation can be realized with certainty.

  FIG. 9A is a diagram for explaining the operation of the horizontal transfer system Htrans of the fourth embodiment using the 3-input sub-selector 302D. Here, FIG. 9A (1) is a diagram for explaining an operation of 1/3 decimation, and FIG. 9A (2) is a diagram for explaining an operation of 1/2 decimation.

  As shown in FIG. 9A (1), at the time of 1/3 decimation, the data in the latch 257 is horizontally transferred every two. The data of every second latch 257 to be transferred is input to the k-th input terminal of the 3-input sub-selector 302D (k is any one of 1 to 3) and sent to the horizontal transfer driver 308. As each 3-input sub-selector 302D, the k-th input end is used in the same relationship with respect to the 3-input end, and all the 3-input sub-selectors 302D and the horizontal transfer driver 308 are used. In the figure, all the horizontal transfer drivers 308 are shaded to indicate this. Therefore, at the time of 1/3 decimation, the horizontal transfer channel usage state is balanced, so that the horizontal transfer channel can be used efficiently.

  On the other hand, as shown in FIG. 9A (2), at the time of 1/2 decimation, every other data of the latch 257 is horizontally transferred. The data of every other latch 257 to be transferred is input to the first and third of the 3-input sub-selector 302D or the second of the 3-input sub-selector 302D and sent to the horizontal transfer driver 308. The three-input sub-selector 302D is generated using the first and third two input terminals and using the second input terminal only. When data is sequentially transferred, a three-input sub-selector 302D that uses two input terminals, a horizontal transfer driver 308 that is used twice in succession, and one input terminal are used. The three-input sub-selector 302D to be received and the horizontal transfer driver 308 that is used only once are generated. In the drawing, in order to show this, the horizontal transfer driver 308 that is used twice consecutively is indicated by shading, and the horizontal transfer driver 308 that is used only once is indicated without shading. Therefore, at the time of 1/2 decimation, the usage state of the horizontal transfer channel becomes unbalanced and the horizontal transfer channel cannot be used efficiently.

  This is different from the case where the horizontal transfer channel can be efficiently used for both 1/2 thinning and 1/3 thinning in the first and second embodiments using the 6-input sub-selectors 302A and 302B. .

  Other basic matters are the same as those of the 6-input sub-selectors 302A and 302B of the first and second embodiments, and there is no cascade connection of the horizontal transfer driver 308, and the series resistance does not increase. You can enjoy the effect of being able to.

<Horizontal Data Transfer System; Fifth Embodiment>
FIG. 10 is a diagram for explaining a fifth embodiment of the horizontal data transfer system of the solid-state imaging device 1. In the fifth embodiment, all the columns of the data storage unit 256 are divided into a plurality of blocks each including four columns, and one horizontal transfer driver 308 is provided for each block. For each block, a 4-input / 1-output type sub-selector 302 (referred to as a 4-input sub-selector 302E) is provided between the horizontal transfer driver 308 and each of the four rows of latches 257. There are four horizontal transfer channels. As in the first embodiment, the case of transferring data in a complementary data format is shown, and the above-described configuration is adopted for each channel.

  Although the reduction effect of the horizontal transfer driver 308 is inferior to that of the first and second embodiments using the 6-input sub-selectors 302A and 302B, the third embodiment using the 2-input sub-selector 302C and the 3-input sub-selector 302D are used. It is superior to the fourth embodiment. The horizontal transfer driver 308 can be reduced to ¼ that of the first comparative example, and since there is no cascade connection of the horizontal transfer driver 308, high-speed operation can be reliably realized.

  FIG. 10A is a diagram for explaining the operation of the horizontal transfer system Htrans of the fifth embodiment using the 4-input sub-selector 302E. Here, FIG. 10A (1) is a diagram for explaining the ¼ decimation operation, and FIG. 8A (2) is a diagram for explaining the ３ decimation operation.

  As shown in FIG. 10A (1), at the time of 1/4 thinning, the data of the latch 257 is horizontally transferred every third. The data of every fourth latch 257 to be transferred is input to the k-th input terminal of the 4-input sub-selector 302E (k is any one of 1 to 4) and sent to the horizontal transfer driver 308. For each 4-input sub-selector 302E, the k-th input terminal is used in the same relationship with respect to the 4-input terminals, and all 4-input sub-selectors 302E and horizontal transfer drivers 308 are used. In the figure, all the horizontal transfer drivers 308 are shaded to indicate this. Therefore, at the time of 1/4 thinning, the horizontal transfer channel usage state is balanced, so that the horizontal transfer channel can be used efficiently.

  Although not shown, in the case of 1/2 decimation, two of the four input terminals of the 4-input sub-selector 302E are used, and each 4-input sub-selector 302E is used in the same relationship, and all the 4-input sub-selectors are used. A selector 302E and a horizontal transfer driver 308 are used. When sequentially transferring data, all horizontal transfer drivers 308 are used twice in succession. Accordingly, the horizontal transfer channel usage state is balanced even during 1/2 thinning, so that the horizontal transfer channel can be used efficiently.

  On the other hand, as shown in FIG. 10A (2), at the time of 1/3 decimation, the data of the latch 257 is horizontally transferred every two. The data of every second latch 257 to be transferred is input to the first and fourth, or only the third, or only the second of the 4-input sub-selector 302E and sent to the horizontal transfer driver 308. As for the 4-input sub-selector 302E, there are a type in which the first and fourth two input ends are used, and a case in which only the third and only the second input ends are used. When data is sequentially transferred, a 4-input sub-selector 302E that uses two input terminals, a horizontal transfer driver 308 that is used twice consecutively, and one input terminal are used. In response to this, the 4-input sub-selector 302E and the horizontal transfer driver 308 that is used only once are generated. In the drawing, in order to show this, the horizontal transfer driver 308 that is used twice consecutively is indicated by shading, and the horizontal transfer driver 308 that is used only once is indicated without shading. Therefore, at the time of 1/3 decimation, the usage state of the horizontal transfer channel becomes unbalanced and the horizontal transfer channel cannot be used efficiently.

  This is different from the case where the horizontal transfer channel can be efficiently used for both 1/2 thinning and 1/3 thinning in the first and second embodiments using the 6-input sub-selectors 302A and 302B. .

  Other basic matters are the same as those of the 6-input sub-selectors 302A and 302B of the first and second embodiments, and there is no cascade connection of the horizontal transfer driver 308, and the series resistance does not increase. You can enjoy the effect of being able to.

<Horizontal Data Transfer System; Sixth Embodiment>
FIGS. 11 to 11C are diagrams for explaining a sixth embodiment of the horizontal data transfer system of the solid-state imaging device 1. In the sixth embodiment, the input number M of the sub-selector 302 is primed into a form of multiplication of a prime number M_k (k is a positive integer of 1 or more) as “M = M_1 × M_2 × M_3 ×. , M_k input-1 output type sub-selector is hierarchized (in a multi-stage configuration). In a stage where a plurality of M_k input-1 output type sub-selectors are arranged in parallel, the sub-select signal SUBSEL and the sub-select signal XSUBSEL are commonly supplied to the gates of the nMOS 322 and the pMOS 324, so that the control wiring as a whole The number is reduced and the merit on the wiring layout is enjoyed.

  For example, in FIG. 11, the 4-input sub-selector 302F is configured by forming the 2-input selector into a two-stage hierarchy. Here, as the two-input selector, a two-input / one-output type signal selection circuit (two-input selector 502V) in which two CMOS switches 326 are connected in parallel is used as shown in the figure. One two-input selector 502V uses four transistors. In the 2-input selector 502V, the gates of the pMOS and the nMOS are connected in common with the other CMOS switch 326. In the same stage, these gates are connected in common.

  Then, two 2-input selectors 502V_1 and 502_2 are arranged in the first stage, and a 2-input selector 502V_3 that receives their outputs is arranged in the second stage. In each stage, a pair of sub-select signals having a complementary relationship are commonly input to the 2-input selector 502V. It is also possible to adopt a mechanism in which one is logically inverted and the other is generated. For example, the sub-select signals SUBSEL_A and XSUBSEL_A are commonly supplied to the first-stage 2-input selectors 502V_1 and 502_2. Sub-select signals SUBSEL_B and XSUBSEL_B are supplied to the second input selector 502V_3. One of input 1 and input 2 is selected by the 2-input selector 502V_1, and one of input 3 and input 4 is selected by the 2-input selector 502V_2. One of the two signals selected by the two two-input selectors 502V_1 and 502V_2 is selected by the two-input selector 502V_3.

  In the 4-input sub-selector 302F having such a structure, the number of transistors is 4 × 3 = 12, and the number of control wirings is 2 × 2 = 4. On the other hand, when the 4-input sub-selector 302 is simply configured without adopting such a mechanism, the number of transistors is 4 × 2 = 8 and the number of control wirings is 4 × 2 = 8. The 4-input sub-selector 302F has an advantage that the number of control wirings from the communication / timing control unit 20 can be reduced although the number of transistors is increased.

  In FIG. 11A, a 6-input sub-selector 302G is configured by hierarchizing a 2-input sub-selector 302C and a 3-input sub-selector 302D into two stages. If 6 is prime factorized, it becomes “2 × 3”, and there are two possible ways of arranging each stage to support 6 inputs: “2 inputs → 3 inputs” and “3 inputs → 2 inputs”.

  In the 6-input sub-selector 302G_1 of the first example shown in FIG. 11A (1), three 2-input selectors 502V_1, 502V_2, and 502V_3 (each CN number = 2, each TR number = 4) are arranged in the first stage, and these 3 input sub-selector 302D (CN number = 3 × 2, TR number = 3 × 2) is arranged in the second stage. The sub-select signals SUBSEL_A and XSUBSEL_A are commonly supplied to the first input selectors 502V_1, 502V_2, and 502V_3. One of input 1 and input 2 is selected by 2-input selector 502V_1, one of input 3 and input 4 is selected by 2-input selector 502V_2, and one of input 5 and input 6 is selected by 2-input selector 502V_3 Is selected. One of the three signals selected by the three two-input selectors 502V_1, 502V_2, and 502V_3 is selected by the three-input sub-selector 302D.

  In the 6-input sub-selector 302G_1 having such a mechanism, the number of transistors is 4 × 3 + 3 × 2 = 18, and the number of control wirings is 2 + 3 × 2 = 8. On the other hand, when the 6-input type sub-selector 302 is simply configured without adopting such a mechanism, the number of transistors is 6 × 2 = 12, and the number of control wirings is 6 × 2 = 12. The 6-input sub-selector 302G_1 has an advantage that the number of control wirings from the communication / timing control unit 20 can be reduced, although the number of transistors is increased.

  In the 6-input sub-selector 302G_2 of the second example shown in FIG. 11A (2), two 3-input sub-selectors 302D_1 and 302D_2 (each CN number = 3 × 2, each TR number = 3 × 2) are provided in the first stage. A two-input selector 502V (CN number = 2, TR number = 4) that receives these outputs is arranged in the second stage. The sub-select signals SUBSEL <0>, XSUBSEL <0>, SUBSEL <1>, XSUBSEL <1>, SUBSEL <2>, and XSUBSEL <2> are commonly supplied to the first stage 3-input sub-selectors 302D_1 and 302D_2 To do. One of input 1, input 2 and input 3 is selected by 3-input sub-selector 302D_1, and one of input 4, input 5, and input 6 is selected by 3-input sub-selector 302D_2. Then, one of the two signals selected by the two three-input sub-selectors 302D_1 and 302D_2 is selected by the two-input selector 502V.

  In the 6-input sub-selector 302G_2 having such a mechanism, the number of transistors is 2 × 3 × 2 + 4 = 16, and the number of control wirings is 2 × 3 + 2 = 8. There is an advantage that the number of transistors can be reduced as compared with the 6-input sub-selector 302G_1 of the first example.

  In FIG. 11B, the 9-input sub-selector 302H is configured by forming the 3-input sub-selector 302D into two layers. If 9 is prime factorized, it becomes “3 × 3”, so the arrangement of each stage to support 9 inputs is “3 inputs → 3 inputs”. In the first stage, three three-input sub-selectors 302D_1, 302D_2, and 302D_3 (each CN number = 3 × 2, each TR number = 3 × 2) are arranged, and three-input sub-selectors 302D_4 (CN number = 3) that receive their outputs. × 2, TR number = 3 × 2) is arranged in the second stage. The sub-select signals SUBSEL <10>, XSUBSEL <10>, SUBSEL <11>, XSUBSEL <11>, SUBSEL <12>, and XSUBSEL <12> are common to the first three-input sub-selectors 302D_1, 302D_2, and 302D_3. To supply. One of input 1, input 2 and input 3 is selected by 3-input sub-selector 302D_1, and one of input 4, input 5, and input 6 is selected by 3-input sub-selector 302D_2, and 3-input sub-selector 302D_3 is selected. One of input 7, input 8, and input 9 is selected. One of the three signals selected by the three three-input sub-selectors 302D_1, 302D_2, and 302D_3 is selected by the three-input sub-selector 302D_4.

  In the 9-input sub-selector 302H having such a structure, the number of transistors is 4 × 3 × 2 = 24, and the number of control wirings is 2 × 3 + 2 × 3 = 12. On the other hand, when the 9-input type sub-selector 302 is simply configured without adopting such a mechanism, the number of transistors is 9 × 2 = 18 and the number of control wirings is 9 × 2 = 18. The 9-input sub-selector 302H has an advantage that the number of control wires from the communication / timing control unit 20 can be reduced, although the number of transistors is increased.

  In FIG. 11C, the 12-input sub-selector 302I is configured by hierarchizing the 2-input selector 502V and the 3-input sub-selector 302D into three stages. If 12 is prime factorized, it becomes “2 × 2 × 3”. The arrangement of each stage is “2 inputs → 2 inputs → 3 inputs”, “2 inputs → 3 inputs → 2 inputs”, “3 inputs”. There are three possible ways: → 2 input → 2 input. The configuration of “2 inputs → 2 inputs → 3 inputs” is a configuration in which a 3-input sub-selector 302D is further arranged on the output of the aforementioned 4-input sub-selector 302F configured by “2 inputs → 2 inputs”. The configuration of “2 inputs → 3 inputs → 2 inputs” and “3 inputs → 2 inputs → 2 inputs” is the aforementioned 6-input sub-selector 302G configured by “2 inputs → 3 inputs” or “3 inputs → 2 inputs”. In this configuration, a two-input selector 502V is further arranged at the output of.

  The 12-input sub-selector 302I shown in FIG. 11C includes two 6-input sub-selectors 302G_2a and 302G_2b (each CN number = 8, each TR number = 16) and further a two-input selector 502V (CN number = 2, each TR Number = 4). In the 12-input sub-selector 302I having such a structure, the number of transistors is 16 × 2 + 4 = 36, and the number of control wirings is 8 + 2 = 10. On the other hand, when the 12-input type sub-selector 302 is simply configured without adopting such a mechanism, the number of transistors is 12 × 2 = 24 and the number of control wirings is 12 × 2 = 24. The 12-input sub-selector 302I has an advantage that the number of control wirings from the communication / timing control unit 20 can be reduced although the number of transistors is increased.

  If the number of stages is excessively large, the number of series transistors (particularly the number of pMOSs in series) in the sub-selector 302 increases, and it becomes difficult to transmit data to the horizontal signal line 18 at a high speed. Considering the number of transistors constituting the sub-selector 302 and the number of control wirings from the communication / timing control unit 20, about two to three stages are considered realistic.

<Horizontal Data Transfer System; Seventh Embodiment>
FIG. 12 is a diagram illustrating a seventh embodiment of a horizontal data transfer system of the solid-state imaging device 1. In the seventh embodiment, when the input number M of the sub-selector 302 is a prime number, an appropriate numerical value α is added and a prime number M_k (k is 1 or more) as “M + α = M_1 × M_2 × M_3 ×. This is a factorization into a form of multiplication of (positive integer), and the M_k input-1 output type sub-selector is hierarchized (multi-stage configuration). Except for adding an appropriate numerical value α to M, this is the same as in the sixth embodiment.

  For example, FIG. 12 shows a case where a 5-input sub-selector 302J having an input number M of 5 is configured to add α = 1 to form a 6-input type, and the configuration shown in FIG. This is an example in which the portion of = 1 is unused. In the 5-input sub-selector 302J_1 of the first example shown in FIG. 12 (1), the first-stage 2-input selector 502V_3 is removed based on the 6-input sub-selector 302G_1 of the first example shown in FIG. 11A (1). The input 4 is directly input to the third input terminal of the second-stage 3-input sub-selector 302D. In this example, the two-input selector 502V_3 is not used for α = 1. In the 5-input sub-selector 302J_2 of the second example shown in FIG. 12 (2), 3 of the 3-input sub-selector 302D_2 of the first stage is based on the 6-input sub-selector 302G_2 of the second example shown in FIG. 11A (2). The second input is unused. In this example, one input terminal of the three-input sub-selector 302D_2 is unused for α = 1. The 3-input sub-selector 302D_2 may be replaced with a 2-input selector 502V.

  In the 5-input sub-selector 302J_1, similarly to the 6-input sub-selector 302G_1, the number of transistors is 9 × 2 = 18, and the number of control wirings is 2 + 2 × 3 = 8. In the 5-input sub-selector 302J_2, similarly to the 6-input sub-selector 302G_2, the number of transistors is 8 × 2 = 16, and the number of control wirings is 2 × 3 + 2 = 8. If the 5-input type sub-selector 302 is simply configured without adopting such a mechanism, the number of transistors is 5 × 2 = 10 and the number of control wirings is 5 × 2 = 10. The 5-input sub-selectors 302J_1 and 302J_2 have an advantage that the number of control wirings from the communication / timing control unit 20 can be reduced.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  In the embodiment, the application example of the solid-state imaging device 1 to the horizontal transfer system has been described. However, the application range of the embodiment is not limited to the solid-state imaging device. Any semiconductor device having a mechanism for sequentially transferring data to the subsequent stage can be applied. Any semiconductor device may be used as long as a specific latch is selected from the one-dimensional or two-dimensionally arranged latches, the latch information is transferred to the transfer wiring, and the data of the transfer wiring is read to the outside. For example, the present invention can be applied to semiconductor memories such as SRAM (Static RAM) and DRAM (Dynamic RAM).

  Note that the solid-state imaging device may have a form formed as a single chip, or a module-like form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Also good. Further, the present invention can be applied not only to a solid-state imaging device but also to an imaging device and any other electronic device. In this case, the same effect as that of the solid-state imaging device can be obtained as the imaging device or other electronic devices. Here, the imaging device indicates, for example, a camera (or camera system) or a portable device having an imaging function. “Imaging” includes not only capturing an image during normal camera shooting, but also includes fingerprint detection in a broad sense.

1 is a basic configuration diagram of a CMOS type solid-state imaging device (CMOS image sensor) which is an embodiment of a solid-state imaging device according to the present invention. It is a figure which shows the basic composition of 1st Embodiment of the horizontal data transfer system of a solid-state imaging device. FIG. 3 is a diagram (part 1) illustrating a comparative example with respect to the first embodiment illustrated in FIG. 2; FIG. 3 is a second diagram illustrating a comparative example with respect to the first embodiment illustrated in FIG. 2. It is a figure which shows the detailed structural example (for 1 block: 6 columns) of the horizontal transfer type | system | group of 1st Embodiment. It is a figure which shows the detailed structural example (for four horizontal transfer channels) of the horizontal transfer type | system | group of 1st Embodiment. It is a figure which shows the structural example of the clocked inverter used for the latch of a data storage part. It is a figure which shows the example of data for demonstrating the basic operation | movement of the horizontal transfer type | system | group of 1st Embodiment. 5 is a timing chart for explaining the basic operation of the horizontal transfer system of the first embodiment in the data example of FIG. 4. It is a figure explaining the deformation | transformation operation | movement of the horizontal transfer system in the solid-state imaging device of 1st Embodiment using 6 input sub-selector. It is a figure which compares the effect of each horizontal transfer system of 1st Embodiment and Unexamined-Japanese-Patent No. 2006-148509. It is the chart which summarized the operation effect of the horizontal transfer system of a 1st embodiment by contrast with a comparative example. It is a figure explaining 2nd Embodiment of the horizontal data transfer system of a solid-state imaging device. It is a figure explaining the 3rd Embodiment of the horizontal data transfer type | system | group of a solid-state imaging device (using 2 input sub-selector). It is a figure explaining operation | movement of the horizontal transfer type | system | group of 3rd Embodiment. It is a figure explaining the 4th Embodiment of the horizontal data transfer type | system | group of a solid-state imaging device (using 3 input sub-selector). It is a figure explaining operation | movement of the horizontal transfer type | system | group of 4th Embodiment. It is a figure explaining the 5th Embodiment of the horizontal data transfer system of a solid-state imaging device (using 4 input sub-selector). It is a figure explaining operation | movement of the horizontal transfer type | system | group of 5th Embodiment. It is a figure explaining the 6th Embodiment of the horizontal data transfer system of a solid-state imaging device (using 4 input sub-selector). It is a figure explaining the 6th Embodiment of the horizontal data transfer type | system | group of a solid-state imaging device (using 6 input sub-selector). It is a figure (9 input sub-selector is used) explaining 6th Embodiment of the horizontal data transfer system of a solid-state imaging device. It is a figure explaining the 6th Embodiment of the horizontal data transfer system of a solid-state imaging device (using 12 input sub-selector). It is a figure (5 input sub-selector is used) explaining 7th Embodiment of the horizontal data transfer system of a solid-state imaging device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 10 ... Pixel array part, 12 ... Horizontal scanning part, 14 ... Vertical scanning part, 18 ... Horizontal signal line, 19 ... Vertical signal line, 20 ... Communication / timing control part (selection control part), 24 ... Read current control unit, 250 ... AD conversion unit, 252 ... comparison unit, 254 ... counter unit, 256 ... data storage unit, 257 ... latch (data holding circuit), 26 ... column AD conversion unit, 27 ... reference signal generation unit 270 ... DA converter, 28 ... output unit, 3 ... unit pixel, 301 ... selector unit (selection unit), 302 ... sub-selector (signal selection unit), 307 ... driver unit (drive unit), 308 ... horizontal transfer driver (Transfer Drive Unit) 331... Inverter, 332, 334... Transfer Transistor, 336 and 338... Select Transistor, 502 V.

Claims (9)

A data storage unit comprising a plurality of data holding circuits for holding digital data;
A selection unit comprising a plurality of signal selection units for selecting any of a plurality of data of the data holding circuit;
A selection control unit that controls each signal selection unit of the selection unit to select data;
A drive unit provided in each of the plurality of signal selection units with a transfer drive unit that drives a signal line for data transfer based on data selected by the signal selection unit;
A scanning unit that controls each transfer driving unit of the driving unit to transfer data to a subsequent circuit via the signal line;
With
The transfer driving unit is configured to select one of the plurality of signal selection units based on an instruction from a transfer transistor that drives the signal line based on data selected by the signal selection unit and the scanning unit. A selection transistor configured to transfer data selected by the signal selection unit to the subsequent circuit via the signal line when both the transfer transistor and the selection transistor are turned on; Semiconductor device. The semiconductor device according to claim 1, wherein the transfer transistor and the selection transistor are connected in series. An inverter that logically inverts the data selected by the signal selection unit;
The transfer driving unit includes the transfer transistor and the selection transistor for each of data selected by the signal selection unit and inverted data logically inverted by an inverter.
The semiconductor device according to claim 1, wherein the signal line is provided for each of data selected by the signal selection unit and inverted data logically inverted by an inverter. The semiconductor device according to claim 1, wherein each of the plurality of signal selection units is controlled by a control signal from a common control wiring connected to the selection control unit. A pixel array unit in which unit pixels are arranged in a matrix;
A vertical scanning unit that reads an analog pixel signal from each unit pixel of the pixel array unit;
An AD conversion unit provided for each column for converting an analog pixel signal read from each unit pixel of the pixel array unit into digital data;
A data storage unit provided at a subsequent stage of the AD conversion unit of each column and including a plurality of data holding circuits for holding digital data converted by the AD conversion unit;
A selection unit comprising a plurality of signal selection units for selecting any of a plurality of data of the data holding circuit;
A selection control unit that controls each signal selection unit of the selection unit to select data;
A drive unit provided in each of the plurality of signal selection units with a transfer drive unit that drives a signal line for data transfer based on data selected by the signal selection unit;
A horizontal scanning unit that controls each transfer driving unit of the driving unit to transfer data to a subsequent circuit via the signal line;
With
The transfer driving unit is configured to select one of the plurality of signal selection units based on an instruction from a transfer transistor that drives the signal line based on data selected by the signal selection unit and the scanning unit. A selection transistor configured to transfer data selected by the signal selection unit to the subsequent circuit via the signal line when both the transfer transistor and the selection transistor are turned on; Solid-state imaging device. An inverter that logically inverts the data selected by the signal selection unit;
The transfer driving unit includes the transfer transistor and the selection transistor for each of data selected by the signal selection unit and inverted data logically inverted by an inverter.
The solid-state imaging device according to claim 5, wherein the signal line is provided for each of data selected by the signal selection unit and inverted data logically inverted by an inverter. The selection control unit and the horizontal scanning unit can select a mode in which data transfer is performed by thinning out columns,
7. The solid-state imaging device according to claim 5, wherein each of the plurality of signal selection units has a reciprocal number of inputs corresponding to a thinning rate. The selection control unit and the horizontal scanning unit can select a plurality of thinning modes having different thinning levels,
7. The solid-state imaging device according to claim 5, wherein each of the plurality of signal selection units has an input number of the least common multiple of the reciprocal of each thinning rate. The signal lines for a plurality of channels are provided,
9. The solid-state imaging device according to claim 7, wherein each signal selection unit of the selection unit and each transfer driving unit of the driving unit are equally distributed to each horizontal signal line of the plurality of channels.

Images