JP2009296016A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device whose pixel pitch is reduced. <P>SOLUTION: In the solid-state imaging device in which a plurality of pixel cells are arranged in the line direction or the column direction, each pixel cell includes: a photoelectric conversion part; a transfer transistor; a floating diffusion part; a source follower transistor; a selection transistor; and a rest transistor. Here, a diffusion area which leads to a certain photoelectric conversion part and forms the reset transistor, the source follower transistor, and a switch transistor is formed in the vicinity of a photoelectric conversion part adjacent to the photoelectric conversion part, and in addition, the transfer transistor, the reset transistor, the source follower transistor and the selection transistor are arranged in parallel with one another. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a pixel layout of a solid-state image sensor.

  In recent years, the application of CMOS image sensors (solid-state imaging devices) to camera modules mounted on portable devices, mobile devices, etc. has progressed, but there is a strong demand for higher sensor resolution and smaller modules. . In order to reduce the size of the module, it is necessary to reduce the pixel pitch of the sensor.

  As an example of a pixel layout of a conventional solid-state imaging device, for example, literature (Sunetra K. Mendis et al., “CMOS Active Pixel Image Sensors for Highly Integrated Imaging Systems”, IEEE J. Solid-State Circuits, vol. 32, no. 2, pp. 187-197 (1977)) and JP-A-11-195576. In the general pixel layout described in JP-A-11-195576, various conditions are taken into consideration. In order to increase the area of the photoelectric conversion unit (photodiode), other components (transfer switch, floating diffusion unit, reset switch, selection switch, amplification unit, output unit, power supply, etc.) are densely placed around them. Be placed. In order to increase the aperture ratio of the pixel, the number of contacts is reduced so that the same diffusion region is obtained as much as possible. In order to shorten the connection line between the floating diffusion section and the amplification section, the output of a signal from one photodiode is performed via an amplifier and an output section provided on the side of the adjacent photodiode in the same row. The floating diffusion part of one photodiode and the amplifying part of the adjacent photodiode are connected using a polysilicon phase and an aluminum layer.

  Conventionally, an optimum layout technique when the pixel pitch is about 4 μm, for example, has not been disclosed. In the conventional pixel layout method, it is difficult to reduce the pixel pitch while ensuring the aperture ratio of the photodiode. In addition, with process shrinking, it becomes difficult to increase the gate width of the charge transfer gate that controls charge transfer from the photodiode to the floating diffusion portion due to layout restrictions, and noise due to incomplete transfer is likely to occur.

Japanese Patent Laid-Open No. 11-195576

Sunetra K. Mendis et al., "CMOS Active Pixel Image Sensors for Highly Integrated Imaging Systems", IEEE J. Solid-State Circuits, vol. 32, no. 2, pp. 187-197 (1977)

  An object of the present invention is to provide a solid-state imaging device with a reduced pixel pitch.

  A solid-state imaging device according to the present invention is a solid-state imaging device in which a plurality of pixel cells are arranged in a row direction or a column direction. Each pixel cell includes a photoelectric conversion unit that converts an optical signal into an electric signal, and a photoelectric conversion unit. A transfer transistor that holds the signal charge accumulated in the transistor, converts it into a voltage and outputs it, a floating diffusion part that holds the charge transferred by the transfer transistor and converts it into a voltage, and outputs it, and amplifies the signal potential of the floating diffusion part A source follower transistor that reads out to the outside, a selection transistor that selects a pixel that reads the signal potential to the outside, and a reset transistor that resets the photoelectric conversion unit. Here, a diffusion region connected to a certain photoelectric conversion unit and forming a reset transistor, a source follower transistor, and a switch transistor is formed in the vicinity of the photoelectric conversion unit adjacent to the photoelectric conversion unit, and the transfer transistor described above The reset transistor, the source follower transistor, and the selection transistor are arranged in parallel to each other.

  With the layout configuration of the solid-state imaging device, the pixel pitch can be reduced to about four times the gate pitch, the pixel size can be reduced, and a large aperture ratio can be secured.

Circuit diagram of pixel cell of solid-state imaging device Diagram of the layout structure of the solid-state imaging device of the first embodiment Diagram of the layout structure of the solid-state imaging device of the first embodiment Diagram of the layout structure of the solid-state imaging device of the first embodiment Diagram of the layout structure of the solid-state imaging device of the first embodiment Diagram for explaining various dimensions in layout structure Diagram of the layout structure of the solid-state imaging device of the second embodiment The figure for demonstrating operation | movement of the solid-state imaging device of Embodiment 3. FIG. The figure which shows operating potential about the reset transistor of a pixel, a transfer transistor, and a selection transistor Operation timing diagram The figure which shows the ion implantation process in Embodiment 4.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, the same reference symbols denote the same or equivalent.

  The solid-state imaging device includes a pixel array in which a plurality of pixel cells are arranged in a row direction or a column direction. FIG. 1 shows a circuit of one pixel in a solid-state imaging device (CMOS image sensor). Each pixel cell is transferred with a photoelectric conversion unit (photodiode) 1 that converts an optical signal into an electric signal, and a transfer transistor 2 that holds the signal charge accumulated in the photoelectric conversion unit 1 and converts it into a voltage for output. Floating diffusion unit 6 that retains the stored charge, converts it into voltage, and outputs it; source follower transistor 3 that amplifies the signal potential of floating diffusion unit 6 and reads it out; and selection transistor that selects the pixel from which the signal potential is read out 5 is provided.

  In the pixel shown in FIG. 1, the operation of a general pixel will be described. The pixel state consists of three states: reset, signal charge accumulation, and signal level readout.

  First, in the reset state, the transfer transistor 2 and the reset transistor 4 are simultaneously turned on, and the selection transistor 5 is off. By this operation, the potential of the photoelectric conversion unit 1 is reset to the reset potential supplied from the reset power source / source follower power source line 9.

  Next, the accumulation state will be described. In the accumulation state, the transfer transistor 2 is always kept off, and the potential of the photoelectric conversion unit 1 decreases according to the incident light due to electrons generated by photoelectric conversion of the light incident on the photoelectric conversion unit 1.

  Finally, the reading state will be described. Reading consists of four operations: resetting of the floating diffusion section 6, reset level reading, signal charge transfer, and signal level reading. In resetting the floating diffusion section 6, the reset transistor 4 is turned on while the transistor 2 is turned off, thereby resetting the potential of the floating diffusion section to the reset potential supplied from the reset power source / source follower power source 9. Next, in the read operation at the reset level, the selection transistor is turned on, the reset level of the floating diffusion unit 6 is read from the read line 11 through the source follower transistor 6, and the potential is applied to the reset level memory outside the pixel array. Hold. Next, the transfer transistor 2 is turned on with the reset transistor 4 turned off, and the signal charge held in the photoelectric conversion unit 1 is transferred to the floating diffusion unit 6 to perform signal charge transfer. Thereafter, the signal level is read from the readout line 11 through the source follower transistor 3 and held in the signal level memory outside the pixel array. Then, the difference between the signal level memory and the reset level memory is output to the outside as a pixel signal component.

Embodiment 1 FIG.
Hereinafter, a solid-state imaging device having a layout in which the pixel pitch is reduced to, for example, about 4 μm will be described. 2 to 5 show the layout structure of the solid-state imaging device according to the first embodiment for realizing the solid-state imaging circuit shown in FIG. In FIG. 2, each component in four adjacent pixels in a solid-state image sensor is shown. Each pixel forms a photoelectric conversion unit (photodiode) 1, a transfer transistor 2, a source follower transistor 3, a reset transistor 4, a selection transistor 5, and a floating diffusion unit 6. In the layout structure shown in FIG. 2, a poly gate, a diffusion region, and a contact are formed on the wafer. A diffusion region connected to one photoelectric conversion unit 1 and forming a reset transistor 4, a source follower transistor 3, and a selection (switch) transistor 5 is arranged in the vicinity of another photoelectric conversion unit 1 adjacent to one photoelectric conversion unit 1. Is done. The transfer transistor 2, the reset transistor 4, the source follower transistor 3, and the selection transistor 5 are all arranged in parallel with each other. That is, the poly gates of these transistors 2 to 5 are formed in a substantially rectangular shape, but their longitudinal directions are parallel. Further, in order to reduce the area of the floating diffusion portion 6, the diffusion region is arranged on the upper side in the figure of the photoelectric conversion portion 1 so as to be bent obliquely downward to the right from the lower portion of the transfer transistor 2, so that three types of transistors are provided. 3 to 5 are positioned below the adjacent photoelectric conversion unit 1.

  FIG. 3 shows a first metal layer and a contact formed on the polygate, the diffusion region and the contact shown in FIG. 2 via an insulating layer (not shown), and FIG. 4 further shows an insulating layer thereon. 5 shows a second metal layer and a first via hole formed through (not shown), and FIG. 5 further shows a third metal layer and a second via hole formed thereover via an insulating layer (not shown). . The first, second, and third metal layers form a transfer control line 7, a read control line 8, a reset control line 10, a reset power source / source follower power line 9 and a read line 11. As shown in the figure, by forming metal wiring, contacts, and via holes, each signal line can be taken out of the pixel array in which a plurality of pixel cells are arranged in the row direction or the column direction.

  In this layout configuration, as shown in FIG. 2, a diffusion region connected to a certain photoelectric conversion unit 1 and forming a reset transistor 4, a source follower transistor 3, and a selection transistor 5 is adjacent to the photoelectric conversion unit. It is formed in the vicinity of the part. Further, almost rectangular regions such as poly gates in the four types of transistors 2, 4, 3, and 5 are all arranged in parallel. With this layout configuration, the pixel pitch can be reduced to about four times the gate pitch, the pixel size can be reduced, and a large aperture ratio can be secured.

The reduction in pixel size in this layout will be described. As shown in FIG. 6, in this solid-state imaging device, the limit value of pixel pitch reduction is the minimum interval allowed between poly gates, S _min , and the gate forming the transistor. If the minimum length is L _min ,
4 * S _min + 4 * L _min
It becomes. On the other hand, in the conventional pixel layout configuration described in FIG. 11 of Japanese Patent Laid-Open No. 11-195576, the minimum interval allowed between the poly gates is S _min , the minimum gate length for forming the transistor is L _min , When the minimum value of the gate width is W _min and the minimum value of the gate extension length from the diffusion region is WEXT _min , the limit value of the pixel pitch reduction is
4 * S _min + 3 * L _min + W _min + 2 * WEXT _min
It becomes. When the difference between the layout configuration of the first embodiment and the conventional example is obtained, the limit value of pixel pitch reduction is
W _min + 2 * WEXT _min -L _min
It becomes. In general CMOS miniaturization process,
W _min + 2 * WEXT _min >> L _min
Therefore, pixel pitch reduction is realized by the above-described difference (W _min + 2 * W EXT _min ).

  Moreover, in the pixel layout shown in FIGS. 2-5, the opening shape of the photoelectric conversion part 1 becomes substantially square. Therefore, there is also an effect that the resolution in the horizontal direction is the same as that in the vertical direction. In addition, there is an effect that it is easy to form a microlens for improving sensitivity.

Embodiment 2. FIG.
In the floating diffusion portion, the signal charge is converted into a voltage. At the time of conversion, the smaller the parasitic capacitance of the floating diffusion, the larger the amount of voltage change with respect to the unit signal charge amount, and the higher the sensitivity of the sensor. For this reason, in general, the capacity of the floating diffusion portion is designed to be small. However, as the pixel pitch decreases, the gate width of the transistor decreases, the peripheral effect of the transistor increases, and the effective channel width tends to decrease. Therefore, even if the capacity of the floating diffusion portion can be reduced, noise due to transfer residue may occur if the charge transfer efficiency is low, and as a result, the S / N ratio of the sensor may be reduced.

  FIG. 7 shows a layout structure of the solid-state imaging device of the second embodiment. In the solid-state imaging device of the first embodiment, in order to reduce the area of the floating diffusion portion 6, the diffusion region is bent diagonally rightward from the lower portion of the transfer transistor 2 on the upper side in FIG. 2 of the photoelectric conversion portion 1. It was. In contrast, in the layout structure of the solid-state imaging device according to the second embodiment, the gate width of the transfer transistor 2 is set to be substantially the same (substantially the same) as the width of the diffusion region forming the photoelectric conversion unit 1. This ensures a large gate width of the transfer transistor 2. That is, a transfer gate to the floating diffusion unit 6 is provided without reducing the width of the diffusion region of the photoelectric conversion unit 1. Thereby, a layout in which the width of the transfer transistor is increased is possible, and complete charge transfer is facilitated.

  The transfer transistor 2 has a function of completely transferring the signal charge accumulated in the photoelectric conversion unit 1 to the floating diffusion unit 6 when turned on, and completely cutting the photoelectric conversion unit 1 and the floating diffusion unit 6 when turned off. Required. When the signal charge transfer is incomplete, the residual charge becomes a noise factor, which causes a decrease in the S / N ratio. In a transfer transistor for realizing complete charge transfer, the device structure is complicated and process difficulty is high as compared with a normal transistor. However, in the second embodiment, as described above, the gate width of the transfer transistor 2 is increased. This alleviates the edge effect, widens the frontage for charge transfer, and makes it easy to realize complete charge transfer that is particularly difficult to realize when the process is reduced.

Embodiment 3 FIG.
FIG. 8 is a layout (FIG. 2) of the first embodiment that realizes the circuit configuration of the solid-state imaging device shown in FIG. 1, and shows a cross section when cut in the AA ′ direction. At the time of imaging, in the reset operation of the photoelectric conversion unit (photodiode) 1, the transfer transistor 2 and the reset transistor 4 are turned on, the charge of the photoelectric conversion unit 1 is drawn out to the floating diffusion unit 6, and the photoelectric conversion unit 1 is removed. Complete depletion (no charge is present). Thereafter, the transfer transistor 2 and the reset transistor 4 are turned off, the photoelectric conversion unit 1 is floated, and incident light is photoelectrically converted to accumulate charges. After a certain accumulation time has elapsed, the charge accumulated in the photoelectric conversion unit 1 is transferred to the floating diffusion unit 6 and the potential change is read to obtain an image signal.

  When the amount of incident light is strong and the photoelectric conversion unit 1 is saturated during the accumulation period in which charges are accumulated in the photoelectric conversion unit, the accumulated charge passes over the photoelectric conversion unit 1 and overflows to the photoelectric conversion unit 1 of the adjacent pixel (FIG. 8). In the pixel layout of the first embodiment, the floating diffusion part 6 is always arranged on both sides of the photoelectric conversion part 1. Since the photoelectric conversion unit 1 and the floating diffusion unit 6 are adjacent to each other, the floating diffusion unit 6 can function as a lateral overflow drain by absorbing the saturated surplus charge with the floating diffusion unit 6. Become. Since the electric charge overflowing the photoelectric conversion unit 1 is absorbed by the floating diffusion unit 6, there is an effect that image quality deterioration due to only an image called blooming hardly occurs.

  However, since the capacity of the floating diffusion section 6 is also finite, the floating diffusion section 6 itself overflows when the amount of incident light is sufficiently strong. Therefore, after the photoelectric conversion unit 1 is reset, the reset transistor 4 is turned off, and then the signal charge is accumulated in the photoelectric conversion unit 1. In the period in which signal charges are accumulated in the photoelectric conversion unit 1, the reset transistor 4 in the off state is turned on again, and the reset power supply of the floating diffusion unit 6 is maintained at a constant voltage, so that excess charge can be swept out to the power supply side. . For this reason, regardless of the amount of incident light, it can function as a horizontal overflow drain that releases charges overflowing from the photoelectric conversion unit 1. That is, during the period in which signal charges are accumulated in the photoelectric conversion unit 1, the floating transistor 6 operates as an overflow drain that releases the charges overflowing from the photoelectric conversion unit by keeping the floating diffusion unit 6 at a constant voltage by turning on the reset transistor 4. Let me. The effect of the overflow drain can be improved by fixing the floating diffusion portion 6 to a constant potential.

  FIG. 9 shows the operation potential of the pixel for the reset transistor 4, the transfer transistor 2, and the selection transistor 5. As shown in FIG. 9, the floating diffusion unit 6 is always fixed to a reset power source, and when surplus charge is generated from the photoelectric conversion unit 1, the charge is swept out to the power source side. FIG. 10 is a timing chart thereof.

Embodiment 4 FIG.
In the solid-state imaging device, charge transfer is performed in which signal charges photoelectrically converted by the photoelectric conversion unit and accumulated during the accumulation period are transferred to the floating diffusion unit through the transfer transistor. In order to realize complete charge transfer, a transfer channel is formed between the transfer transistor and the photoelectric conversion unit. In order to form this transfer channel, it has been proposed that an ion implantation process for forming the photoelectric conversion unit 1 is performed by implanting implanted ions at a certain angle. In this method, ion implantation is performed from a direction perpendicular to the gate of the transfer transistor. At the time of ion implantation, the implantation region is limited by a photoresist. However, since ion implantation is performed at a constant angle, a region where ions are not implanted is generated depending on the thickness of the photoresist.

  On the other hand, in the method of manufacturing the image pickup element of the fourth embodiment, an ion implantation method having a constant implantation angle for impurities is used, but the implanted ions implanted into the photoelectric conversion unit 1 at a certain angle are shielded. A structure such as a gate wiring is not formed around the photoelectric conversion unit 1. That is, in the method for manufacturing a solid-state imaging device in this embodiment, in order to form the photoelectric conversion unit 1, ions are implanted into the region where the photoelectric conversion unit is to be formed by ion implantation with a certain implantation angle. When implanting, a structure such as a gate wiring that shields implanted ions implanted into the photoelectric conversion unit 1 at a certain angle is not formed around the photoelectric conversion unit 1. With this layout configuration, a large opening area of the photoelectric conversion unit 1 is secured.

  For example, in the manufacturing process shown in the upper side of FIG. 11, a region for the photoelectric conversion portion (photodiode) 1 and a region for the floating diffusion portion 6 are provided on the semiconductor wafer 20, and then an insulating layer is formed thereon. Form. Next, an electrically conductive layer is formed, a photoresist is formed to create a mask, and the gate of the transfer transistor 2 is formed between the region for the photoelectric conversion unit 1 and the region for the floating diffusion unit 6. Next, in order to perform ion implantation in the region of the photoelectric conversion unit 1, a photoresist 100 is provided in a region other than the region for the photoelectric conversion unit 1, and then impurity ions are fixed in the region for the photoelectric conversion unit 1. Inject at an angle. In the layout structure shown in the upper part of FIG. 11, no structures such as gate wirings are provided around the photoelectric conversion unit 1 in the ion implantation direction. For this reason, when the impurity is formed by an ion implantation method having a fixed implantation angle, only the photoresist 100 shields the ion implantation into the region of the photoelectric conversion unit 1. In the drawing, a portion described as “implantation block” is a portion that is blocked (blocked) by the photoresist 100 and ions cannot be implanted. According to this layout configuration, a large opening area of the photoelectric conversion unit 1 can be secured, which is effective for improving the sensitivity and expanding the saturation charge amount.

  On the other hand, in the layout configuration of the comparative example shown in the lower part of FIG. 11, when impurity ions are implanted at a constant implantation angle, there are obstacles other than the mask material in the ion implantation direction. Blocked by the photoresist. For this reason, the implanted ions are not implanted into a part of the region for the photoelectric conversion unit 1, and the effective area of the photoelectric conversion unit 1 is reduced. This is a factor that causes a decrease in sensitivity. On the other hand, in the layout structure of the fourth embodiment, a structure such as a gate wiring that shields implanted ions implanted into the photoelectric conversion unit 1 at a certain angle is not formed around the photoelectric conversion unit 1. The effective area of the part 1 can be widened.

  DESCRIPTION OF SYMBOLS 1 Photoelectric conversion part, 2 Transfer transistor, 3 Source follower transistor, 4 Reset transistor, 5 Selection transistor, 6 Floating diffusion part, 7 Transfer control line, 8 Read-out control line, 9 Power supply line, 10 Reset control line, 11 Read-out line

Claims (4)

A solid-state imaging device in which a plurality of pixel cells are arranged in a row direction or a column direction,
Each pixel cell holds a photoelectric conversion unit that converts an optical signal into an electrical signal, a transfer transistor that holds the signal charge accumulated in the photoelectric conversion unit, converts it into a voltage, and outputs it, and holds the charge transferred by the transfer transistor Resets the floating diffusion section that converts the voltage into a voltage, the source follower transistor that amplifies the signal potential of the floating diffusion section and reads it out, the selection transistor that selects the pixel from which the signal potential is read out, and the photoelectric conversion section And a reset transistor
A diffusion region connected to a certain photoelectric conversion unit and forming a reset transistor, a source follower transistor, and a switch transistor is formed in the vicinity of the photoelectric conversion unit adjacent to the photoelectric conversion unit,
A solid-state imaging device, wherein the transfer transistor, the reset transistor, the source follower transistor, and the selection transistor are arranged in parallel to each other. The solid-state imaging device according to claim 1,
A solid-state imaging device, wherein a floating diffusion part is disposed between one photoelectric conversion part and a photoelectric conversion part adjacent thereto. The solid-state imaging device according to claim 1,
A solid-state imaging device, wherein a gate width of a transfer transistor is substantially the same as a width of a diffusion region forming a photoelectric conversion portion. In the solid-state image sensor according to any one of claims 1 to 3,
Operation of the solid-state imaging device characterized by fixing the reset transistor to the reset power supply of the floating diffusion unit after turning off the reset transistor after resetting the photoelectric conversion unit and then turning it on again during the period of charge accumulation in the photoelectric conversion unit Method.

Images