JP2009278461A - Switch semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve distortion characteristics and to reduce an insertion loss of a switch element in accordance with a selected single passing route, without enlarging a chip size, in a simple configuration. <P>SOLUTION: Between a first high frequency input/output terminal 101 and a ground potential, a first DC signal changeover switch element 22 and a first bias resistor 24 are connected in series and provided and between the first high frequency input/output terminal 101 and a control circuit 21, on the other hand, a second DC signal changeover switch element 23 and a second bias resistor 25 are connected in series and provided. The conduction/non-conduction of the first and second DC signal changeover switch elements 22 and 23 is controlled by the control circuit 21 while being linked to operations of first to third switch elements 11 to 13, and a bias voltage of the first to third switch elements 11 to 13 is made variable as needed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a switch semiconductor integrated circuit for switching a high-frequency signal path in a mobile communication device such as a cellular phone or a high-frequency device, and in particular, to improve distortion characteristics in a switch semiconductor integrated circuit for multiband / multimode. It relates to what was planned.

  2. Description of the Related Art Conventionally, in devices such as cellular phones and mobile radio communications that handle high-frequency signals, switch semiconductor integrated circuits using MES FETs, HEMTs, and the like, which are field-effect transistors made of GaAs compound semiconductors, are used for switching high-frequency signal paths. in use. As such a switch semiconductor integrated circuit, for example, there is one disclosed in Patent Document 1 or the like. Such a switch semiconductor integrated circuit has electrical characteristics such as insertion loss, isolation, handling power, and distortion characteristics. Required.

Conventionally, as this type of circuit, for example, a circuit having the configuration shown in FIG. 4 is publicly known.
Hereinafter, the conventional circuit will be described with reference to FIG. 1. The switch semiconductor integrated circuit includes a first electric field and a second electric field connected in series between the first and second high-frequency input / output terminals 201 and 202. The first switch element 211 having the effect transistors 203 and 204 as main components is provided, while the field effect transistors 210 and 211 connected in series between the second high-frequency input / output terminal 202 and the ground are main components. A second switch element 212 as an element is provided.

  In such a configuration, the first high-frequency input / output terminal 201 and the second high-frequency input / output terminal 202 are turned on (hereinafter, this state is referred to as “switch semiconductor integrated circuit is turned on”). A control voltage higher than the pinch-off voltage of the first and second field effect transistors 203 and 204 is applied to the control terminal 205 of the first and second field effect transistors 203 and 204, so that the impedance between the drain and source of the first and second field effect transistors 203 and 204 is low. And On the other hand, a control voltage lower than the pinch-off voltage of the third and fourth field effect transistors 210 and 211 is applied to the second control terminal 215, and the drains of the third and fourth field effect transistors 210 and 211 are applied.・ High impedance between sources.

  In order to turn off the first high-frequency input / output terminal 201 and the second high-frequency input / output terminal 202 (hereinafter, this state is referred to as “switch semiconductor integrated circuit is turned off”), Conversely, a control voltage lower than the pinch-off voltage of the first and second field effect transistors 203 and 204 is applied to the first control terminal 205, and the drains of the first and second field effect transistors 203 and 204 are applied.・ High impedance between sources. On the other hand, a control voltage higher than the pinch-off voltage of the third and fourth field effect transistors 210 and 211 is applied to the second control terminal 215, and the drains of the third and fourth field effect transistors 210 and 211 are applied.・ Low impedance between sources.

  Here, when the switch semiconductor integrated circuit is turned off, a control voltage higher than the pinch-off voltage of the third and fourth field effect transistors 210 and 211 is applied to the second control terminal 215, and By turning on the third and fourth field effect transistors 210 and 211, the first and second field effect transistors 202 and 204 are in an off state, even though the first and second field effect transistors 202 and 204 are in an off state. The high frequency input signal leaked without being blocked by 203 and 204 is grounded in a high frequency manner to ensure high isolation between the first and second high frequency input / output terminals 201 and 202.

  By the way, the maximum power that can be handled in such a switch semiconductor integrated circuit can be generally expressed by Equation 1 below.

Pmax = 2 {n (Vp−VCTL)} ² / Zo Formula 1

  In Equation 1, n is the number (number of stages) of field effect transistors connected in series, Vp is the pinch-off voltage of the field effect transistor, VCTL is the bias voltage applied to the gate of the field effect transistor in the off state, and Zo is the switch This is a characteristic impedance of a system in which a semiconductor integrated circuit is used.

  According to this equation, in order to increase the power (handling power) that can be handled in the switch semiconductor integrated circuit, the number of stages of field effect transistors connected in series is increased, or a field effect transistor having a shallow Vp is used, or bias is applied. It can be understood that there is an option of increasing the voltage, and any of these may be selected, or any combination thereof may be performed.

  However, since Vp of the field effect transistor is determined by a process used in the manufacturing process, it is practically difficult to change it arbitrarily. Also, as for the operating voltage, if it is assumed to be used in a mobile phone terminal, it is battery-powered, so it is often necessary to secure about 3V, and it is realistic to select a larger voltage than that. Is impossible.

Therefore, it is common to deal with the improvement in handling power characteristics of the switch semiconductor integrated circuit by increasing the number n of field effect transistors connected in series, but increasing the number of stages increases the chip size and cost. Therefore, in recent years, a method of increasing the bias voltage by incorporating a booster circuit is also being used (see, for example, Patent Document 2).
JP 2002-164772 A (page 4-5, FIG. 1 and FIG. 2) Japanese Patent Laying-Open No. 2005-354279 (page 4-7, FIGS. 1 to 3)

  However, with the recent increase in the number of bands and the number of mobile phones and mobile radio devices, there is an increasing demand for further performance improvement, and the above-described countermeasures are insufficient. For example, a switch semiconductor integrated circuit used for a multimode terminal of GSM and WCDMA is exemplified by harmonic characteristics when a high frequency signal of about 32 dBm to 35 dBm is input for GSM applications, and a high frequency signal of about 20 dBm for WCDMA applications. IMD characteristics at the time of input are important, and further improvement of these characteristics is desired.

  The present invention has been made in view of the above circumstances, and aims to improve the distortion characteristics and reduce the insertion loss of the switch element according to the selected signal passing path with a simple configuration and without increasing the chip size. It is an object of the present invention to provide a switch semiconductor integrated circuit.

In order to achieve the above object of the present invention, a switch semiconductor integrated circuit according to the present invention comprises:
A plurality of individual high-frequency input / output terminals, at least one common high-frequency input / output terminal, and the plurality of individual high-frequency input / output terminals and the common input / output terminal are respectively arranged to control conduction / non-conduction from the outside. A plurality of high-frequency switching elements configured to be possible, and a control circuit that controls the operation of the high-frequency switching elements, by controlling the operation of the high-frequency switching elements by the control circuit, A signal passing path can be formed between one desired individual high frequency input / output terminal of the plurality of individual high frequency input / output terminals and one desired common high frequency input / output terminal among the common high frequency input / output terminals. A switch semiconductor integrated circuit comprising:
A first DC signal switching switch element and a first resistor are provided in series between the common high frequency input / output terminal and the ground potential, while the common high frequency input / output terminal and the control circuit A second DC signal switching switch element and a second resistor are connected in series between a voltage source equal to the voltage applied to the output switch element, and the first and second DC signals are provided. The switch element for signal switching is configured such that conduction / non-conduction can be interlocked with conduction / non-conduction of the plurality of high-frequency switching switch elements.
In the above configuration, the control circuit causes the first DC signal switching switch element to be non-conductive when the signal passing path in which the high-frequency power to be passed is relatively large with respect to the other signal passing paths is turned on. And the second DC signal switching switch element is turned on,
When the signal passing path having a relatively small high-frequency power to be passed is made conductive with respect to the other signal passing paths, the first DC signal switching switch element is turned on, and the second DC signal switching is performed. What is comprised so that the switch element for operation may be made into a non-conduction state is suitable.
Further, in the above configuration, a shunt switch element that grounds the individual high frequency input / output terminal in high frequency by external control is connected to each of the plurality of individual high frequency input / output terminals. While making the control signal of the shunt switch element connected to the individual high frequency input / output terminal relatively large with respect to the passage path common with the control signal of the first DC signal changeover switch element,
The control signal of the shunt switch element connected to the individual high frequency input / output terminal whose high frequency power to be passed is relatively small with respect to other signal passing paths is made common with the control signal of the second DC signal changeover switch element. It is also suitable to be configured.
Further, in the above configuration, the gate width of the field-effect transistor constituting the high-frequency switching switch element connected to the individual high-frequency input / output terminal in which the high-frequency power allowed to pass is relatively large with respect to other signal passage paths is The high frequency power to be squeezed is set to be larger than the gate width of the field effect transistor constituting the high frequency switching device connected to the individual high frequency input / output terminal which is relatively small with respect to other signal passing paths. Is also suitable.

According to the present invention, the bias voltage of the switch element for high frequency switching provided in the signal passing path can be changed according to the selected signal passing path. As compared with other signal passing paths, the distortion characteristic can be improved.
In addition, by configuring the operation of the DC signal switching switch element used for switching the bias voltage to be linked to the operation of the high frequency switching switch element, it is possible to simplify the circuit configuration by sharing the control signal. Therefore, there is an effect that an increase in chip size can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a first configuration example of the switch semiconductor integrated circuit according to the embodiment of the present invention will be described with reference to FIG.
The switch semiconductor integrated circuit according to the first configuration example includes an on / between a first high-frequency input / output terminal 101 serving as a common terminal and second to fourth high-frequency input / output terminals 102 to 104 serving as individual terminals. An SP3T (single-pole, three-throw) switch for switching an off (conductive / non-conductive) state is configured. The first to third switch elements 11 to 13 and the first and second DC signal switching switch elements 22 are configured. , 23 and the control circuit 21 are the main components.

The first to third switch elements 11 to 13 as switching elements for high-frequency switching use depletion type field effect transistors (hereinafter referred to as “FETs”) and basically have the same configuration. It will be.
That is, each of the first to third switch elements 11 to 13 includes two FETs connected in series. The first switch element 11 includes FETs 31a and 32a, and the second switch element 12 includes The FETs 31b and 32b and the third switch element 13 are configured such that the FETs 31c and 32c are connected in series so that the drain and the source are in series.

One end of the first switch element 11 is connected to the second high-frequency input / output terminal 102 via the second DC cut capacitor 42, and one end of the second switch element 12 is connected to the third DC cut capacitor 43. To the third high-frequency input / output terminal 103, and one end of the third switch element 14 is connected to the fourth high-frequency input / output terminal 104 via the fourth DC cut capacitor 44.
On the other hand, the other ends of the first to third switch elements 11 to 13 are both connected to the first high-frequency input / output terminal 101 via the first DC cut capacitor 41.

Further, the gates of the FETs 31a and 32a constituting the first switch element 11 are connected to each other, and a control voltage is applied from the control circuit 21 as will be described later.
Similarly, the gates of the FETs 31b and 32b constituting the second switch element 12 are also connected to each other, and a control voltage is applied from the control circuit 21 as will be described later. Further, the gates of the FETs 31 c and 32 c constituting the third switch element 13 are also connected to each other, and a control voltage is applied from the control circuit 21 as will be described later.

  On the other hand, one end of each of the first bias resistor 24 and the second bias resistor 25 is connected to a connection point between the first to third switch elements 11 to 13 and the first DC cut capacitor 41. The other end of the first bias resistor 24 can be connected to the ground via the first DC signal changeover switch element 22, while the other end of the second bias resistor 25 is connected to the second DC resistor. It is connected to the control circuit 21 via the signal changeover switch element 23, and a voltage output from the control circuit 21 is applied as will be described later.

  Each of the first and second DC signal changeover switch elements 22 and 23 has a single-pole single-throw switch configuration, and the opening and closing thereof is configured to be controllable by the control circuit 21. For example, a switch semiconductor element is used.

  The control circuit 21 has first and second control circuit input terminals 62 and 63, decodes an external control signal input from the outside, and the first to third switch elements 11 according to the decoding result. ... 13 is turned on, and one of the first and second DC signal changeover switch elements 22 and 23 is turned on, and the control voltage necessary to turn off the other is output. (The details will be described later).

Next, the operation in this configuration will be described.
First, an antenna (not shown) is connected to the first high-frequency input / output terminal 101, and the second high-frequency input / output terminal 102 is connected to a transmitter (not shown) of a 900 MHz GSM (Global System Mobile Communicatios). The terminal, the third high-frequency input / output terminal 103 are a transmission terminal to which a transmitter (not shown) of 2 GHz band WCDMA (Wideband Code Division Multiple Access) is connected, and the fourth high-frequency input / output terminal 104 is a 900-MHz band. Assume a receiving terminal to which a GSM receiver (not shown) is connected.

Under this assumption, the operation when the first high-frequency input / output terminal 101 and the second high-frequency input / output terminal 102 are used as signal passing paths will be described.
First, the switch semiconductor integrated circuit in the first configuration example has the same basic operation as the conventional circuit except for the operations of the first and second DC signal changeover switch elements 22 and 23.
That is, the control circuit 21 receives a predetermined external control signal to make the first high-frequency input / output terminal 101 and the second high-frequency input / output terminal 102 a signal passage path, and the first and second control circuit input terminals 62, When input to 63, the control circuit 21 provides a control voltage higher than a predetermined control voltage suitable for turning on the two FETs 31a and 32a constituting the first switch element 11, that is, a pinch-off voltage of the FETs 31a and 32a. The voltage is output and the FETs 31a and 32a are turned on.

On the other hand, for the second and third switch elements 12 and 13, the control circuit 21 supplies a predetermined control voltage, that is, an FET 31b to turn off both the second and third switch elements 12 and 13. , 32b, 31c, and 32c, a control voltage lower than the pinch-off voltage is applied to each gate, and the second and third switch elements 12 and 13 are turned off.
As a result, the first high-frequency input / output terminal 101 and the second high-frequency input / output terminal 102 are in a conductive state to form a signal passing path, and a first signal from a transmitter (not shown) connected to the second high-frequency input / output terminal 102 A high frequency signal can be transmitted to an antenna (not shown) connected to the high frequency input / output terminal 101.

Further, in such an operating state, the control circuit 21 outputs a control signal for making the first DC signal changeover switch element 22 non-conductive to the first DC signal changeover switch element 22, while A control signal for turning on the second DC signal changeover switch element 23 is outputted to the second DC signal changeover switch element 23.
As a result, a voltage output from the control circuit 21 via the second bias resistor 25 is connected to the connection point between the first to third switch elements 11 to 13 and the first DC cut capacitor 41. Will be applied.
That is, the control circuit 21 includes a voltage source (not shown) that outputs a voltage equal to the control voltage applied to the gates of the first to third switch elements 11 to 13. A voltage (not shown) is output to the other end of the second DC signal changeover switch element 23 connected to the control circuit 21, and the first to third switch elements 11 to 13 and the first DC cut capacitor 41 is applied to the mutual connection point with 41.

Therefore, the potential difference between the gates and drains of the FETs 31a and 32a constituting the first switch element 11 and between the gate and the source is almost 0 V, so that the FETs 31a and 32a are surely turned on.
On the other hand, in the second and third switch elements 12 and 13, the gate-drain voltage and the gate-source voltage of the FETs 31 b, 32 b, 31 c, 32 c are all the same as the power supply voltage applied to the control circuit 21. As a result, the FETs 31b, 32b, 31c, and 32c are kept off. The voltage between the gate and the drain and between the gate and the source is VCTL in the equation 1 shown in the background art section.

Next, the first to fourth high-frequency input / output terminals 101 to 104 are connected to the outside in the same manner as described above, and the first high-frequency input / output terminal 101 and the third high-frequency input / output terminal 103 are connected. The operation when the signal passing path is used will be described.
A predetermined external control signal is sent to the control circuit 21 so that the first high-frequency input / output terminal 101 and the third high-frequency input / output terminal 102 are used as signal passing paths, and the first and second control circuit input terminals 62 and 63 are used. Is input from the control circuit 21 to a predetermined control voltage suitable for turning on the two FETs 31b and 32b constituting the second switch element 12, that is, a control voltage higher than the pinch-off voltage of the FETs 31b and 32b. Is output to turn on the FETs 31b and 32b.

On the other hand, for the first and third switch elements 11 and 13, the control circuit 21 supplies a predetermined control voltage, that is, an FET 31a to turn off the second and third switch elements 12 and 13 together. , 32a, 31c, and 32c, a control voltage lower than the pinch-off voltage is applied to each gate, and the first and third switch elements 11 and 13 are turned off.
As a result, the first high-frequency input / output terminal 101 and the third high-frequency input / output terminal 103 are in a conductive state to form a signal passing path, and a first signal from a transmitter (not shown) connected to the third high-frequency input / output terminal 103 A high frequency signal can be transmitted to an antenna (not shown) connected to the high frequency input / output terminal 101.

Further, in such an operating state, the control circuit 21 gives a control signal for making the first DC signal changeover switch element 22 conductive, and a control signal for making the second DC signal changeover switch element 23 nonconductive. Are output, and the first DC signal changeover switch element 22 is turned on, while the second DC signal changeover switch element 23 is turned off.
As a result, the connection point between the first to third switch elements 11 to 13 and the first DC cut capacitor 41 is connected to the ground via the first bias resistor 24.

  Therefore, the gate-drain voltage and the gate-source voltage of the FETs 31b and 32b constituting the second switch element 11 become the gate forward voltage (Vf) of the FET 31b or FET 32b, while the first, third The gate-drain voltages and the gate-source voltages of the FETs 31a, 32a, 31c, 32c constituting the switch elements 11, 13 are applied to the gates of the FETs 31a, 32a, 31c, 32c by the control circuit 21. The voltage is lower than the control voltage by the gate forward voltage (Vf), and this voltage is VCTL in the equation 1 shown in the background art section.

  Here, when the first high-frequency input / output terminal 101 and the second high-frequency input / output terminal 102 described above are in a conductive state, the VCTL of the FET that is in the off state, and the first high-frequency input / output terminal 101 described above. And the third high-frequency input / output terminal 103 are in a conductive state, the mutual relationship between the VCTL of the FET that is in the off state can be expressed as in Equation 2 below.

  VCTL (1-2)> VCTL (1-3) Expression 2

  Here, for convenience, VCTL (1-2) is the VCTL of the FET that is off when the first high-frequency input / output terminal 101 and the second high-frequency input / output terminal 102 are in a conductive state, and VCTL (1-2) 1-3) is the VCTL of the FET in the off state when the first high frequency input / output terminal 101 and the third high frequency input / output terminal 103 are in a conductive state.

FIG. 3 is a characteristic diagram showing the relationship between the VCTL in the embodiment of the present invention and the maximum power Pmax that can be handled by the circuit, and this figure will be described below.
First, in FIG. 3, the horizontal axis indicates VCTL (V), and the vertical axis indicates Pmax (dBm). In the figure, the characteristic curve represented by a solid line (denoted as “mode 1” in the figure) is the first high-frequency input / output terminal 101 and the second high-frequency input / output terminal 102 in the embodiment of the present invention. A characteristic curve showing a change in Pmax with respect to a change in VCTL when the gap is in a conductive state, and a characteristic curve represented by a two-dot chain line (denoted as “mode 2” in the figure) is an embodiment of the present invention. It is a characteristic curve which shows the change of Pmax with respect to the change of VCTL when the 1st high frequency input / output terminal 101 and the 3rd high frequency input / output terminal 103 are conduction | electrical_connection states.

According to the figure, the value of Pmax with respect to VCTL is different between mode 1 and mode 2, and the value of Pmax in mode 1 is higher.
Generally, VCTL used in a semiconductor switch is constant unless a complicated circuit is provided. Therefore, when mode 1 and mode 2 are compared in terms of a certain VCTL value, Pmax may be set higher in mode 1. This means that the distortion characteristics generated from the switch semiconductor integrated circuit can be improved. That is, the distortion characteristics can be reduced in the case of mode 1 than in mode 2.

In general, the input power required for an antenna switch for multiband / multimode use is 35 dBm in the GSM transmission mode and 26 dBm in the WCDMA transmission mode. Increasing the Pmax in the GSM transmission mode can improve the distortion characteristics.
On the other hand, in mode 2, the VCTL is low, but since the transmission power is relatively low, the characteristic deterioration that causes a particular problem does not occur.

Next, regarding the ON characteristic of the switch element, when mode 2 is selected, the bias of the FETs 31b and 32b constituting the second switch element 12 is Vgs> 0V as described above. Compared with the case where 1 is selected, there is an advantage that the insertion loss can be reduced.
Here, as a method for improving the insertion loss of the switch element when mode 1 is selected, for example, there is a method of widening the gate width of the FET.
In the circuit configuration shown in FIG. 1, the gate width of each of the FETs 31a and 32a constituting the first switch element 11 used when selecting the mode 1 is set, and the second and third switch elements 12 and 13 are set. You may set widely compared with FET31b, 32b, 31c, and 32c to comprise. As a result, the insertion loss when mode 1 is selected is reduced.

Next, a second configuration example will be described with reference to FIG. Detailed descriptions of the same components as those shown in FIG. 1 will be omitted, and different points will be mainly described below.
The switch semiconductor integrated circuit in the second configuration example is the same as the configuration example shown in FIG. 1, but is further shunted between the terminals of the second to fourth high-frequency input / output terminals 102 to 104 and the ground. The switch element is provided.

  More specifically, first, between the second high frequency input / output terminal 102 and the ground, the first shunt switch element 14 and the fifth DC cut are provided from the second high frequency input / output terminal 102 side. Capacitors 45 are sequentially connected in series, and the second shunt switch element 15 and the sixth DC cut are provided between the third high-frequency input / output terminal 103 and the ground from the third high-frequency input / output terminal 103 side. Capacitors 46 are sequentially connected in series, and further, between the fourth high-frequency input / output terminal 104 and the ground, the third shunt switch element 16 and the sixth A DC cut capacitor 47 is provided in series.

Each of the first to third shunt switch elements 14 to 16 uses a depletion type FET, and has basically the same configuration as the first to third switch elements 11 to 13. .
In the embodiment of the present invention, the first shunt switch element 14 is connected in series by FETs 33a and 34a, and the second shunt switch element 15 is connected in series by FETs 33b and 34b. Are configured by connecting the FETs 33c and 34c in series.

The control circuit 21 applies the same control voltage as the control voltage applied to the first DC signal changeover switch element 22 to the gates of the FETs 33 a and 34 a constituting the first shunt switch element 14. It has become.
Further, the control circuit 21 applies the same control voltage as the control voltage applied to the second DC signal changeover switch element 23 to the gates of 33 b and 34 b constituting the second shunt switch element 15. It has become.
Further, a control voltage is applied from the control circuit 21 to the gates of the FETs 33 c and 34 c constituting the third shunt switch element 16, separately from the first and second shunt switch elements 14 and 15. ing.

In this configuration, the operations of the first to third switch elements 11 to 13 are basically the same as the operations described in the first configuration example shown in FIG. The first to third shunt switch elements according to the selection of the signal passing path between the first high-frequency input / output terminal 101 and the second to third high-frequency input / output terminals 102 to 104 are omitted. Description will be made centering on the operations 14-16.
First, when the first high frequency input / output terminal 101 and the second high frequency input / output terminal 102 are selected as a signal passing path, the first DC signal changeover switch element 22 includes the first DC signal changeover switch element 22 as described above. The control voltage for turning off the first DC signal changeover switch element 22 is applied to the second DC signal changeover switch element 23, and the control voltage for turning on the second DC signal changeover switch element 23 is applied thereto. The first shunt switch element 14 is turned off like the first DC signal changeover switch element 22, while the second shunt switch element 15 is turned on like the second DC signal changeover switch element 23. It will be. Further, a control voltage for turning on the third shunt switch element 16 is applied from the control circuit 21 to the third shunt switch element 16.

  That is, the first shunt switch element 14 connected to the first switch element 11 forming the signal passing path is turned off, while the remaining second and third shunt switch elements 15 and 16 are turned on. Thus, signal leakage between the third and fourth high-frequency input / output terminals 103 and 104 and the first high-frequency input / output terminal 101 does not occur.

Next, when the first high-frequency input / output terminal 101 and the third high-frequency input / output terminal 103 are selected as a signal passing path, the first DC signal changeover switch element 22 is turned on, One shunt switch element 14 is also turned on.
On the other hand, as the second DC signal changeover switch element 23 is turned off, the second shunt switch element 15 is also turned off. The third shunt switch element 16 is also turned off by the control voltage directly applied from the control circuit 21.
Thereby, only the second shunt switch element 15 connected to the second switch element 12 forming the signal passing path is turned off, while the first and third shunt switch elements 14 and 16 are turned on. Thus, signal leakage between the second and fourth high-frequency input / output terminals 102 and 104 and the first high-frequency input / output terminal 101 does not occur.

Next, when the first high-frequency input / output terminal 101 and the fourth high-frequency input / output terminal 104 are selected as a signal passing path, the first DC signal changeover switch element 22 is turned on, The shunt switch element 14 is also turned on. As the second DC changeover switch element 23 is turned off, the second shunt switch element 15 is also turned off.
Further, the third shunt switch element 16 is turned off.
Thereby, in particular, signal leakage between the second high-frequency input / output terminal 102 and the first high-frequency input / output terminal 101 is suppressed.

  In the second configuration example, the voltage is shared by the control voltage of the first and second DC signal changeover switch elements 22 and 23 and the control of the first and second shunt switch elements 14 and 15. Therefore, the circuit configuration is simplified and suitable for miniaturization.

In the above-described embodiment of the present invention, an example of a so-called SP3T switch has been described. However, the present invention is not limited to this, and can be applied to switches having other configurations.
In addition, when the operation of the switch element is switched with a negative voltage, a DC voltage blocking capacitor is unnecessary, and the present invention does not substantially change depending on the presence or absence of the capacitor, and the effects as described above. You can get the same.

1 is a circuit diagram illustrating a first configuration example of a switch semiconductor integrated circuit according to an embodiment of the present invention. It is a circuit diagram which shows the 2nd structural example of the switch semiconductor integrated circuit in embodiment of this invention. It is a characteristic line figure showing change of passage electric power to change of a switch element control voltage of a switch semiconductor integrated circuit in an embodiment of the invention. It is a circuit diagram which shows the structural example of a conventional circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... 1st switch element 12 ... 2nd switch element 13 ... 3rd switch element 14 ... 1st shunt switch element 15 ... 2nd shunt switch element 16 ... 3rd shunt switch element 101 ... 1st High frequency input / output terminal 102 ... Second high frequency input / output terminal 103 ... Third high frequency input / output terminal 104 ... Fourth high frequency input / output terminal

Claims (4)

A plurality of individual high-frequency input / output terminals, at least one common high-frequency input / output terminal, and the plurality of individual high-frequency input / output terminals and the common input / output terminal are respectively arranged to control conduction / non-conduction from the outside. A plurality of high-frequency switching elements configured to be possible, and a control circuit that controls the operation of the high-frequency switching elements, by controlling the operation of the high-frequency switching elements by the control circuit, A signal passing path can be formed between one desired individual high frequency input / output terminal of the plurality of individual high frequency input / output terminals and one desired common high frequency input / output terminal among the common high frequency input / output terminals. A switch semiconductor integrated circuit comprising:
A first DC signal switching switch element and a first resistor are provided in series between the common high frequency input / output terminal and the ground potential, while the common high frequency input / output terminal and the control circuit A second DC signal switching switch element and a second resistor are connected in series between a voltage source equal to the voltage applied to the output switch element, and the first and second DC signals are provided. The switch semiconductor integrated circuit, wherein the signal switching switch element is configured such that conduction / non-conduction can be interlocked with conduction / non-conduction of the plurality of high-frequency switching switch elements. The control circuit sets the first DC signal switching switch element to a non-conduction state when the signal passage path in which the high-frequency power to be passed is relatively large with respect to the other signal passage paths is turned on. While the second DC signal switching switch element is turned on,
When the signal passing path having a relatively small high-frequency power to be passed is made conductive with respect to the other signal passing paths, the first DC signal switching switch element is turned on, and the second DC signal switching is performed. 2. The switch semiconductor integrated circuit according to claim 1, wherein the switch element is configured to be in a non-conductive state. A shunt switch element for grounding the individual high frequency input / output terminals in high frequency by external control is connected to each of the plurality of individual high frequency input / output terminals, and the high frequency power to be passed is relative to other signal passing paths. A control signal for the shunt switch element connected to a large individual high frequency input / output terminal is shared with a control signal for the first DC signal changeover switch element,
The control signal of the shunt switch element connected to the individual high frequency input / output terminal whose high frequency power to be passed is relatively small with respect to other signal passing paths is made common with the control signal of the second DC signal changeover switch element. The switch semiconductor integrated circuit according to claim 1 or 2, wherein   The gate width of the field-effect transistor that constitutes the switching element for high-frequency switching connected to the individual high-frequency input / output terminal, where the high-frequency power that is allowed to pass is relatively large with respect to other signal passing paths, 2. The gate width of a field effect transistor constituting a high frequency switching device connected to a small individual high frequency input / output terminal relative to the signal passing path is set larger than the gate width of the field effect transistor. Item 4. The switch semiconductor integrated circuit according to any one of Items 3 to 4.

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