JP2009277970A - Circuit wiring board package - Google Patents

Abstract

Provided is a circuit wiring board mounting body suitable for miniaturization / thinning of three-dimensional mounting using a semiconductor device with high reliability of connection between double-sided wirings.
A circuit wiring board mounting body includes a semiconductor chip having a semiconductor layer and a wiring layer / element electrode for an element region formed on one side of the semiconductor device, and one side of the chip. A first insulating film 4 formed with a device electrode contact hole, a second insulating film 6 formed on the other surface, and a pad portion on the surface of the first insulating film connected to the device electrode. Along the first rewiring layer 7, the terminal electrode provided on the pad portion 8 of the first rewiring layer, the second rewiring layer 9 formed on the surface of the second insulating film, and the dicing line of the chip An interlayer wiring layer 10 formed on the side surface and connecting the first and second rewiring layers is provided, and terminal electrodes are overlapped and connected to land portions of the circuit wiring board PCB.
[Selection] Figure 1

Description

  The present invention relates to a circuit wiring board mounting body on which a semiconductor device is mounted, and more particularly to a circuit wiring board mounting body suitable for miniaturization / thinning in three-dimensional mounting.

  In the printed wiring board field, the number of electronic components such as semiconductor IC / LSI devices mounted on circuit wiring boards is also increasing significantly as user demands for higher functionality and multi-functionality of applied electronic devices increase. It is in. On the other hand, even when such a large number of electronic components are mounted, there is a strong demand for downsizing and thinning of the outer shape of the circuit wiring board mounting body, and in order to meet these demands, three-dimensional mounting technology has been developed conventionally. ing.

  Therefore, an example of a conventional three-dimensional mounting technique will be described with reference to FIG. 7. FIG. 7A shows a SiP (System in a Package) structure, and FIG. 7B shows a PoP (Package on Package) structure. FIG. 7C shows a PiP (Package in Package) structure.

  The SiP structure incorporates a multifunctional system into one package. A plurality of semiconductor LSI chips 71 are stacked on the package substrate 70, and the package substrate 70 and each chip 71 are electrically connected by bonding wires 72. However, it is a three-dimensional laminated form sealed as one package by the resin mold 73. Further, external terminals 74 made of solder balls for face-down bonding are provided.

  In the PoP structure, a plurality of package substrates 70a and 70b have the same form as the SiP structure, and a package having an upper substrate 70a is stacked on a package having a lower substrate 70b. In the PiP structure, a package having the same form as the SiP structure is stacked on the package substrate 70 a together with the other LSI chip 71 on the lower package substrate 70 b, and the entire package is formed by the outer resin mold 73. The sealed form is taken.

In any of the SiP, PoP, and PiP structures, the semiconductor IC / LSI chip 71 is used.
Can be mounted only from one side of the chip, and cannot be stacked by direct bonding between a plurality of chips, and the connection method is limited. In addition, for this reason, the number of bonding wires is remarkably increased as the system scale with the increase in functionality is increased, and the connection of bonding wires to the package substrate is generally performed at the outer peripheral edge portion thereof. There is a problem that the bonding area increases, and the package substrate and the entire mounting package are significantly enlarged.

  Further, as seen in Patent Document 1 and Patent Document 2, for example, a technique for three-dimensionally mounting a flip chip type electronic component on a circuit wiring board by a face-down bonding method or the like has been developed.

  In the semiconductor package technology with outer bumps of Patent Document 1, in particular, as shown in FIG. 1 and the like, an insulating resin having wirings 3 on both sides with respect to a normal semiconductor device chip 6 with inner bumps 2. A material in which the layer 5 is bonded to the sheet-like thermoplastic resin layer 4 is prepared, and the thermoplastic resin layer 4 is bent so as to wrap from the lower surface of the chip 6 toward the upper surface side. A package structure in which external terminals including outer bumps connected to a part of the wiring 3 are provided on both surfaces of the chip 6 and a plurality of such semiconductor packages are three-dimensionally stacked on a circuit wiring board is disclosed. Has been.

  In the wafer technology with solder bumps of Patent Document 2, as shown in FIG. 1 and the like, the through holes 2 penetrating the wafer 1 having the rewiring circuits 3 and 4 formed on both sides are vertically and horizontally latticed. The rewiring circuits 3 and 4 are connected by a plating 9 provided on the inner wall surface of at least a part of the through holes 2. As shown in FIGS. 4 and 5, a wafer structure is disclosed that is cut into chips along the array of through-holes 2 groups.

  However, in the technique of Patent Document 1, the semiconductor device chip itself is not subjected to special processing for enabling three-dimensional stacking, and the chip is formed between the double-sided wiring insulating resin layer and the thermoplastic resin layer. The package structure is such that the laminated sheet is bent and the chip is wrapped. Therefore, the package outer shape and volume are considerably larger than the semiconductor device chip size. In addition, when bending, for example, a connection failure due to misalignment between the wiring and the inner bump, or a connection failure due to misalignment between the outer bumps of the stacked adjacent packages and the external terminals (misalignment) occurs. It is easy to deteriorate. Furthermore, there is a problem in that the bending process itself is difficult to carry out while maintaining the connection consistency with high accuracy.

Further, in the technique of Patent Document 2, since the package outer shape is a chip state obtained by cutting a wafer provided with a rewiring circuit on both sides, it can be made smaller and thinner than the case of Patent Document 2. There is a difficulty in the operation of penetrating and forming a large number of through-holes in a lattice pattern in the vertical and horizontal directions. Since a large number of through holes are formed in the wafer, the chip size is increased by at least the area of the through holes, so that the wafer yield is reduced. Further, since the chip peripheral side wall after cutting has an uneven shape due to the through hole, the chip peripheral side wall is liable to be damaged, and the wiring connection between the redistribution circuits is impaired, and the connection wiring to the inner surface of the through hole There is a problem that the degree of freedom of pattern formation is significantly reduced.
Japanese Patent Laid-Open No. 2004-172329 Japanese Patent Laid-Open No. 2005-123569

  The present invention solves the above-mentioned conventional problems, uses a semiconductor device with high reliability of connection between double-sided wirings, and is particularly suitable for circuit wiring board mounting suitable for miniaturization / thinning of three-dimensional mounting. The purpose is to provide.

  The present invention according to claim 1 is a circuit wiring board mounting body in which a semiconductor device is mounted on a circuit wiring board, and the semiconductor device is diced and formed on one surface of a semiconductor wafer. A semiconductor chip having a wiring layer and an element electrode for the element region, a first insulating film formed on one surface of the chip and having a contact hole for the element electrode, and a second insulation formed on the other surface of the chip A coating, a first redistribution layer formed to include a pad portion on the surface of the first insulating coating connected to the element electrode, a terminal electrode provided on the pad portion of the first redistribution layer, A second redistribution layer formed on the surface of the second insulating film, and an interlayer wiring layer formed on a side surface along the dicing line of the chip to electrically connect the first and second redistribution layers to each other. Prepared, said half Body device, the land portion of the circuit wiring while the wiring pattern layer provided on the surface of the substrate, characterized in that it is connected to overlap the terminal electrodes.

  According to a second aspect of the present invention, in the circuit wiring board mounting body according to the first aspect, the second rewiring layer of the semiconductor device includes a pad portion as an external terminal portion, and the second rewiring layer The pad portion and the land portion of the wiring pattern layer of the circuit wiring board are electrically connected.

  According to a third aspect of the present invention, in the circuit wiring board mounting body according to the first or second aspect, the circuit wiring board is included in the wiring pattern layer provided on the other surface and the wiring pattern layer. A conductive via for electrically connecting the wiring pattern layers on both sides of the circuit wiring board, and an external terminal electrode provided on the land portion of the wiring pattern layer on the other surface. And

  According to a fourth aspect of the present invention, in the circuit wiring board mounting body according to any one of the first to third aspects, a plurality of the semiconductor devices are stacked and three-dimensionally mounted on the circuit wiring board. It is characterized by that.

  According to the circuit wiring board mounting body of the present invention, the semiconductor device to be mounted can be connected to the external terminals from both sides, and the size of the electronic component mounted on the circuit wiring board is reduced to a semiconductor chip level and thinned. In particular, a three-dimensional mounting form corresponding to high functionality and multi-functionality can be greatly downsized.

In addition, since the interlayer wiring layer of the semiconductor device can be formed on a flat side surface along the dicing line of the semiconductor chip, the degree of freedom of pattern formation is increased, and the high accuracy and high level between the first and second rewiring layers can be achieved. Reliable interlayer connection is easily obtained. In addition, since the through hole as in Patent Document 2 is not formed, the area of the semiconductor device can be reduced, the yield of the semiconductor wafer can be improved, damage to the peripheral wall of the semiconductor chip can be avoided, and the interlayer wiring can be avoided. A good connection state of the layers is maintained.Furthermore, external terminal connection is possible from both sides of the semiconductor device, and a plurality of semiconductor devices can be directly joined to each other to form a laminate that is electrically connected. Even if the system scale increases due to the increase in functionality, the number of electrical connections with the wiring pattern layer of the circuit wiring board can be remarkably reduced compared to the above-mentioned prior art, while the increase in function can be achieved. It is possible to achieve an effect that the body can be reduced in size and thickness.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a semiconductor device mounted on a circuit wiring board mounting body of the present invention and a manufacturing method thereof will be described with reference to FIGS. Here, the same reference numerals denote the same or similar components throughout the drawings.

  First, an embodiment of a semiconductor device according to the present invention will be described with reference to FIG. 1A is a side view showing a part of the semiconductor device in cross section, FIG. 1B is a partially enlarged perspective view of the semiconductor device, and FIG. 1C is a rewiring of the semiconductor device. It is a top view which shows an example of the pattern of a layer. These drawings are expressed to such an extent that the contents of the present invention can be understood, and the dimensions and shapes between the drawings do not necessarily match.

  The semiconductor device 1 has a semiconductor chip 2 made of, for example, a silicon substrate as a main body portion. As will be described later, the semiconductor chip 2 is diced from a semiconductor wafer and separated into individual pieces. Although not shown on at least one surface (the upper surface in the drawing), selective diffusion of various conductive impurities is performed. Thus, an element region such as an IC / LSI circuit and a wiring layer connected thereto are formed. A plurality of element electrodes 3 formed on a part of the wiring layer for the element region are provided on the one surface.

  Further, the first insulating film 4 provided on the one surface is formed so as to have a flat surface, and has a corresponding contact hole 5 so as to expose the device electrode 3. A second insulating film 6 is deposited on the other surface (lower surface in the drawing) of the semiconductor chip 2 in a flat state.

  A first rewiring layer 7 is provided on the surface of the first insulating coating 4. The first rewiring layer 7 is connected to the element electrode 3 through the contact hole 5 and is formed with a desired circuit wiring pattern, and is formed on a part of the pattern as can be seen from FIG. The pad portion 8 is included. A second rewiring layer 9 is provided on the surface of the second insulating coating 6. Although not shown, the second rewiring layer 9 is formed with a desired circuit wiring pattern, and can include a pad portion formed in a part of the pattern.

For easy understanding with reference to FIG. 1B, the side surfaces S1 and S2 of the semiconductor chip 2 have a perpendicular plane along the orthogonal dicing lines D1 and D2, and the side surfaces S1 and S2 include An interlayer wiring layer 10 for electrically connecting the first and second rewiring layers 7 and 9 to each other
Is formed.

  Here, as an example, the first and second redistribution layers 7 and 9 are formed to a thickness of 12 μm by a conductive material such as copper plating, gold plating or vapor deposition, and the first and second insulating coatings 4. , 6 have a thickness of 10 μm.

  The wiring pattern shapes of the first and second redistribution layers 7 and 9 take various forms depending on the relationship between the semiconductor device 1 and other peripheral electronic components. One example is shown in FIG. Is shown in In addition, although the example in which the element region and the element electrode are formed on one surface of the semiconductor chip 2 has been described, it may be formed on the other surface, in which case the second insulating film 6 is formed. And the 2nd rewiring layer 9 can take the form similar to the said 1st insulating film 4 and the 1st rewiring layer 7 regarding the relationship with a contact hole or an element electrode.

  Although the first redistribution layer 7 includes the pad portion 8, whether or not the second redistribution layer 9 includes the pad portion depends on the mounting form of the semiconductor device. Can be selected. Although not shown, an insulating protective film can be formed on the surfaces of the first and second redistribution layers 7 and 9.

  According to the semiconductor device of such an embodiment, the double-sided wiring pattern by the first and second redistribution layers 7 and 9 is provided, and a double-sided multi-pin configuration is possible. In addition, the size of the electronic component mounted on the circuit wiring board can be reduced and thinned to the level of a semiconductor chip, and a circuit wiring board mounting body of a three-dimensional mounting form corresponding to high functionality and multi-function can be obtained. The size can be greatly reduced.

  Next, an example of a semiconductor device manufacturing method according to the embodiment of the present invention will be described with reference to FIG.

  In the step shown in FIG. 2A, the element regions X, Y, and Z corresponding to the desired number of IC chips are formed on the semiconductor wafer 2A made of the Si substrate by a normal IC manufacturing technique. A chip wiring layer (not shown) and a large number of element electrodes 3 constituting a part thereof are formed on the surface of each element region X, Y, Z.

  In the step shown in FIG. 2B, for example, a liquid photosensitive polyimide precursor is spin-coated over one surface (upper surface) of the wafer 2A including the element electrode 3, and each electrode layer is formed by photolithography. A first insulating film 4 having contact holes 5 for exposing 3 is formed. Further, the second insulating film 6 is formed by spin-coating and curing a liquid photosensitive polyimide precursor on the other surface (lower surface) of the wafer 2A.

  In forming the first and second insulating coatings 4 and 6, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like may be used as another resin material. The photosensitive resin is not limited to liquid and may be laminated on the wafer using a film-like resin. The coating of the photosensitive resin is not limited to the application by spin coating, and may be performed by any one of curtain coating, screen printing, spray coating, and the like.

  In the step shown in FIG. 2C, the first redistribution layer 7 connected to the element electrode layers 3 in the element regions X, Y, and Z through the contact holes 5 is formed on the surface of the first insulating film 4. A conductive material is deposited on the substrate and patterned using, for example, a semi-additive method, thereby forming a circuit pattern including a pad portion (see 8 in FIG. 1B). A second rewiring layer 9 is formed in a circuit pattern on the surface of the second insulating coating 4 in the same manner as the first rewiring layer 7. Then, in the wafer process stage, probing inspection is performed to determine whether the characteristics are good or bad.

  In the step shown in FIG. 2D, a plurality of semiconductor chips 2 separated by dicing and separating along the boundaries between the element regions X, Y and Z are taken out.

  Next, in the step shown in FIG. 2E, the first and second redistribution layers 7 are formed on the flat side surfaces S1 and S2 (see FIG. 1B) along the dicing line of the semiconductor chip 2. 9 An interlayer wiring layer 10 is formed to electrically connect the layers together. Prior to this step, if the side surfaces S1 and S2 are appropriately flattened or smoothed by physicochemical etching such as chemical etching or plasma etching, the interlayer wiring layer 10 can be obtained. Can be formed more accurately and reliably.

  According to such a method of manufacturing a semiconductor device according to the present invention, the interlayer wiring layer 10 can be formed on a flat side surface along the dicing line of the semiconductor chip 2, so that the degree of freedom of pattern formation is increased. A highly accurate and reliable interlayer connection between the first and second redistribution layers 7 and 9 can be easily obtained. In addition, since a through hole as in Patent Document 2 is not formed, the wafer yield is improved, damage to the peripheral side wall of the semiconductor chip can be avoided, and the connection state of the interlayer wiring layer 10 can be maintained well. it can.

  Next, other various embodiments such as a method of forming the second rewiring layer 9 and the interlayer wiring layer 10 will be described.

[In the case of forming the second rewiring layer]: Any one of the following methods (1) to (3) can be selectively employed.

(1) A method in which a conductive material is deposited on the entire surface of the second insulating coating 6 and patterned by a photolithography method.

(2) A method of forming a desired pattern by spraying a conductive ink containing silver or copper on the surface of the second insulating coating 6 by an inkjet method.

(3) A method of forming a desired pattern on the surface of the second insulating coating 6 by a direct drawing method using a laser.

By the way, the second insulating film 6 is formed by a form formed of a SiO2 film formed on the back surface side of the semiconductor chip 2 or a plurality of films of a SiO2 film and a resin film such as polyimide deposited on the surface. Various forms such as the above can also be taken. Then, regardless of the form of the second insulating film 6, the second redistribution layer forming methods (1) to (3) can be applied, and the surface of the second insulating film is a resin film. In this case, the adhesion strength of the second rewiring layer is high.

  When the second insulating film 6 is made of a SiO2 film, the adhesion strength can be increased by forming a conductive thin film on the SiO2 surface and forming the second rewiring layer 9 thereon. In this case, the conductive thin film can be selected from metals such as Al, Au, Pt, Ti, Ag, Cu, Bi, Sn, Ni, Cr, Zn, and alloys thereof. The conductive thin film can be formed using various conventional methods such as a sputtering method, a vacuum deposition method, and a plating method, and the thickness is preferably several μm or less. Such methods (1) to (3) can be similarly applied to the formation of the first redistribution layer 4.

[In the case of interlayer wiring layer formation]: Any one of the following methods (a) to (d) can be selectively employed.

(A) A method of forming an interlayer wiring layer on the side surface of the semiconductor chip 2 by, for example, forming a seed layer of Ni—Cr or Cu and performing electrolysis or electroless plating by a sputtering method and patterning by a photolithography method.

(B) A method of forming a desired pattern by spraying conductive ink containing silver or copper on the side surface of the semiconductor chip 2 by an inkjet method.

(C) A method in which a seed layer is formed on the side surface of the semiconductor chip 2 by sputtering, laser patterning is performed, and then formed by electrolytic or electroless plating.

(D) A method in which a seed layer is formed on the side surface of the semiconductor chip 2 by sputtering, followed by electrolysis or electroless plating, and a desired pattern is formed by laser.

  The side surface of the semiconductor chip 2 may be a dicing exposed surface of the side surface of the semiconductor substrate material, or may have a form in which a resin film is previously deposited on the side surface. The formation methods (a) to (d) of the interlayer wiring layer can be selectively applied.

  Next, an embodiment of a circuit wiring board mounting body of the present invention will be described with reference to FIG.

On the circuit wiring board PCB having the land portions 20a included in the wiring pattern layer 20, the first to third semiconductor devices 21 to 23 constituting the stacked body that are directly connected to each other and electrically connected are stacked. Has been implemented. Each of these semiconductor devices 21 to 23 has a dimension / shape different from that of the semiconductor device 1 in the embodiment shown in FIGS. 1 and 2 and is shown upside down. First and second insulating coatings 4 and 6 formed on both surfaces of the chip 2, first and second redistribution layers 7 and 9 deposited on the surfaces of the respective insulating coatings 4 and 6, and side surfaces of the semiconductor chip 2, respectively. The interlayer wiring layer 10 is provided.

  Each of the semiconductor devices 21 to 23 has a terminal electrode 21 </ b> B such as a solder bump provided on the surface of the plurality of pad portions 8 included in the first redistribution layer 7, respectively. , 22B, and 23B.

  The plurality of terminal electrodes 21B of the first semiconductor device 21 are overlapped and fixed to the plurality of land portions 20a of the wiring pattern layer 20 of the circuit wiring board PCB, respectively. The plurality of terminal electrodes 22B of the second semiconductor device 22 are overlapped and fixed to the plurality of pad portions 8 included in the second redistribution layer 9 of the first semiconductor device 21, respectively, and the plurality of terminals of the third semiconductor device 23 are connected. The electrode 23 </ b> B is overlapped and fixed to each of the plurality of pad portions 8 included in the second redistribution layer 9 of the second semiconductor device 22.

  Each of the second redistribution layers 9 of the first and second semiconductor devices 21 and 22 has a plurality of pad portions as external terminals for connection to the terminal electrodes 22B and 23B of the second and third semiconductor devices, respectively. 8 is included. However, since the third semiconductor device 23 is located in the outermost layer of the mounting body, the second redistribution layer 9 may not require a pad portion as an external terminal. It is. It is also possible to mount the third semiconductor device 23 directly on the first semiconductor device 21 without mounting the second semiconductor device 22. In this case, the third semiconductor device 23 is connected to the second semiconductor device. It can also be handled as a device.

  According to such an embodiment of the circuit wiring board mounting body of the present invention, the size of the semiconductor device including a large number of terminal electrodes is reduced and reduced in thickness to the semiconductor chip level, so that high functionality and multi-function are supported. Thus, the circuit wiring board mounting body of the three-dimensional mounting form can be greatly downsized.

  Further, the interlayer wiring layer is formed on a flat side surface along the dicing line of the semiconductor chip, and does not have a through hole as in Patent Document 2, so that damage to the peripheral wall of the semiconductor device can be avoided, and the connection between the wiring layers can be avoided. A circuit wiring board mounting body with good reliability can be obtained.

  Next, the 1st-3rd Example concerning embodiment of the circuit wiring board mounting body of this invention is shown in FIGS. 4-6, The structure and its manufacturing method are demonstrated. 4 to 6 also indicate that the same reference numerals as those shown in FIGS. 1 to 3 are the same or similar components.

  First, a first embodiment of the circuit wiring board mounting body of the present invention will be described with reference to FIG. The circuit wiring board mounting body 40 of the first embodiment shown in FIG. 4 (e) is manufactured through the steps of FIGS. 4 (a) to 4 (d).

  That is, in the process of FIG. 4A, the semiconductor device 21 as shown in FIG. 3 is connected to each terminal electrode 21B made of the solder bump or ball of the circuit wiring board PCB having the single-sided wiring pattern layer 20. It arrange | positions in the state facing each land part 20a.

  In the step of FIG. 4B (reflow step), the solder bumps of the terminal electrodes 21B are reflowed by heating, whereby the terminal electrodes 21B are electrically connected and fixed to the land portions 20a. In the step of FIG. 4C (underfill process), each terminal electrode 21B and the connection portion are connected by filling an insulating resin 30 made of, for example, silicon resin between the semiconductor device 21 and the circuit wiring board PCB. However, it is covered with the insulating resin 30 to be protected from the outside air, and the support strength of the semiconductor device 21 to the circuit wiring board PCB is enhanced.

  4D (wire bonding process), the pad portions 8 of the second rewiring layer 9 on the upper surface side of the semiconductor device 21 and the peripheral portion of the wiring pattern layer 20 of the circuit wiring board PCB are provided. The plurality of land portions (bonding pad portions) 20b are electrically connected by a plurality of bonding wires 31 made of, for example, gold wires.

  In the step (molding step) of FIG. 4E, the semiconductor device 21 and the bonding wire 31 are entirely covered, and an insulating resin material such as an epoxy resin is molded to form a package portion 32 having a desired outer shape. It is formed. Prior to the formation of the package portion 32, the semiconductor device 21 and the bonding wire 31 can be covered in advance with an encap material made of, for example, silicon resin. In this way, the final structure of the circuit wiring board mounting body 40 in the first embodiment of the present invention is obtained.

  Next, a second embodiment of the circuit wiring board mounting body of the present invention will be described with reference to FIG. The circuit wiring board mounting body 50 of the second embodiment shown in FIG. 5 (f) is manufactured through the steps of FIGS. 5 (a) to 5 (e).

  That is, in the process of FIG. 5A, in place of the circuit wiring board PCB in the first embodiment, for example, a multilayer circuit in which circuit wiring boards PCB1 to PCB4 each having wiring pattern layers provided on four insulating boards are laminated. A wiring board 35 is used. The wiring pattern layer 36 formed on one surface (upper surface) of the multilayer circuit wiring board 35 has a plurality of land portions 36a and 36b. Another wiring pattern layer 37 formed on the other surface (lower surface) of the multilayer circuit wiring board 35 has a plurality of land portions 37a. Wiring pattern layers without reference signs are also provided on the inner layer of the multilayer circuit wiring board 35, and the wiring pattern layers are connected by interlayer conductive vias 38. Then, the semiconductor device 21 as shown in FIGS. 3 and 4 has each terminal electrode 21 </ b> B included in each land portion included in a part of the wiring pattern layer 36 on the multilayer circuit wiring board 35. It arrange | positions in the state facing 36a.

  Next, in each process shown in FIGS. 5B to 5E, the reflow process, the underfill process, the wire bonding process and the molding process similar to those in FIGS. 4B to 4E are performed. Implemented sequentially. In these steps, as shown in FIG. 5B, the terminal electrodes 21 </ b> B are electrically connected and fixed to the land portions 36 a of the wiring pattern layer 36. Further, as shown in FIG. 5C, the terminal electrodes 21 </ b> B and the connection portions are covered and protected by the insulating resin 30 filled between the semiconductor device 21 and the multilayer circuit wiring board 35, and the semiconductor device 21 is also protected. The support strength to the circuit wiring board PCB is increased. As shown in FIG. 5D, a plurality of lands provided on each pad portion 8 of the second redistribution layer 9 on the upper surface side of the semiconductor device 21 and on the peripheral portion of the wiring pattern layer 36 of the multilayer circuit wiring board 35. The part (bonding pad part) 36 b is electrically connected by a plurality of bonding wires 31. Then, as shown in FIG. 5E, the semiconductor device 21 and the bonding wires 31 are entirely covered, and an insulating resin material such as an epoxy resin is molded to form the package portion 32.

  In the step of FIG. 5F, the external terminal electrodes 35B made of, for example, solder bumps or balls are formed on the surfaces of the land portions 37a of the wiring pattern layer 37 on the lower surface side of the multilayer circuit wiring board 35. In this way, a compact packaging structure is obtained in which the circuit wiring board mounting body 50 in the second embodiment of the present invention can be attached to a board or panel of an electronic device by face-down bonding.

  Furthermore, the circuit wiring board mounting body 60 of the third embodiment of the present invention shown in FIG. 6 (e) incorporates a much more versatile large-scale system than the above-mentioned embodiments. Yes, it is manufactured through the steps of FIGS. 6 (a) to 6 (d). The multilayer circuit wiring board 35 used here may be different in the shape of each wiring pattern layer and the number and arrangement of interlayer conductive vias from the case of the second embodiment, but the constituent members are the same. The first to third semiconductor devices 25 to 27 are smaller in chip size toward the upper one, but all of them are more multifunctional than the semiconductor devices 1, 21 to 23 shown in FIGS. The chip size is large, and the components are similar. Accordingly, parts having the same or similar configurations as those in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof is omitted.

  6A, each terminal electrode 25B of the first semiconductor device 25 is formed on each land portion 36a of the wiring pattern layer 36 formed on the upper surface of the multilayer circuit wiring board 35 in which the circuit wiring boards PCB1 to PCB4 are laminated. Each one.

  6B, the terminal electrodes 26B of the second semiconductor device 26 are overlaid on the pad portions 8 of the second redistribution layer 9 of the first semiconductor device 25, respectively. Each terminal electrode 27 </ b> B of the third semiconductor device 27 is overlaid on each pad portion 8 of the second redistribution layer 9. Then, a reflow process similar to that of the second embodiment is performed, and electrical and physical connections are obtained at each overlapping portion.

  In the step of FIG. 6C, each pad portion 8 of each second redistribution layer 9 on the upper surface side of the first to third semiconductor devices 25 to 27 and the periphery of the wiring pattern layer 36 of the multilayer circuit wiring board 35 A plurality of land portions (bonding pad portions) 36 b provided on the portion are electrically connected by a plurality of bonding wires 31, respectively.

  In the step of FIG. 6D, the package portion 32 is formed by molding an insulating resin material such as an epoxy resin so as to cover the first to third semiconductor devices 25 to 27 and the bonding wire 31 as a whole. It is formed.

  In the step of FIG. 6E, the surface of each land portion 37a of the wiring pattern layer 37 on the lower surface side of the multilayer circuit wiring board 35 is the same as the bump forming step shown in FIG. 5F of the second embodiment. Each terminal electrode 35B is formed on top. In this manner, the circuit wiring board mounting body 60 in the third embodiment of the present invention is much larger and more multifunctional than the above embodiments, and is compact enough to be attached to an electronic device. A packaged structure is obtained.

  By the way, in the third embodiment, the underfill process (see FIG. 5C) of the second embodiment is excluded, but the reflow process in FIG. 6B and the wire bonding process in FIG. 6C. In between, the underfill process with respect to each clearance gap between the multilayer circuit wiring board 35 and the 1st-3rd semiconductor devices 25-27 may be performed similarly to the case of 2nd Example.

  In addition, the terminal electrodes 21B to 23B, 25B to 27B, and the external terminal electrode 35B in each embodiment have been described with a solder bump or ball-like protruding electrode structure, but a beam lead type extraction electrode structure may be used. The circuit wiring board PCB and the multilayer circuit wiring 35 in each embodiment constitute a part of a package for the mounted semiconductor device, and can also be referred to as a package board.

  The term “rewiring” in the first and second rewiring layers 7 and 9 is a term used in contrast to a wiring layer in which a semiconductor wafer or chip is directly formed in a semiconductor element region. A wiring layer formed to achieve a circuit configuration suitable for mounting on a wiring board or stacking of a plurality of chips is expressed as rewiring. Of course, the first and second rewiring layers 7 and 9 can be simply expressed as a wiring layer, a wiring pattern, a conductor circuit, or the like without losing the essence of the present invention.

It is a figure for demonstrating one Embodiment of the semiconductor device mounted in the circuit wiring board mounting body which concerns on this invention, (a) is a side view which shows a partial cross section of a semiconductor device, (b) is a semiconductor device FIG. 4C is a partially enlarged perspective view, and FIG. 4C is a plan view showing an example of a pattern of the rewiring layer of the semiconductor device. It is a figure for demonstrating the manufacturing method of the semiconductor device shown in FIG. 1, (a)-(e) is sectional drawing according to the process. , It is a side view which has a partial cross section which shows one Embodiment of the circuit wiring board mounting body which concerns on this invention. It is a side view which has a partial cross section which shows 1st Example of the circuit wiring board mounting body which concerns on this invention. It is a side view which has a partial cross section which shows 2nd Example of the circuit wiring board mounting body which concerns on this invention. It is a side view which has a partial cross section which shows the 3rd Example of the circuit wiring board mounting body which concerns on this invention. It is a side view which has a partial cross section which shows the three-dimensional mounting form in three types of prior art of (a)-(c).

Explanation of symbols

1, 2 to 23, 25 to 27 Semiconductor device 2 Semiconductor chip 2A Semiconductor wafer 3 Element electrode 4 First insulating coating 5 Contact hole 6 Second insulating coating 7 First redistribution layer 8 Pad portion 9 Second redistribution layer 10 Interlayer Wiring layer 20, 36, 37 Wiring pattern layer (for circuit wiring board)
21B to 23B Terminal electrode PCB, 35 Circuit wiring board X, Y, Z Element region 30 Insulating resin 31 Bonding wire 32 Package portion

Claims (4)

A circuit wiring board mounting body in which a semiconductor device is mounted on a circuit wiring board, wherein the semiconductor device is
A semiconductor chip having a wiring layer and an element electrode for an element region formed by dicing a semiconductor wafer and formed on one surface, and a first contact hole formed on one surface of the chip and having a contact hole for the element electrode. An insulating coating; a second insulating coating formed on the other surface of the chip; a first redistribution layer connected to the device electrode and including a pad portion on the surface of the first insulating coating; A terminal electrode provided on a pad portion of the first redistribution layer; a second redistribution layer formed on a surface of the second insulating film; and the first and the second redistribution layers formed on a side surface along a dicing line of the chip. An interlayer wiring layer that electrically connects the second rewiring layers to each other, and the semiconductor device is connected by overlapping the terminal electrode on a land portion of a wiring pattern layer provided on one surface of the circuit wiring board Has been Circuit wiring board mounting member, characterized in that.   The second rewiring layer of the semiconductor device includes a pad portion as an external terminal portion, and the pad portion of the second rewiring layer and the land portion of the wiring pattern layer of the circuit wiring board are electrically connected. The circuit wiring board mounting body according to claim 1.   The circuit wiring board includes a wiring pattern layer provided on the other surface, a land portion included in the wiring pattern layer, a conductive via electrically connecting the wiring pattern layers on both surfaces of the circuit wiring board, and the other The circuit wiring board mounting body according to claim 1, further comprising an external terminal electrode provided on a land portion of the wiring pattern layer on the surface.   4. The circuit wiring board mounting body according to claim 1, wherein a plurality of the semiconductor devices are stacked and three-dimensionally mounted on the circuit wiring board.