JP2009272340A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that a standard cell type CMOS semiconductor integrated circuit increases in layout area since wiring resources of upper-layer wiring are consumed even for a wiring connection between logic gate cells at near positions and then the logic gate cells do not have larger spread density because of deficiency of the wiring resources. <P>SOLUTION: A logic gate cell includes a special terminal structure and then when logic gate cells are arranged at specified near positions, a wiring connection is made using only first and second metal wiring layers to increase wiring re sources of an upper layer, thereby reducing the layout area. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a CMOS semiconductor integrated circuit designed by a standard cell system, and relates to the arrangement of logic gate cells used therein, the wiring structure between the logic gate cells, and the terminal structure of the logic gate cell itself, thereby making effective use of wiring resources. The present invention relates to means that can be used to help reduce the layout area of a CMOS semiconductor integrated circuit.

The standard cell system is a well-known technique for designing logic circuits in CMOS semiconductor integrated circuits. In the standard cell system, a unit for realizing a logic function is prepared as a logic gate cell. Representative logic functions of the logic gate cell include NAND, NOR, NOT, AND, OR and the like. The logic circuit is realized as a connection structure in which these logic gate cells are combined and interconnected at the logic design stage. This is called a netlist. Each logic gate cell has a layout shape for each logic gate cell so that it can be used as a component part of layout design. At the layout design stage, layout shape data corresponding to the logic gate cells included in the netlist is arranged in a plurality of cell columns, and the wiring length is not increased when wiring between terminals of the logic gate cells is performed at this time. The arrangement of the logic gate cells is determined so that all the necessary wirings can be completely connected without contact with each other. However, in practice, if the wiring process is not performed, it cannot be determined whether or not the wiring can be completely connected, and if the logic gate cells are not properly arranged, the wiring process cannot be completed, so that the arrangement needs to be redone.

The wiring track concept is used in the wiring process. In the metal wiring layers such as the first layer (M1), the second layer (M2), and the third layer (M3), a position where the wiring should be placed when it is desired to pass the wiring is defined as a wiring track. If the M1 layer is used for horizontal wiring, the M2 layer is usually used for vertical wiring, and the M3 layer is used for horizontal wiring. Since these wiring tracks look like a lattice when viewed simultaneously, they are also called wiring grids. In addition, the wiring track of each layer that can be used for wiring is sometimes referred to as a wiring resource, and when the wiring is not completed by the wiring process, the wiring resource is insufficient. When the netlist is determined, it is determined how much wiring is required between the logic gate cells. However, if the logic gate cells are densely laid in a small area, the wiring resources that can be used by the netlist are not satisfied because the available wiring resources are small. The wiring process is not completed. In this case, the packing density of the logic gate cells is lowered, and in other words, the logic gate cells are sparsely arranged in a wide area, thereby increasing the available wiring resources, thereby completing the wiring process. How much area is required depends on the design object. In general, as the logic gate cells are arranged sparsely in a wider area, it becomes easier to complete the wiring process. However, the layout cost of the circuit increases instead, and the manufacturing cost of the integrated circuit chip increases.

Continue to explain the background technology. A typical prior art of a logic gate cell used in a CMOS semiconductor integrated circuit will be described. FIG. 13A illustrates a layout structure according to the prior art of the logic gate cell NAND2. A logic symbol of NAND2 and a circuit diagram of a transistor level are shown in FIG. FIG. 13B shows the diffusion layer and the polysilicon wiring layer 3 extracted from FIG. 13A. The diffusion layer includes a P-type diffusion layer 1 and an N-type diffusion layer 2. A MOS transistor is formed at the intersection of the diffusion layer and the polysilicon wiring layer, PMOS transistors 4 and 5 are formed on the P-type diffusion layer 1, and NMOS transistors 6 and 7 are formed on the N-type diffusion layer 2. FIG. 13C similarly shows the M1 wiring layer, which is a metal wiring layer, and contact holes. The M1 wiring layer is usually used for wiring connection inside the logic gate, and the M2 wiring layer, the M3 wiring layer, and a wiring layer higher than that are usually used for wiring between the logic gates.
The VDD power supply line is a high potential power supply line and runs in the first direction (lateral direction) as is apparent from FIGS. 13A and 13C, and the GND power supply line is a ground potential power supply line. It is also running in the first direction. When the power supply line runs in the first direction in the logic gate cell, the wiring of the M2 wiring layer used for the wiring between the logic gate cells is inevitably used for the wiring in the second direction. This will be described. In the standard cell layout, there is a case where it is desired to use the M1 layer for wiring by providing a cell row in which no logic gate cell is arranged. In this case, since the power supply wiring runs in the first direction in the M1 wiring layer, the wiring in the M1 layer must be used as the wiring in the first direction. As a result, the wiring in the upper M2 wiring layer is used as the wiring in the second direction orthogonal to each other.
The source region of the PMOS transistor 4, that is, the P-type diffusion region associated with the PMOS transistor 4 is connected to the VDD power supply line from the P-type diffusion region associated with the PMOS transistor 4 by the M1 wiring 11. To the VDD power supply line through the M1 wiring 12. Further, the source region of the NMOS transistor 6, that is, the N-type diffusion region associated with the NMOS transistor 6 is connected to the GND power supply line by the M1 wiring 13. Further, the M1 wiring 14 is connected from the drain region common to the PMOS transistors 4 and 5, that is, the P-type diffusion region associated with both the PMOS transistors 4 and 5, to the drain region of the NMOS transistor 7, that is, the N-type diffusion region associated with the NMOS transistor 7. The output terminal Y of the NAND 2 exists on the M1 wiring 14. The PMOS transistors 4 and 5 and the NMOS transistor 7 are transistors existing in the output part of the logic gate cell. A and B are input terminals of the NAND 2 and exist in the M1 wiring layer. The input terminal A is connected to the polysilicon wiring 3 through the contact hole from the M1 wiring layer, and further has an electrical connection with the gate of the PMOS transistor 4 and the gate of the NMOS transistor 6. Similarly, the input terminal B is electrically connected to the gate of the PMOS transistor 5 and the gate of the NMOS transistor 7.

The main configuration of the above-described conventional logic gate cell NAND2 can be summarized as follows. The logic gate cell is composed of an interconnection of a PMOS transistor and an NMOS transistor, and has an input terminal and one output terminal. The input terminal is electrically connected to each of the gate of the PMOS transistor and the gate of the NMOS transistor. The output terminal is electrically connected to both the drain of the NMOS transistor existing in the output portion as well as the drain of the PMOS transistor existing in the output portion of the logic gate cell. Further, the logic gate cell has VDD and GND power supply wiring by the M1 wiring layer running in the first direction (lateral direction), and the input terminal and the output terminal exist in the M1 wiring layer. Further, since the power supply line runs in the first direction, the M2 wiring layer is inevitably used for the wiring running in the second direction (vertical direction) as the inter-terminal connection wiring of the logic gate cell.

In the standard NAND 2 according to the prior art, as described above, the M1 wiring layer is used for all the wirings in the logic gate cell, and the input terminals and the output terminals are all in the M1 wiring layer. The reason is that the wiring is completed with only the M1 wiring layer inside the logic gate cell, and it is not necessary to use any other metal wiring layer, and if the M2 wiring layer above the M1 wiring layer is used, for example. This is based on the idea that extra wiring resources are consumed. The case where the input terminal is provided in the polysilicon wiring layer existed in an era when the integration degree of the semiconductor integrated circuit was low and the operation speed was low, but it is not seen at present. In the manufacturing process where the line width is 0.18 micrometers or more and the miniaturization is advanced, there is a problem that the operation speed is lowered due to the resistance component when the polysilicon wiring layer is used for the wiring between the logic gates, and the design restriction at the time of wiring connection. Due to problems in the realization of CAD tools due to the complexity, the case of having an input terminal in the polysilicon wiring layer disappeared, and now it is standard to have an input terminal in the M1 wiring layer. The standard design of NAND2 frequently used for logic design is as described above.
As a rare example, there is a layout example of a logic gate cell having an output terminal in an M2 wiring layer in the case of realizing a reduction in area for a logic gate cell having a more complicated structure and a function different from that of NAND2.
Japanese Patent No. 3110422

Logic gate cells that are frequently used after the NAND 2 include a two-input NOR, abbreviated NOR2, NOT, a three-input NAND, abbreviated NAND3, a three-input NOR, and abbreviated NOR3. A logic circuit used in a CMOS semiconductor integrated circuit can be realized with almost no inconvenience by using the above-mentioned five types of logic gate cells and a composite logic gate cell combining them. 14 and 15 show layout examples of NOR2 and NOT according to the prior art. The drawing method is the same as that shown in FIG. FIG. 18 and FIG. 20 show NOT and NOR2 logic symbols and transistor level circuit diagrams.
In any case, the logic gate cell is composed of an interconnection of a PMOS transistor and an NMOS transistor, and has an input terminal and one output terminal. The input terminal is electrically connected to each of the gate of the PMOS transistor and the gate of the NMOS transistor. The output terminal is electrically connected to both the drain of the NMOS transistor existing in the output portion as well as the drain of the PMOS transistor existing in the output portion of the logic gate cell. Further, the logic gate cell has VDD and GND power supply wiring by the M1 wiring layer running in the first direction (lateral direction), and the input terminal and the output terminal exist in the M1 wiring layer. Further, since the power supply line runs in the first direction, the M2 wiring layer is inevitably used for the wiring running in the second direction (vertical direction) as the inter-terminal connection wiring of the logic gate cell.

Next, the standard cell layout will be described with reference to FIGS. 16 and 17. FIG. FIG. 16 is a diagram showing only a part extracted from the layout of a CMOS semiconductor integrated circuit according to the prior art, in which NAND2, NOR2, NOT of logic gate cells according to the prior art are arranged in a cell row and a part of wiring is applied. FIG. NOR2 and NAND2 are arranged in order from the left in the first cell column 31, NOR2 and NOT2 are arranged in order from the left in the second cell column 32, and NOT and NAND2 are arranged in the third cell column 33 in order from the left. Is arranged. In an actual semiconductor integrated circuit, the cell rows are much longer on the left and right than in FIG. 16, and the number of cell rows is much higher on the top and bottom. Note that the logic gate cells arranged in the third cell row 33 are arranged upside down. This is a technique for sharing a power supply line between logic gate cells in adjacent cell rows, and is sometimes called double back. Normally, the logic gate cells are arranged by inverting the second direction (vertical direction) of each cell row. In FIG. 16, the input terminal B of the first logic gate cell 41 is connected to the output terminal Y of the second logic gate cell 42. The output terminal Y of the second logic gate cell 42 is in the M1 wiring layer, and is connected to the M2 wiring 34 that travels in the second direction (vertical direction) via the M1M2 via hole 25 and further to the first via the M2M3 via hole 26. Connected to the M3 wiring 35 traveling in one direction (lateral direction), further connected to the short M2 wiring 36 via the M2M3 via hole 26, and finally connected to the terminal B of the first logic gate cell 41 via the M1M2 via hole 25. Connected to. The M3 wiring 35 passes three-dimensionally above the first logic gate cell 41 and the third logic gate cell 43 and does not have any direct contact with the internal wiring of the logic gate cells 41 and 43. The M2 wiring 34 passes three-dimensionally above the second logic gate cell 42, the fourth logic gate cell 44, the VDD and GND power supply lines, and has no contact with the internal wiring and power supply lines of the logic gate cell 44. do not have. The M2 wiring 34, the M3 wiring 35, and the M2 wiring 36 run on the wiring track of the wiring layer to which each belongs.

FIG. 17 is also a diagram showing only a part of the layout of a CMOS semiconductor integrated circuit according to the prior art, in which NAND2, NOR2, NOT of logic gate cells according to the prior art are arranged in a cell row and a part of wiring is applied. FIG. NAND2 and NOT2 are arranged in order from the left in the first cell row 31, NOT and NOR2 are arranged in order from the left in the second cell row 32, and NAND2 and NOR2 are arranged in the third cell row 33 in order from the left. Is arranged. In FIG. 17, the input terminal A of the first logic gate cell 41 is connected to the output terminal Y of the second logic gate cell 42. The output terminal Y of the second logic gate cell 42 is in the M1 wiring layer, and is connected to the M2 wiring 34 that travels in the second direction (vertical direction) via the M1M2 via hole 25 and further to the first via the M2M3 via hole 26. Connected to the M3 wiring 35 traveling in two directions (lateral directions), further connected to the short M2 wiring 36 via the M2M3 via hole 26, and finally connected to the terminal A of the first logic gate cell 41 via the M1M2 via hole 25. Connected to. The M3 wiring 35 passes three-dimensionally above the first logic gate cell 41 and does not have any direct contact with the internal wiring of the logic gate cell 41. Further, the M2 wiring 34 passes three-dimensionally above the second logic gate cell 42 and the VDD and GND power supply lines and does not have any contact with the power supply lines. The M2 wiring 34, the M3 wiring 35, and the M2 wiring 36 run on the wiring track of the wiring layer to which each belongs.

FIGS. 16 and 17 are layout examples of a CMOS semiconductor integrated circuit using logic gate cells according to the prior art, in which the first logic gate cell 41 and the second logic gate cell 42 are arranged close to each other. Normally, the logic gate cells are arranged so that the total wiring length of the connection wirings between the logic gate cells is not increased according to the interconnection state between the plurality of logic gate cells. There are many cases. In this case, the terminal of the logic gate cell to be connected, that is, the input terminal of the first logic gate cell 41 and the output terminal Y of the second logic gate cell 42 in FIGS. In general, the positions in one direction (lateral direction) and the second direction (vertical direction) are different from each other. Therefore, the connection between the terminals requires at least the M2 wiring in the second direction and the wiring in the first direction. At this time, it is apparent from FIGS. 16 and 17 that at least the M3 wiring 35 and the M2 wiring 36 are required to have the connection from the input terminal of the first logic gate cell 41 to the M2 wiring 34.
In general, upper layer wiring such as M3 wiring and further upper layer wiring, and, in some cases, M2 wiring, are used for long-distance inter-cell wiring between logic gate cells that had to be arranged far away, and logic gate cells arranged in proximity to each other It is important to use as little upper layer wiring as possible between the cells to reduce the wiring area, increase the density of logic gate cells, and reduce the layout area of the integrated circuit chip. However, in the layout using the logic gate cell according to the prior art, as shown in FIGS. 16 and 17, the M3 wiring 35 is simply connected to the M2 wiring 34 located at a close position from the input terminal of the first logic gate cell 41. M2 wiring 36 is required, and upper layer wiring resources that are desired to be used for long distance inter-cell wiring between logic gate cells located far away are consumed. Therefore, wiring congestion is likely to occur, and the density of logic gate cells is lowered. As a result, the area of the integrated circuit chip is increased, resulting in an increase in chip unit cost.

First, an outline of means for solving the problems will be described. Instead of the logic gate cell according to the prior art, the logic gate cell of the first structure in which the structure of the terminal is modified is used as the first logic gate cell, and the input terminal of the first logic gate cell and the output terminal of the second logic gate cell By arranging both of the logic gate cells at a position that serves as both a specific proximity position in the first direction (lateral direction) and a specific proximity position in the second direction (vertical direction), The output terminal can be connected only by one wiring in the second direction (vertical direction) by the second metal wiring layer (M2 wiring layer), one wiring by the first metal wiring layer (M1 wiring layer), and the via hole. And By this means, compared with the case where the logic gate cell according to the prior art is used, at least one wiring by the third metal wiring layer (M3 wiring layer) and one wiring by the second metal wiring layer (M2 wiring layer) are provided. Save use and increase the wiring resources available for long distance wiring.

Means for solving the problem will be described accurately.
A CMOS semiconductor integrated circuit designed by a standard cell method, wherein the CMOS semiconductor integrated circuit has a logic gate cell as a component, and the logic gate cell is composed of an interconnection of a PMOS transistor and an NMOS transistor and has one input terminal And the input terminal is electrically connected to each of the gate of the PMOS transistor and the gate of the NMOS transistor, and the output terminal is present in the output portion of the logic gate cell. VDD that is electrically connected to both the drain of the transistor and the drain of the NMOS transistor present in the output portion of the logic gate cell, and in which the logic gate cell runs in the first direction. And GND power supply wiring, and The input terminal is present in the first metal wiring layer, and the CMOS semiconductor integrated circuit is connected to the wiring composed of the second metal wiring layer as the inter-terminal connection wiring of the logic gate cell perpendicular to the first direction. It is assumed that it is used for wiring that runs in the second direction.
The presupposed CMOS semiconductor integrated circuit has the logic gate cell having the first structure as a constituent element. Here, the first structure includes an output wiring interconnecting the drain of the PMOS transistor existing in the output portion and the drain of the NMOS transistor existing in the output portion, and the entire output wiring or A part of which is a second layer output wiring composed of a second metal wiring layer, the second layer output wiring has the output terminal, and the second layer output wiring runs in the second direction. It is what. In addition, in the first structure, when there are a plurality of input terminals, each of the plurality of input terminals exists at a different position in the second direction. In addition, the first structure means that the logic gate cell does not come into contact with any wiring in the logic gate cell when a temporary wiring of the first metal wiring layer is extended from each of the input terminals in the first direction. The temporary wiring has a spatial structure that can reach the boundary of the first layer and has a positional relationship in which all of the temporary wirings three-dimensionally intersect with the second layer output wiring. In addition, the first structure accommodates a passing wiring composed of a first metal wiring layer that travels in the first direction in the logic gate cell and does not contact any wiring in the logic gate cell. It has a possible spatial structure, and the passing wiring has a positional relationship that three-dimensionally intersects with the second layer output wiring.
Further, the presupposed CMOS semiconductor integrated circuit has a first logic gate cell and a first wiring as components. Here, the first logic gate cell has the first structure, and the first wiring is a wiring composed of a second metal wiring layer that travels in the second direction, and further includes the first wiring. And the first logic gate cell are present at close positions in the first direction. The proximity position in the first direction means that no logic gate cell exists between the first logic gate cell and the first wiring in the first cell row where the first logic gate cell exists, or Only the logic gate cell having the first structure exists between the first logic gate cell and the first wiring. Furthermore, the presupposed CMOS semiconductor integrated circuit has the following structure. That is, the input terminal of the first logic gate cell and the first wiring are connected only by the second wiring constituted by the first metal wiring layer and only one first layer second interlayer via hole. Has a structure.
By this means, at least a third metal is used to connect the first logic gate cell and the first wiring existing in the proximity position in the first direction as compared with the case where the logic gate cell according to the prior art is used. The use of one wiring by the wiring layer and one wiring by the second metal wiring layer is saved, and the available wiring resources of the third and second metal wiring layers that can be used for long-distance wiring are increased.

Further, means for solving the problem will be additionally described.
In addition to the above, the presupposed CMOS semiconductor integrated circuit further includes a second logic gate cell as a component, and the first cell row in which the first logic gate cell exists and the second logic gate cell exist. It is assumed that the second cell row is in the proximity position in the second direction. Here, the proximity position in the second direction refers to the second cell row and the first cell row, where X is the position in the first direction where the output terminal of the second logic gate cell exists. Or no logic gate cell having an output terminal at the position X in the cell column between the second cell column and the first cell column. Furthermore, the presupposed CMOS semiconductor integrated circuit has the following structure. That is, the first wiring is directly connected to the output terminal of the second logic gate cell or is connected only through one first layer second interlayer via hole, and with this, the second logic gate cell of the second logic gate cell An output terminal and the input terminal of the first logic gate cell are connected only to the first wiring, the second wiring, and the first layer second interlayer via hole.
By this means, the first logic gate cell and the second logic gate at a position having both the proximity position in the first direction and the proximity position in the second direction compared to the case where the logic gate cell according to the prior art is used. Third and second metals that can be used for long-distance wiring, saving the use of at least one wiring with a third metal wiring layer and one wiring with a second metal wiring layer to connect the gate cell terminals together Increase available wiring resources in the wiring layer.

According to the present invention, the wiring resources of the third metal wiring layer and the second metal wiring layer can be saved when wiring connection is performed between logic gate cells at specific proximity positions, and can be used for long-distance wiring. Increase the wiring resources. As a result, even when the packing density of logic gate cells is set higher than before, it is possible to increase the possibility of completing long-distance wiring connections, thereby reducing the layout area of the integrated circuit chip and lowering the unit cost of the chip. Contribute to it.

First, a CMOS semiconductor integrated circuit which is a precondition will be described.
A CMOS semiconductor integrated circuit designed by a standard cell method, wherein the CMOS semiconductor integrated circuit has a logic gate cell as a component, and the logic gate cell is composed of an interconnection of a PMOS transistor and an NMOS transistor and has one input terminal Output terminal. The input terminal has an electrical connection to each of the gate of the PMOS transistor and the gate of the NMOS transistor, and the output terminal has a drain of the PMOS transistor and an output of the logic gate cell present in the output portion of the logic gate cell. Both of the drains of the NMOS transistor existing in the output portion have electrical connection. Further, the logic gate cell has VDD and GND power supply wiring by a first metal wiring layer running in the first direction, and the input terminal exists in the first metal wiring layer. Further, the CMOS semiconductor integrated circuit uses a wiring composed of a second metal wiring layer as a wiring between terminals of the logic gate cell as a wiring running in a second direction perpendicular to the first direction.
The CMOS semiconductor integrated circuit, which is the above precondition, will be described in more detail although it is repeated. In the CMOS semiconductor integrated circuit, a desired circuit is formed by interconnecting a PMOS transistor and an NMOS transistor, and all the transistors included in the desired circuit and wiring for interconnecting them are integrated on one integrated circuit chip. It is a thing. Examples of layouts using the logic gate cell and standard cell system, which are components of the CMOS semiconductor integrated circuit, are as described in detail in the section of “Background Art”, but will be briefly described again.
An example of the logic gate cell will be described with reference to FIG. FIG. 13A shows a layout structure according to the prior art of the logic gate cell NAND2, and FIG. 13B shows the diffusion layer and the polysilicon wiring layer 3 extracted from FIG. 13A. FIG. 13C shows the first metal wiring layer and contact holes extracted. The logic gate cell is formed by interconnecting PMOS transistors 4 and 5 and NMOS transistors 6 and 7 and has input terminals A and B and one output terminal Y. The input terminal A is electrically connected to the gate of the PMOS transistor 4 and the gate of the NMOS transistor 6 through the polysilicon wiring 3. The input terminal B has an electrical connection to each of the gate of the PMOS transistor 5 and the gate of the NMOS transistor 7. Further, the output terminal Y is electrically connected to both the drains of the PMOS transistors 4 and 5 existing in the output part of the logic gate cell and the drain of the NMOS transistor 7 existing in the output part of the logic gate cell. It is. Further, the logic gate cell has VDD and GND power supply wirings by a first metal wiring layer running in the first direction. The input terminals A and B are present in the first metal wiring layer. As a precondition of the present invention, the number of input terminals of the logic gate cell and the number of PMOS transistors and NMOS transistors are not limited.
In addition, the CMOS semiconductor integrated circuit uses a wiring composed of a second metal wiring layer as a wiring between terminals of the logic gate cell as a wiring that runs in a second direction perpendicular to the first direction. This is inevitably derived from the fact that the VDD and GND power supply lines are formed of the first metal wiring layer and run in the first direction in the logic gate cell.
An example of the layout by the standard cell system is as shown in FIGS. These figures are examples of using logic gate cells according to the prior art as constituent elements, and details are as described in the section “Background Art”.

Next, preferred embodiments for carrying out the invention will be described with reference to the drawings.
The CMOS semiconductor integrated circuit has the logic gate cell having the first structure as a constituent element. The first structure will be described with reference to the drawings. FIG. 3A is a layout diagram of a logic gate cell forming a part of the embodiment of the present invention, and the logic function is NAND2. The logic symbol of NAND2 and the circuit diagram of the transistor level are as shown in FIG. FIG. 3B shows the diffusion layers 1 and 2 and the polysilicon wiring layer 3 extracted from FIG. 3A, and FIG. 13C shows the first metal wiring layer and the contact hole extracted. FIG. 3D shows the second metal wiring layer and the first layer second interlayer via hole 25 extracted. As the first structure, output wirings 24 and 22 interconnecting the drains of the PMOS transistors 4 and 5 existing in the output portion of the logic gate cell and the drain of the NMOS transistor 7 existing in the output portion are provided. And all or a part of the output wiring is a second layer output wiring 22 composed of a second metal wiring layer, and the second layer output wiring 22 has the output terminal Y, and The second layer output wiring 22 runs in the second direction. Further, as the first structure, when there are a plurality of input terminals, each of the plurality of input terminals A and B exists at different positions in the second direction. Next, FIG. 4 is obtained by adding temporary wiring 51 by the first metal wiring layer to FIG. As the first structure, as shown in FIG. 4, when the temporary wiring 51 by the first metal wiring layer is extended from each of the input terminals A and B in the first direction, any of the logic gate cells It has a spatial structure that can reach the boundary of the logic gate cell without coming into contact with the wiring, and all of the temporary wirings 51 have a positional relationship that three-dimensionally intersects with the second layer output wiring 22. ing. The broken lines in FIGS. 3 and 4 indicate the boundaries of the logic gate cells and are called cell frames. Next, FIG. 5 is obtained by adding the passing wiring 52 by the first metal wiring layer to FIG. As shown in FIG. 5, the first structure further includes a first metal wiring layer that travels in the first direction in the logic gate cell and does not contact any wiring in the logic gate cell. It has a spatial structure that can accommodate the wiring 52, and the passing wiring 52 has a positional relationship that three-dimensionally intersects with the second layer output wiring 22.

Next, FIG. 1 and FIG. 2 are layout diagrams showing an embodiment of the present invention, which corresponds to a part extracted from the layout of the CMOS semiconductor integrated circuit, and NAND2, NOR2, A form in which NOT is arranged in a cell row and a part of wiring is applied is shown. In FIG. 1, NOR2 according to the present invention and NAND2 according to the present invention are arranged in order from the left in the first cell row 61, and NOR2 and NOT according to the prior art are arranged in order from the left in the second cell row 62. In the third cell row 63, NOT and NAND2 according to the prior art are arranged in order from the left. In FIG. 2, NAND2 and NOT2 are arranged in order from the left in the first cell row 61, NOT and NOR2 are arranged in order from the left in the second cell row 62, and from the left in the third cell row 63. NAND2 and NOR2 are arranged in order, and all the logic gate cells are according to the present invention. The CMOS semiconductor integrated circuit further includes a first logic gate cell 71 and a first wiring 64 as constituent elements as shown in FIGS. 1 and 2, and the first logic gate cell 71 includes the first logic gate cell 71. The first wiring 64 having a structure is a wiring composed of a second metal wiring layer that travels in the second direction. Further, the first wiring 64 and the first logic gate cell 71 are present in close proximity in the first direction. The proximity position in the first direction refers to a position between the first logic gate cell 71 and the first wiring 64 in the first cell row 61 where the first logic gate cell 71 exists as shown in FIG. 1, or only the logic gate cell having the first structure between the first logic gate cell 71 and the first wiring 64 as shown in FIG. 1 (FIG. 1 shows a logic gate cell). There is an example in which 73 is only one).
Further, in the CMOS semiconductor integrated circuit, the input terminal (the input terminal B in FIG. 1 and the input terminal A in FIG. 2) of the first logic gate cell 71 and the first wiring 64 are arranged in a first metal wiring layer. The second wiring 65 configured as described above and only one first layer second interlayer via hole 25 are connected.
According to the above embodiment, for example, the first logic gate cell 71 and the first logic gate cell located in the proximity positions in the first direction are compared with the case where the conventional logic gate cell shown in FIGS. 16 and 17 is used. The third and second metal wirings can be used for long-distance wiring by saving the use of at least one wiring by the third metal wiring layer and one wiring by the second metal wiring layer to connect the wiring 64 of Increase the available wiring resources of the layer.
Here, a supplementary explanation will be made about the proximity position in the first direction. For the logic gate cell 73 in FIG. 1, the wiring 65 is the passing wiring 52 described with reference to FIG. In FIG. 1, a plurality of logic gate cells 73 may be arranged side by side in the first direction instead of one, and in this case, the wiring 65 is arranged inside the logic gate cells 73 existing in the plurality as a passing wiring. Will pass. Here, the maximum number of logic gate cells 73 that are arranged side by side is the maximum number, and the upper limit number is based on the number of passing wirings that can pass through the logic gate cell 73. For example, if the logic gate cell 73 is NAND2, the number of passing wirings that can pass through the cell is two as shown in FIG. This is a consideration for facilitating wiring connection when a plurality of different pairs of first logic gate cells 71 and first wirings 64 exist in the same cell column.

Further, a preferred embodiment for carrying out the invention will be additionally described with reference to FIGS.
The semiconductor integrated circuit further includes a second logic gate cell 72 as a component, and the first cell row 61 where the first logic gate cell 71 exists and the second logic gate cell 72 where the second logic gate cell 72 exists. The cell row 62 exists in the proximity position in the second direction. Here, the proximity position in the second direction means that the position in the first direction where the output terminal Y of the second logic gate cell 72 exists is X, and the second cell row 62 and the first direction. There is no cell column between the cell column 61 or a cell column between the second cell column 61 and the first cell column 62 (in the example of FIGS. 1 and 2, the cell column 63 is 1). 2), there is no logic gate cell whose output terminal is located at the position X. At this time, the first wiring 64 is directly connected to the output terminal Y of the second logic gate cell 72 (FIG. 2). In the case of FIG. 1) or connected via only one first layer / second interlayer via hole 25 (in the case of FIG. 1). With this structure, the output terminal Y of the second logic gate cell 72 and the input terminal (B in FIG. 1 and A in FIG. 2) of the first logic gate cell 71 are connected to the first wiring 64 and the second logic gate cell 72. These wirings 65 are connected only by the first layer second interlayer via hole 25.
According to the above embodiment, for example, the proximity position in the first direction and the proximity position in the second direction are combined as compared with the case where the logic gate cell according to the prior art shown in FIGS. 16 and 17 is used. The connection between the terminals of the first logic gate cell 71 and the second logic gate cell 72 saves the use of at least one wiring by the third metal wiring layer and one wiring by the second metal wiring layer. In addition, the available wiring resources of the third and second metal wiring layers that can be used for long-distance wiring are increased.
Here, a supplementary explanation will be made about the proximity position in the second direction. When the position in the first direction where the output terminal Y of the second logic gate cell 72 exists is X, there is a cell column 63 between the second cell column 61 and the first cell column 62. Usually, a logic gate cell is arranged there. For example, if the logic gate cell 74 of FIG. 1 is in the cell row 63 and the position of the output terminal Y of the logic gate cell 74 overlaps the position X, the wiring 64 covers the output terminal Y and covers the output terminal Y. Difficult to connect different wiring to If the output terminal Y of the logic gate cell 74 is in the second metal wiring layer and its position overlaps the position X, this time, the wiring 64 is prevented from traveling. For this reason, the cell row 63 must not have a logic gate cell whose output terminal is at the position X. Here, the number of cell rows 63 may be plural, but there is a guide for the upper limit number. That is, 1 minus the average cell width of the logic gate cells placed in the cell row 63, that is, 1 minus the number of wirings (number of wiring tracks) that can pass in the second direction above the cell with respect to the width in the first direction of the logic gate cells. Given. For example, if NAND2 in FIG. 13 has a width of 4, NOR2 in FIG. 14 has a width of 4, and NOT in FIG. 15 has a width of 3 and only these appear uniformly, the average of the width is about 4, The guideline for the upper limit number is 4 by 1 minus 3. If this is exceeded, it is probabilistically difficult to satisfy the above-mentioned condition that “the logic gate cell whose output terminal is at the position X must not exist”.

The first wiring 64 in FIG. 1 passes three-dimensionally above the second logic gate cell 72, the logic gate cell 74, the VDD and GND power supply lines, and the internal wiring and power supply lines of the logic gate cell 74 Has no contact at all. Further, the second wiring 65 in FIG. 1 is three-dimensional with both the second layer output wiring 22 of the first logic gate cell 71 and the second layer output wiring 22 of the logic gate cell 73 having the first structure. Intersects. Further, the first wiring 64 in FIG. 2 passes three-dimensionally above the second logic gate cell 72, VDD, and GND power supply line, and has no contact with the power supply line. Further, the second wiring 65 in FIG. 2 crosses the second layer output wiring 22 of the first logic gate cell 71 in three dimensions. The first wiring 64 runs on a wiring track in the second metal wiring layer in both FIG. 1 and FIG. In FIG. 2, the second wiring 65 travels in the first direction on the wiring track in the first metal wiring layer. In FIG. 1, the second wiring 65 mainly travels on the wiring track in the first metal wiring layer in the first direction. In this example, there is a short bend called a jog where it is connected to the input terminal B of the logic gate cell 61.
1 and 2 used in the description as an embodiment show an example of the layout of a very narrow region of the CMOS semiconductor integrated circuit, and the logic gate cells shown in the drawing are NAND2, NOR2. However, in the present invention, the terminal structure of the logic gate cell is mainly defined as the first structure, and the logic function of the logic gate cell is not limited.

FIG. 6 shows a first embodiment of the logic gate cell having the first structure, which forms part of the present invention. FIG. 6 differs from FIG. 3 taken up in the embodiment in the shape (terminal shape) of the first metal wiring layer of the input terminals A and B. That is, only the points that are longer in the first direction (lateral direction) than the case of FIG. 3 are different, but there is no other difference. If the terminal shape is changed by a CAD tool that performs automatic placement and routing, the wiring connection may be made better.

FIG. 7 shows a second embodiment of the logic gate cell having the first structure, which forms part of the present invention. The logic function of the logic gate cell of FIG. 7 is NOR2, and a logic symbol and a transistor level circuit diagram are as shown in FIG. NAND2 and NOR2 are just the opposite way of using PMOS transistors and NMOS transistors, and the wiring configuration is also upside down with respect to NAND2 in FIG. FIG. 7 is a layout diagram, and a description method (ground pattern in the drawing) of the diffusion layers 1 and 2, the polysilicon wiring layer, the first metal wiring layer, and the second metal wiring layer in FIG. 7 is shown in FIG. Follow. NOR2 in FIG. 7 appears in FIGS. 1 and 2 showing the embodiment.
FIG. 7 shows a logic gate cell which is a constituent element of a CMOS semiconductor integrated circuit designed by the standard cell method, and includes the following as prerequisite constituent requirements. That is, the logic gate cell is composed of an interconnection of a PMOS transistor and an NMOS transistor, and has an input terminal and one output terminal Y. The input terminal has an electrical connection between the gate of the PMOS transistor and the gate of the NMOS transistor. Further, the output terminal Y has an electrical connection to both the drain of the PMOS transistor present in the output portion of the logic gate cell and the drain of the NMOS transistor present in the output portion of the logic gate cell. Further, the logic gate cell has VDD and GND power supply wiring by a first metal wiring layer running in the first direction. The input terminal is present in the first metal wiring layer. Since the above configuration is common to all the following embodiments, the description is omitted below.
Next, the logic gate cell of FIG. 7 has the following structure as the first structure. That is, an output wiring interconnecting the drain of the PMOS transistor present in the output portion of the logic gate cell and the drain of the NMOS transistor present in the output portion, and all or part of the output wiring Is a second layer output wiring 22 composed of a second metal wiring layer, the second layer output wiring 22 has the output terminal Y, and the second layer output wiring 22 is in the second direction. Running. Further, when there are a plurality of the input terminals, each of the plurality of input terminals exists at a different position in the second direction. Next, when a temporary wiring of the first metal wiring layer is extended from each of the input terminals in the first direction, a space that can reach the boundary of the logic gate cell without contacting any wiring in the logic gate cell. Each of the temporary wirings has a positional relationship in which the second-layer output wirings 22 intersect three-dimensionally. The broken lines in the figure indicate the boundaries of the logic gate cells and are called cell frames. Next, it has a spatial structure capable of accommodating a passing wiring composed of a first metal wiring layer that travels in the first direction in the logic gate cell and does not contact any wiring in the logic gate cell. In addition, the passing wiring has a positional relationship that three-dimensionally intersects with the second layer output wiring 22. Since the above configuration is also common to all the following embodiments, description thereof is omitted below.

FIG. 8 shows a third embodiment of the logic gate cell having the first structure, which forms part of the present invention. The logic function of the logic gate cell of FIG. 8 is NOT, and a logic symbol and a transistor level circuit diagram are as shown in FIG. FIG. 8 is a layout diagram, and a description method (ground pattern in the drawing) of the diffusion layers 1 and 2, the polysilicon wiring layer, the first metal wiring layer, and the second metal wiring layer in FIG. 8 is shown in FIG. Follow. The logic gate cell of FIG. 8 appears in FIG. 2 showing the embodiment. NOT differs from the other embodiments in that it has one input terminal. Since the number of input terminals is small, the number of through wirings that can pass through the logic gate cell is large.

FIG. 9 shows a fourth embodiment of the logic gate cell having the first structure, which forms part of the present invention. The logic function of the logic gate cell of FIG. 9 is NAND3, and the logic symbols are as shown in FIG. 9A is a layout diagram of the entire NAND 3, FIG. 9B is a diagram in which the diffusion layers 1 and 2 and the polysilicon wiring layer are extracted from FIG. 9A, and FIG. The first metal wiring layer and the contact hole are extracted from FIG. 9A, and FIG. 9D is the second metal wiring layer and the via hole extracted from FIG. 9A. The description method (ground pattern in the drawing) of the diffusion layers 1 and 2, the polysilicon wiring layer, the first metal wiring layer, and the second metal wiring layer in FIG. 9 is the same as FIG.
NAND3 has three input terminals. Since the number of input terminals is large, the number of passing wirings that can pass through the logic gate cell is limited to one.

FIG. 10 shows a fifth embodiment of the logic gate cell having the first structure, which forms part of the present invention. The logic function of the logic gate cell of FIG. 10 is NOR3, and the logic symbols are as shown in FIG. In NAND3 and NOR3, the usage of the PMOS transistor and the NMOS transistor is exactly opposite, and the form of wiring is also upside down with respect to NAND2 in FIG. FIG. 10 is a layout diagram, and a description method (ground pattern in the drawing) of the diffusion layers 1 and 2, the polysilicon wiring layer, the first metal wiring layer, and the second metal wiring layer in FIG. 10 is shown in FIG. Follow.
NOR3 has three input terminals. Since the number of input terminals is large, the number of passing wirings that can pass through the logic gate cell is limited to one.

FIG. 11 shows a sixth embodiment of the logic gate cell having the first structure, which forms a part of the present invention. The logic function of the logic gate cell of FIG. 11 is AND2, and the logic symbols are as shown in FIG. The internal configuration of AND2 is obtained by connecting NOT to the output of NAND2. 11A is a layout diagram of the entire AND2, FIG. 11B is a diagram in which the diffusion layers 1 and 2 and the polysilicon wiring layer 3 are extracted from FIG. 11A, and FIG. FIG. 11A shows the first metal wiring layer and the contact hole extracted, and FIG. 11D shows the second metal wiring layer and the via hole extracted from 11A. The description method (ground pattern in the drawing) of the diffusion layers 1 and 2, the polysilicon wiring layer 3, the first metal wiring layer, and the second metal wiring layer in FIG. 11 is the same as FIG.
11 requires a wiring 23 for connecting the PMOS transistor and the NMOS transistor at the output of the internal NAND2. Since the use of the first metal wiring layer does not meet the structural requirements of the first structure, the polysilicon wiring 3 which is the NOT input wiring inside the AND 2 is also used as the wiring 23 here. This prevents the temporary wiring extending from the input terminals A and B in the first direction and the passing wiring passing through the logic gate cell in the first direction from being blocked. In AND2 of FIG. 11, there is one passing wiring that can pass through the logic gate cell.

FIG. 12 shows a seventh embodiment of the logic gate cell having the first structure, which forms part of the present invention. The logic function of the logic gate cell of FIG. 12 is OR21, and the logic symbols are as shown in FIG. The internal configuration of OR21 is such that one input of NAND2 is connected to the output of NOT. 12A is a layout diagram of the entire OR 21. FIG. 12B is a diagram in which the diffusion layers 1 and 2 and the polysilicon wiring layer 3 are extracted from FIG. 12A, and FIG. FIG. 12 (a) shows the first metal wiring layer and contact hole extracted, and FIG. 12 (d) shows the second metal wiring layer and via hole extracted from 12 (a). The description method (ground pattern in the drawing) of the diffusion layers 1 and 2, the polysilicon wiring layer 3, the first metal wiring layer, and the second metal wiring layer in FIG. 12 is the same as FIG.
The OR 21 in FIG. 12 requires the wiring 23 for connecting the PMOS transistor and the NMOS transistor at the output of the internal NOT, as in the case of AND2. Since the use of the first wiring layer does not meet the structural requirements of the first structure, the polysilicon wiring 3 that is the input wiring of the NAND 2 inside the OR 21 is also used as the wiring 23 here. This prevents the temporary wiring extending from the input terminals A and B in the first direction and the passing wiring passing through the logic gate cell in the first direction from being blocked. In the OR 21 of FIG. 12, there is one passing wiring that can pass through the logic gate cell.

The present invention is applied to a CMOS semiconductor integrated circuit and has the effect of increasing the wiring resources as compared with the prior art, and increases the possibility that the logic gate cells can be arranged at a high density, thereby reducing the layout area of the integrated circuit chip and the chip unit price. Helps reduce

1 is a layout diagram of a CMOS semiconductor integrated circuit according to the present invention. (Embodiment) 1 is a layout diagram of a CMOS semiconductor integrated circuit according to the present invention. (Embodiment) FIG. 4 is a layout diagram of a logic gate cell according to the present invention. (Part of the embodiment) FIG. 4 is a layout diagram of a logic gate cell according to the present invention. (Part of the embodiment) FIG. 4 is a layout diagram of a logic gate cell according to the present invention. (Part of the embodiment) FIG. 4 is a layout diagram of a logic gate cell according to the present invention. Example 1 FIG. 4 is a layout diagram of a logic gate cell according to the present invention. (Example 2) FIG. 4 is a layout diagram of a logic gate cell according to the present invention. (Example 3) FIG. 4 is a layout diagram of a logic gate cell according to the present invention. (Example 4) FIG. 4 is a layout diagram of a logic gate cell according to the present invention. (Example 5) FIG. 4 is a layout diagram of a logic gate cell according to the present invention. (Example 6) FIG. 4 is a layout diagram of a logic gate cell according to the present invention. (Example 7) It is a layout diagram of a logic gate cell according to the prior art. It is a layout diagram of a logic gate cell according to the prior art. It is a layout diagram of a logic gate cell according to the prior art. It is a layout diagram of a CMOS semiconductor integrated circuit according to the prior art. It is a layout diagram of a CMOS semiconductor integrated circuit according to the prior art. It is a circuit diagram of a logic symbol and a transistor level of a logic gate. It is a circuit diagram of a logic symbol and a transistor level of a logic gate. It is a circuit diagram of a logic symbol and a transistor level of a logic gate. A logic symbol of a logic gate. It is the logic circuit diagram and logic symbol of a logic gate. It is the logic circuit diagram and logic symbol of a logic gate.

Explanation of symbols

1, 2 Diffusion layer 3 Polysilicon wiring layer 4, 5 PMOS transistor 6, 7 NMOS transistor 11, 12, 13, 14, 21, 22, 23, 24 Wiring 25, 26 Via holes 31, 32, 33, 61, 62, 63 Cell row 34, 35, 36, 51, 52, 64, 65 Wiring 41, 42, 43, 44, 71, 72, 73, 74 Logic gate cells

Claims (2)

A CMOS semiconductor integrated circuit designed by a standard cell method, wherein the CMOS semiconductor integrated circuit has a logic gate cell as a component, and the logic gate cell is composed of an interconnection of a PMOS transistor and an NMOS transistor and has one input terminal And the input terminal is electrically connected to each of the gate of the PMOS transistor and the gate of the NMOS transistor, and the output terminal is present in the output portion of the logic gate cell. VDD that is electrically connected to both the drain of the transistor and the drain of the NMOS transistor present in the output portion of the logic gate cell, and in which the logic gate cell runs in the first direction. And GND power supply wiring, and The input terminal is present in the first metal wiring layer, and the CMOS semiconductor integrated circuit is connected to the wiring composed of the second metal wiring layer as the inter-terminal connection wiring of the logic gate cell perpendicular to the first direction. In what is used for wiring that runs in the second direction of orientation,
The logic gate cell having a first structure as a constituent element, and the first structure as a drain of the PMOS transistor present in the output portion and the drain of the NMOS transistor present in the output portion Output wiring interconnecting the output wiring, and all or part of the output wiring is a second layer output wiring composed of a second metal wiring layer, and the second layer output wiring has the output terminal. In addition, when the second layer output wiring runs in the second direction, and the first structure has a plurality of input terminals, each of the plurality of input terminals is in the second direction. The logic gate cell is located at a position different from each other, and when the temporary wiring of the first metal wiring layer is extended from each of the input terminals in the first direction as the first structure. A position having a spatial structure that can reach the boundary of the logic gate cell without contacting any of the wirings, and where all of the temporary wirings three-dimensionally intersect with the second layer output wiring In addition, the first structure includes a first metal wiring layer that travels in the first direction in the logic gate cell and does not contact any wiring in the logic gate cell. It has a spatial structure capable of accommodating a passage wiring, and the passage wiring has a positional relationship that three-dimensionally intersects with the second layer output wiring,
In addition, a first logic gate cell and a first wiring are included as components, and the first logic gate cell has the first structure and the first wiring travels in the second direction. A wiring composed of a metal wiring layer, wherein the first wiring and the first logic gate cell are present in a proximity position in a first direction, and the proximity position in the first direction is the first There is no logic gate cell between the first logic gate cell and the first wiring in the first cell column in which the logic gate cell exists, or the first logic gate cell and the first wiring There are only logic gate cells having the first structure in between, and at this time, the input terminal of the first logic gate cell and the first wiring are constituted by a first metal wiring layer. Second wiring and only one first The second and second metal layers without the use of a third and second metal wiring layer for the second wiring. A CMOS semiconductor integrated circuit having increased available wiring resources in the wiring layer. A second logic gate cell is included as a component, and the first cell row in which the first logic gate cell exists and the second cell row in which the second logic gate cell exists are in close proximity in the second direction. Yes, the proximity position in the second direction refers to the second cell row and the first cell row, where X is the position in the first direction where the output terminal of the second logic gate cell exists. A cell row does not exist between the second cell row and the first cell row, and a logic gate cell having an output terminal at the position X does not exist in the cell row between the second cell row and the first cell row. In this case, the first wiring has a structure that is directly connected to the output terminal of the second logic gate cell or is connected only through one first layer second interlayer via hole. The output terminal of the second logic gate cell; 2. The CMOS semiconductor integrated circuit according to claim 1, wherein the input terminal of the first logic gate cell is connected only by the first wiring, the second wiring, and the first layer second interlayer via hole.

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