JP2009270912A - Semiconductor integrated circuit and inspection method of semiconductor integrated circuit - Google Patents

Abstract

A semiconductor integrated circuit capable of reducing an inspection time while suppressing an increase in external terminals as much as possible when data for inspection is serially input from the outside.
A 3V power supply is supplied to a circuit under test 4 from the outside via a power input terminal 12 and a 5V power is supplied to the circuit under test 5 via a power input terminal 13. Then, the inspection circuit unit 5 converts the data serially input in synchronization with the clock through the inspection data input terminal 10 to parallel, and converts the level of the converted inspection data by the level shift circuit 9 to inspect the circuit to be inspected. Part 4 is given.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit including a test circuit unit that converts data serially input from the outside in synchronization with a clock into parallel and outputs test data to the circuit unit to be tested, and a method for testing the semiconductor integrated circuit About.

  With respect to semiconductor integrated circuits, the circuit scale tends to increase as the number of functions increases, and it takes time to inspect all the functions of each circuit. When the function test data is serially input from the outside, the test time can be shortened by increasing the number of test data input terminals to test each part in parallel. However, when the number of external terminals for inspection increases, the package size of the semiconductor integrated circuit increases. Since semiconductor integrated circuits are constantly required to be miniaturized as well as multifunctional, there is a trade-off between shortening the inspection time and miniaturizing the package.

As a conventional technique related to the inspection of the semiconductor integrated circuit as described above, for example, there is one disclosed in Patent Document 1. In Patent Document 1, an operation margin of the self-inspection circuit is ensured by allowing a power supply voltage higher than that of the circuit to be measured to be supplied to the built-in self-inspection circuit.
JP 2003-37174 A

  However, in the semiconductor integrated circuit disclosed in Patent Document 1, the test data is not input from the outside, and the self-test circuit automatically generates a test signal when the power is turned on. Therefore, in the configuration of Patent Document 1, it does not matter that the number of external terminals for inspection increases, but the inspection patterns that can be executed are limited. If the number of inspection patterns is increased, the amount of inspection data held inside increases. For example, in the case of a multi-chip configuration in which a plurality of IC chips are mounted, self-inspection corresponding to each chip is performed. If a circuit is added, the circuit scale itself increases.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit and a semiconductor capable of shortening the inspection time while suppressing the increase in the number of external terminals as much as possible when serially inputting inspection data from the outside. An object of the present invention is to provide an integrated circuit inspection method.

  According to the semiconductor integrated circuit of the first aspect, the inspection circuit unit converts the data input serially in synchronization with the clock via the inspection data input terminal into parallel and outputs the parallel data to the circuit under test. In this case, power is supplied from the outside to the circuit portion to be inspected via the first power supply terminal, and the power supply voltage supplied to the circuit portion to be inspected is supplied to the circuit portion to be inspected via the second power supply terminal. High voltage power is supplied. Then, the inspection data is level-converted by the level shift circuit and given to the circuit portion to be inspected.

That is, since a power supply having a voltage higher than that of the circuit portion to be inspected is supplied to the inspection circuit portion, each element constituting the inspection circuit portion can operate at a higher speed. Therefore, since the time for serially inputting the inspection data can be shortened by increasing the frequency of the synchronous clock applied from the outside, the number of inspection data input terminals is reduced and the number of bits of data input serially from one terminal is increased. In this case, the inspection can be performed in a short time, and the increase in the number of external terminals can be suppressed and the package size can be reduced.
Since the frequency of using the test circuit unit is extremely low compared to the circuit unit to be tested, there is no functional problem even if stress is applied by applying a higher power supply voltage. Since the circuit portion to be inspected that is frequently used does not have such an influence, the reliability is not lowered.

  According to the semiconductor integrated circuit of the second aspect, the present invention is applied to a case where the circuit portion to be inspected is a plurality of IC chips. That is, in the case of a multi-chip configuration, it is necessary to perform functional inspection for more items, and the overall inspection time is also prolonged. Therefore, the application of the present invention is preferable because the inspection can be performed in a short time while suppressing the increase in the number of external terminals.

  According to the semiconductor integrated circuit of the third aspect, since the test circuit unit is shared by a plurality of IC chips, it is not necessary to provide the same number of test circuit units as the IC chips, and the entire semiconductor integrated circuit is configured in a small size. it can.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram showing a part related to the gist of the configuration of the semiconductor integrated circuit of the present embodiment. The multichip module 1 (semiconductor integrated circuit) includes, for example, two IC chips 2 and 3. The IC chip 2 includes a circuit part to be inspected 4 and an inspection circuit part 5. The circuit under test 4 has, for example, a 4-bit shift register 7 (1, 2) configured by serially connecting four flip-flops 6 and 4-bit data output from the shift register 7 (1, 2). And a level shift circuit 9 for level-shifting the output data of the latch circuit 8 and outputting it to the circuit section 4 to be tested.
The D input terminal of the first stage flip-flop 6 constituting the shift register 7 (1, 2) is connected to the test data input terminal 10 (1, 2) which is an external terminal of the multichip module 1. The clock terminal CLK of each flip-flop 6 is connected to the clock input terminal 11 which is the same external terminal.

The multichip module 1 includes two power input terminals 12 and 13 (first and second power terminals). The power input terminals 12 and 13 receive power V1 and V2 supplied from the outside. , And supplied independently to the circuit portion to be inspected 4 and the inspection circuit portion 5. The circuit under test 4 operates with a power supply voltage of 3V, for example, and the test circuit section 5 operates with a power supply voltage of 5V, for example. Therefore, the level shift circuit 9 converts the high level of the data output from the inspection circuit unit 5 to the circuit part 4 to be inspected from 5V to 3V.
The IC chip 3 has only a configuration corresponding to the circuit part 4 to be inspected, and the 8-bit data bus output from the level shift circuit 9 is also connected to the IC chip 3.

Next, the operation of this embodiment will be described with reference to FIG. When the multichip module 1 operates normally, the power input terminal 12 is supplied with 3V power V1. When inspecting the circuit part 4 to be inspected, the power source input terminal 13 is supplied with a 5 V power source V1 to operate the inspection circuit part 5.
At this time, when a serial clock signal (for example, a frequency of about several MHz to several tens MHz) is input from the clock input terminal 11 and the inspection data is input serially in synchronization with the clock signal, the shift register 7 The serial data is converted to parallel. The latch circuit 8 is a serial / parallel converted data in the shift register 7 in accordance with a latch signal given when the input of serial data is completed by a control circuit (not shown) counting the number of pulse inputs of the clock signal, for example. Latch. The latched data is output to the circuit under test 4 via the level shift circuit 9, and the function of the circuit under test 4 is inspected by the inspection data.

In this case, since the test circuit unit 5 is supplied with the power supply V2 having a voltage higher than that of the circuit unit 4 to be tested, the test circuit unit 5 can operate at high speed, and can quickly perform the serial / parallel conversion processing in the shift register 7. . In general, a logic circuit operates at a higher speed because a signal propagation delay time becomes shorter as a power supply voltage becomes higher. Therefore, in FIG. 1, the shift register 7 is shown in a 4-bit configuration for the sake of illustration, but it may be configured in a larger scale of 8 bits, 16 bits, or more.
If the inspection data can be input in a short time, the shift register 7 can be enlarged as described above, so that the number of inspection data input terminals 10 can be reduced.

  Here, for comparison, FIG. 2 shows a conventional example of a configuration in which inspection data is serially input from the outside as in the multichip module 1. In the conventional multichip module 21, the power supplied to the circuit under test 22 and the circuit under test 23 is common, and if the operating voltage of the circuit under test 22 is 3V by one power input terminal 12, then 3V. Power is supplied. Then, since the operation speed of the shift register 24 does not increase, the only way to perform the inspection in a short time is to configure the shift register 24 on a small scale (2 bits in FIG. 2). As a result, the number of inspection data input terminals 10 increases.

  Also in FIG. 2, for the convenience of illustration, the inspection data output to the circuit portion 22 to be inspected is only shown for 6 bits, but if it is 8 bits, four inspection data input terminals 10 are required. That is, in the multichip module 1 of FIG. 1, one extra power input terminal is required, but the total number of external terminals is five, and in the multichip module 21 of FIG. 2, the total number of external terminals is There will be six. This difference in the number is further increased if the shift register 7 of the multichip module 1 is made larger. Further, although the level shift circuit 9 is required on the multichip module 1 side, an increase in circuit scale associated therewith is not burdened.

In the configuration of FIG. 2, it is conceivable that both the circuit under test 22 and the test circuit unit 23 are operated with a 5V power source. However, for example, when the circuit is configured by a MOS process, a high voltage is applied to the circuit. As a result, the lifespan is shortened due to hot carrier deterioration. In other words, the circuit life due to hot carrier deterioration is assumed that the substrate current is Isub.
(Life) ∝Isub ^-α (1)
As the substrate current Isub increases, the shortening of life is accelerated. And the substrate current Isub is Vds as the power supply voltage.
Isub∝Vds ^β (2)
Therefore, the lifespan shortens as the power supply voltage Vds increases. Note that α and β in the equations (1) and (2) are constants.

  Compared with the time during which the circuit portion 4 to be inspected, which has the original function of the multichip module 1, operates, the time during which the inspection circuit portion 5 operates is only during the inspection, and thus is extremely short. Therefore, even if a high voltage is applied to the inspection circuit unit 5 side and stress is applied only during the inspection, the function as the multichip module 1 is not affected.

As described above, according to the present embodiment, 3 V power is supplied to the circuit under test 4 from the outside via the power input terminal 12, and 5 V power is supplied to the test circuit 5 via the power input terminal 13. Supply. Then, the inspection circuit unit 5 converts the data serially input in synchronization with the clock through the inspection data input terminal 10 to parallel, and converts the level of the converted inspection data by the level shift circuit 9 to inspect the circuit to be inspected. Part 4 was given.
Therefore, since the time for serially inputting the inspection data can be shortened by increasing the frequency of the synchronous clock given from the outside, the number of inspection data input terminals 10 is reduced and the number of bits of data input serially from one terminal is increased. Even in such a case, the inspection can be performed in a short time, and the increase in the number of external terminals can be suppressed and the package size can be reduced. Since the high voltage is applied only to the test circuit unit 5 that is used less frequently, the circuit unit 4 that is used frequently is not affected, and the reliability is reduced. There is no.

Since the present invention is applied to the multi-chip module 1 including a plurality of IC chips 2 and 3, it is necessary to perform a function test for more items, and the present invention is applied to a case where the entire test time must be prolonged. Thus, the inspection can be performed in a short time while suppressing an increase in the number of external terminals, which is preferable.
In addition, since the inspection circuit unit 5 is shared by the plurality of IC chips 2 and 3, it is not necessary to provide the same number of inspection circuit units 5 as the IC chips, and the entire multichip module 1 can be configured in a small size.

The present invention is not limited to the embodiments described above and shown in the drawings, and the following modifications or expansions are possible.
You may apply to the semiconductor integrated circuit of a single chip structure. Moreover, you may apply to what is equipped with three or more IC chips.
When a plurality of IC chips are provided, an inspection circuit portion may be provided corresponding to the circuit portion to be inspected of each IC chip.
The number of bits of the inspection data may be changed as appropriate.
The power supply voltages applied to the circuit part to be inspected and the circuit part to be inspected are also examples, and may be appropriately changed according to individual designs within a range that satisfies the condition (V1 <V2).

1 is a diagram schematically showing a configuration of a multichip module according to an embodiment of the present invention. FIG. 1 equivalent diagram of the conventional configuration shown for comparison

Explanation of symbols

  In the drawings, 1 is a multichip module (semiconductor integrated circuit), 2 is an IC chip, 3 is an IC chip (circuit portion to be inspected), 4 is a circuit portion to be inspected, 5 is an inspection circuit portion, 7 is a shift register, A level shift circuit, 10 is an inspection data input terminal, 11 is a clock input terminal, and 12 and 13 are power supply input terminals (first and second power supply terminals).

Claims (6)

When a clock signal is given from the outside via a circuit input to be inspected and a clock input terminal, and the data input serially through the inspection data input terminal is converted into parallel in synchronization with the clock signal, the circuit to be inspected In a semiconductor integrated circuit comprising a test circuit unit that outputs test data to the unit,
A first power supply terminal to which power is supplied from the outside to the circuit part to be inspected;
A power supply voltage higher than a power supply voltage supplied to the first power supply terminal is applied, and a second power supply terminal is provided to supply power to the inspection circuit unit from the outside,
The semiconductor integrated circuit according to claim 1, wherein the inspection circuit unit includes a level shift circuit that converts a level of the inspection data and outputs the converted data to the circuit under test.   2. The semiconductor integrated circuit according to claim 1, wherein the circuit portion to be inspected is a plurality of IC chips.   3. The semiconductor integrated circuit according to claim 2, wherein the inspection circuit unit is shared by a plurality of IC chips. A clock signal is given from the circuit to be inspected and the clock input terminal from the outside, and the data inputted serially through the inspection data input terminal is converted into parallel in synchronization with the clock signal, and the object to be inspected In a test method for a semiconductor integrated circuit comprising a test circuit unit that outputs test data to a circuit unit,
Supply a power supply voltage higher than the power supply voltage supplied to the circuit portion to be inspected to the inspection circuit portion, and in that state, input the inspection data serially from the outside,
A method for inspecting a semiconductor integrated circuit, wherein the level of inspection data converted into parallel is converted and output to the circuit portion to be inspected.   5. The semiconductor integrated circuit inspection method according to claim 4, wherein the circuit portion to be inspected is applied to a plurality of IC chips.   6. The method for inspecting a semiconductor integrated circuit according to claim 5, wherein the inspection circuit portion is inspected in a state where the inspection circuit portion is shared by a plurality of IC chips.

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