JP2009266125A - Memory system - Google Patents

Abstract

In a memory system having a function of accessing a plurality of memory blocks in a plurality of NAND memories in parallel, at least one of the plurality of memory blocks is defective when accessing the plurality of memory blocks in parallel. Even if there is, there is a single access to minimize the performance degradation of the NAND memory, and management is performed so that useless memory blocks do not occur.
In a memory system having a management table used for NAND flash memory access management, a parallel management table corresponding to an area space for managing the management table according to the degree of parallelism of memory blocks when accessing the management table in parallel In the case of independent access, it is separated from the single management table corresponding to the area space to be managed, and if even one of the memory blocks accessed in parallel is defective, the single management table is entered and accessed independently. Switching function.
[Selection] Figure 2

Description

  The present invention relates to a memory system using a flash-EEPROM type nonvolatile memory, and in particular, a memory having a function of accessing a memory block of a plurality of NAND flash memories (hereinafter referred to as NAND memories) in parallel. For example, the system is used for main storage as an alternative to a hard disk drive.

  Currently, semiconductor memories are used everywhere from the main memory of large computers to personal computers, home appliances, mobile phones and the like. The market that has grown significantly is flash EEPROM type nonvolatile memory represented by NAND-Flash Memory. This is used for many information devices such as mobile phones and digital cameras because the data does not disappear even when the power is turned off and the structure is suitable for high integration. That is, various memory cards (SD cards, SD cards, MP3 and other music devices, storage media such as mobile PCs, digital TVs, etc.) are used as media for storing information such as images, videos, sounds, and games. MMC card, MS card, CF card, etc.), USB memory (USB memory) as a storage medium for personal computers, mobile phone memory, etc.

Flash EEPROM type non-volatile memory mainly includes NOR type memory (NOR memory) and NAND type memory (NAND memory). NOR memory has the characteristics of high-speed reading and the number of ^{readings of} about 10 ¹³ and is used as an instruction code storage for portable devices, but it is not suitable for file recording because its effective writing bandwidth is small.

  On the other hand, NAND memory can be highly integrated compared with NOR memory, and with respect to read characteristics, the access time is as low as about 25 μs, but burst read is possible and the effective bandwidth is high. As for the write characteristics, although the program time is as slow as 200μs and the erase time is about 1ms, the number of bits that can be programmed and erased at one time is large, the write data is captured by burst operation, and a large number of bits are paged at a time. Because it can be programmed, the effective bandwidth is high.

In addition, since the NAND memory can be increased in capacity by high integration, it has recently been considered as a replacement of a hard disk, but there are some restrictions in use. First, since there is data deterioration due to the number of read / write (& erase) times, there is a write number limit (program / erase number limit). That is, the NAND memory program injects electrons into the floating gate by applying a high voltage to the gate of the memory cell transistor with respect to the substrate. If this operation is performed many times, the oxide film around the floating gate of the memory cell transistor deteriorates and the data is destroyed. Currently, the reading and writing of the NAND memory (and erase) possible number of times is about 10 ⁵ times, very low compared to other non-volatile memory, along with the multi-level of miniaturization and cell of the future of the process, writing the number of times Is expected to decrease further. When using NAND memory with a memory card or USB memory, it takes a considerable amount of time to access about 10 ⁵ times, so NAND memory can be used practically. However, considering that NAND memory is installed in a hard disk replacement system, the number of accesses reaches about 10 ⁵ times in a short period of time.

  In addition, the NAND memory has a restriction of prohibiting writing twice with erasing before writing. The NAND memory program can only be controlled in the direction in which electrons are injected into the floating gate (data “1” → data “0” direction: 0 write), and the electrons are extracted (data “0” → data “1” direction). : 1 writing) must be erased. At this time, in general, a program is in units of pages, whereas erasing can be performed only in units of blocks composed of several pages. Therefore, when it is desired to change the data of the programmed page, it is necessary to temporarily save the data in the same block to another area, erase it, and then program it again. Actually, since there is a limit on the number of rewrites described above, an excessive program / erase operation is avoided by writing a page to be rewritten in another erased area and managing it using a logical-physical conversion table.

  As a further constraint on NAND memory, reverse page programming is prohibited in NAND memory. For example, when programming in a block, there is a restriction that it must be executed in ascending order from page address 0.

  In the case of constructing a memory system using the NAND memory as described above, consider the case where the main storage used for replacing the hard disk is constructed as a solid state drive (SSD). In this case, high speed / performance is required, it is necessary to access a plurality of memory blocks in parallel, and to increase the parallelism of access to, for example, 4 parallels (8 bits × 4 channels) or more. However, if the number of defective memory blocks having a large number of defective cells varies greatly, there is a problem that memory blocks of usable channels are wasted when accessed in parallel.

Patent Document 1 discloses a method for creating a logical block, a physical block having a redundant part for storing the address of the logical block, and a logical address / physical address conversion table for managing the correspondence between the logical block and the physical block. Is disclosed.
Japanese Patent Laid-Open No. 11-110283

  The present invention has been made to solve the above-described conventional problems, and even when accessing a plurality of memory blocks in the NAND memory in parallel, it is possible to minimize the decrease in the performance of the NAND memory, and An object of the present invention is to provide a memory system that can be managed so as not to generate useless memory blocks.

  In a memory system having a management table used for access management of NAND flash memory, the present invention provides a parallel block access function for accessing a plurality of memory blocks of the NAND flash memory in parallel, and a plurality of the memory blocks. A single block access function for accessing a specific memory block independently, and a parallel management table corresponding to an area space that is managed according to the degree of parallelism of the memory block when accessing the management table in parallel. A function that separates into a single management table corresponding to the area space to be managed and switches to enter a single management table and access it independently if there is any bad block among memory blocks accessed in parallel It is characterized by comprising.

  According to the memory system of the present invention, when a plurality of memory blocks of a NAND memory are accessed in parallel, even if one of the plurality of memory blocks has a defective block, the performance degradation of the NAND memory is minimized. And can be managed so that a useless memory block does not occur.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

<First Embodiment>
FIG. 1 is a block diagram schematically showing an example of a hardware configuration of an SSD capable of parallel access according to the first embodiment of the memory system of the present invention. In this example, a configuration in which 4-channel parallel access is possible is shown. FIG. 2 is a block diagram showing in detail an example of the relationship between the firmware (FW) layer and the hardware (HW) layer in the SSD of FIG.

  1 and 2, reference numerals 111 to 114 denote a plurality of flash type EEPROM memories (in this example, NAND memories) having a floating gate and an array of electrically erasable and writable memory cells. The SSD controller (SSD Controller) 10 includes a NAND memory controller (NANDC) 12, a DMAC (direct memory access controller) 13, and cache memory for temporarily storing data in the NAND memories 111 to 114, MeP, Boot ROM, PIO , Various controllers such as SIO, ATA-C, and DRAM-C, various interface circuits (I / F) that communicate with an external host computer (PC) 41 and a communication terminal (Terminal) 42, and the like. As the cache memory, a volatile memory such as DRAM or SRAM or a non-volatile memory such as FeRAM, MRAM, PRAM, or RRAM can be used.

  The FW layer 20 includes a boot loader 21, an ATA manager 22, a security manager 23, a data manager 24, a debug manager 25, and various drivers. Of these, data manager 24 is particularly relevant to the present invention.

  The data manager 24 includes a management table (including a bad block address management table in which addresses of bad block areas in the NAND memories 111 to 114 are registered) used for access management of the NAND memories 111 to 114 and data management of the block areas. Have.

  The NAND memory controller 12 has a parallel block access function for accessing each memory block (a plurality of memory blocks) of the NAND memories 111 to 114 in parallel (four-channel parallel block access) and a specific one of the plurality of memory blocks. It has a single block access function for accessing a memory block independently. Furthermore, the parallel management table corresponding to the area space that manages the management table according to the degree of parallelism of the memory block when performing parallel block access, and the single management table corresponding to the area space that is managed when accessing the single block And has a function of separating. In addition, if any one of the memory blocks accessed in parallel has a bad block (Bad Block), it has a function of entering into the single management table and switching to single access.

  When the NAND memory controller 12 tries to access each memory block in parallel as the access target in the NAND memories 111 to 114, the NAND memory controller 12 sets the access target based on the bad block address management table managed by the data manager 24. When it is determined that there is no defective block area, it has a function of performing parallel block access processing based on the parallel management table. Further, the NAND memory controller 12 has a function of entering the single management table and switching to single block access when at least one defective block area exists in the access target.

  The above processing can be performed even by an MPU connected to the NAND memory, but the time required for data comparison becomes long and overhead for other processing. Therefore, in the present invention, the NAND memory controller 12 The above processing function is provided.

  FIG. 3 shows a physical configuration in the case of performing parallel block access to the four NAND memories 111 to 114 in FIG. 1 and a state in which single block access is performed by performing logical address / physical address conversion. In FIG. 3, 30 is a normal block area, 31 is a defective block area, 30a is a normal block area relieved by single block access, and 30b is a normal block area accessed in parallel block. Here, it is assumed that a defective block region 31 exists in each of the four NAND memories 111 to 114.

  According to FIG. 3, when performing parallel block access to the NAND memories 111 to 114, if any one of the plurality of memory blocks has a defective block area, the NAND memory 111 to 114 can be accessed independently to obtain a non-defective block area. It can be seen that the normal block is relieved.

  For example, in a 16 Mbit NAND memory, each page of the physical block has a data area of 256 bytes and a redundant area of 8 bytes. For example, in a 64-Mbit NAND memory, each page of the physical block has a 512-byte data area and a 16-byte redundant area. With such a configuration, the actual physical bit number of the NAND memory is larger than the nominal bit number, and the required data (stored data pass / fail flag, Block Address data, ECC data, etc.) are stored.

  As described above, according to the memory system of this embodiment, when accessing a plurality of memory blocks in the NAND memory in parallel, even if one of the plurality of memory blocks has a defective block, the memory system is accessed independently. As a result, it is possible to manage the deterioration of the performance of the NAND memory to a minimum and prevent a useless memory block from being generated.

1 is a block diagram schematically showing an example of a hardware configuration of an SSD capable of parallel access according to a first embodiment of a memory system of the present invention; The block diagram which shows in detail an example of the relationship between the firmware layer and hardware layer in SSD of FIG. FIG. 2 is a diagram illustrating a physical configuration when performing parallel access to four NAND memories in FIG. 1 and a state when performing single block access by performing logical address / physical address conversion.

Explanation of symbols

10 ... SSD controller, 111-114 ... NAND memory, 12 ... NAND memory controller, 20 ... FW layer, 24 ... Data manager.

Claims (1)

In a memory system having a management table used for NAND flash memory access management,
A parallel block access function for accessing a plurality of memory blocks of the NAND flash memory in parallel and a single block access function for accessing a specific memory block of the plurality of memory blocks independently;
A parallel management table corresponding to an area space that is managed according to the degree of parallelism of the memory blocks when accessing the management table in parallel; and a single management table corresponding to an area space that is managed when accessing the management table independently. A memory system comprising a function of switching to separate access to a single management table if there is any defective block among the memory blocks accessed in parallel.

Images