JP2009261079A - Digital converter and method of controlling the same - Google Patents

Abstract

A digital converter capable of operating under optimum conditions in accordance with the characteristics of each switching element is provided.
A boost chopper 4 configured by connecting three sets of circuits in which coils L1 to L3 and switching elements Q1 to Q3 are connected in series, and a rectifier circuit 2 for supplying an input current to each of the coils L1 to L3; The digital converter includes a computer circuit 3 that performs PWM control of the switching elements Q1 to Q3 in a predetermined control cycle. While determining whether the input current to the coil is a continuous mode in which the current is not interrupted during the control cycle or a discontinuous mode in which the current is interrupted in the middle of the control cycle, the PWM control is executed with a different algorithm based on the determination result, while each switching The element Qi is driven by a PWM wave having a pulse width Ni * Ton corrected according to each characteristic.
[Selection] Figure 7

Description

  The present invention relates to a digital converter using a step-up chopper, and more particularly to an apparatus capable of realizing high-efficiency and low-loss PWM control by optimally operating a plurality of switching elements.

The applicant has previously proposed a device capable of realizing precise PWM control without using an expensive coil (Patent Document 1).
JP 2007-202342 A

  The invention described in this patent document is a digital converter having a step-up chopper provided with a coil and a switching element, a rectifier circuit that supplies an input current to the coil, and a computer circuit that performs PWM control of the switching element in a predetermined control cycle. The PWM control is performed by a different algorithm based on the determination result while determining whether the input current to the coil is a continuous mode where the current is not interrupted during the control cycle or the discontinuous mode where the current is interrupted during the control cycle.

  Then, three circuits including substantially the same coils L1 to L3 and switching elements Q1 to Q3 are connected in parallel to constitute a boost chopper.

  However, even if each switching element is controlled with the same control on-time due to variations in the characteristics of the coil and the switching element and variations in the wiring, the average current flowing through each switching element is different, and power loss and heat generation are unbalanced. There is a problem that each element cannot be operated at the maximum capacity in balance. That is, as long as a power loss higher than the design power loss is expected, a switching element having a large current capacity corresponding to the design margin must be mounted, which is an obstacle to downsizing and cost reduction of the device.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a digital converter that can be operated under optimum conditions in accordance with the characteristics of each switching element.

  In order to achieve the above object, according to the first aspect of the present invention, there is provided a step-up chopper configured by connecting a plurality of n sets of circuits each having a coil and a switching element connected in series, and supplying an input current to each of the coils. A digital converter comprising a rectifier circuit and a computer circuit that PWM-controls each switching element in a predetermined control cycle, and controls whether the input current to the coil is not interrupted during the control cycle. While determining whether the discontinuous mode is interrupted in the middle of the cycle, the PWM control is executed by a different algorithm based on the determination result, while each switching element Qi has a pulse width Ni corrected according to each characteristic. * Driven by a PWM wave with Ton.

  In the present invention, each switching element is preferably driven sequentially with a phase shift of 360 / n degrees, and a typical example is n = 3.

  According to a third aspect of the present invention, there is provided a step-up chopper configured by connecting a plurality of n switching elements connected in parallel and a coil, a rectifier circuit for supplying an input current to the coil, and the switching elements. A digital converter configured with a computer circuit that performs PWM control in a predetermined control cycle, and a continuous mode in which the input current to the coil is not interrupted during the control cycle, or a discontinuous mode in which the current is interrupted during the control cycle While the PWM control is executed by a different algorithm based on the determination result, each switching element Qi is driven by a PWM wave having a pulse width Ni * Ton corrected according to each characteristic. Is done.

  In any of the above inventions, it is preferable that the DC output voltage of the step-up chopper is obtained from a single capacitor that is charged when each switching element is turned off. In addition, in the current control cycle, whether the continuous mode or the discontinuous mode is determined is determined based on the measured values of the coil charging start current, the AC input voltage to the boost chopper, and the DC output voltage of the boost chopper. Typically, it is determined based on the control time of the PMW wave in the control cycle and the inductance value of the coil.

  In the above invention, the coil charging start current may be detected by a current detection resistor, but may be specified based on the voltage value between the output terminal and the common terminal of the switching element at the coil charging start timing. In this case, no detection element is required. An IGBT is typically used as the switching element, and the coil charging start current is specified based on the collector-emitter voltage and the collector current characteristics.

  Further, in the present invention, since the coil charging end current can be specified in the same manner, the coil inductance is determined by the voltage value between the output terminal and the common terminal of the switching element at the start and end of charging of the coil. And a pre-stored registered value for the voltage-current characteristic of the switching element.

  The correction value Ni (i = 1 to n) defining the pulse width Ni * Ton is set to Ni = MID / Ipi based on the current value Ipi at the time of OFF transition of each switching element. However, it is the average value or median value of MID: Ip1-Ipn.

  If such a correction term Ni is provided, the power loss of the plurality of switching elements can be made uniform when the digital converter is operating in the discontinuous mode. Further, even when the digital converter is operating in the continuous mode, the power loss imbalance can be suppressed.

  Further, the correction value Ni (i = 1 to n) for defining the pulse width Ni * Ton is based on the statistical value TYP (Ipi) of the current value Ipi at the time of OFF transition of each switching element, Ni = MID / ( It is also preferable that the value is updated during the driving operation by calculating Ni * TYP (Ipi)). However, it is the average value or median value of MID: N1 * TYP (Ip1) to Nn * TYP (Ipn). Here, the statistical value TYP (Ipi) is appropriately determined, but it is easy to adopt an average value as in the embodiment.

  Furthermore, it is also preferable that the correction value Ni (i = 1 to n) that defines the pulse width Ni * Ton is determined based on the heat generation state of each switching element. In such an embodiment, the heat generation of each switching element can be made uniform in all operation regions regardless of whether the operation state is the discontinuous mode or the continuous mode.

  According to the present invention described above, a plurality of switching elements can be operated under optimum conditions in accordance with respective characteristics.

  Hereinafter, the present invention will be described in more detail based on examples. FIG. 1 is a circuit configuration diagram showing a digital converter 1 under software control, which is incorporated as a part of a motor control system. In this digital converter 1, a single-phase AC voltage (for example, 200 V) is rectified by a full-wave rectifier circuit 2 to become a pulsating current, and then a step-up chopper 4 that is PWM (Pulse Width Modulation) controlled by a one-chip microcomputer 3. It is converted into a predetermined DC voltage Vdc (for example, 350V). The three-phase motor M is driven by an inverter circuit 5 controlled by the one-chip microcomputer 3.

  In this embodiment, three step-up choppers 4a to 4c are connected in parallel, and each step-up chopper 4a to 4c is controlled to turn on with a phase delay of 120 degrees. That is, the step-up chopper 4 includes switching elements Q1 to Q3 that are turned on by three types of PWM waves (PWM1 to PWM3) having different phases, coils L1 to L3 and diodes D1 to D3 corresponding to the switching elements Q1 to Q3, and The shunt resistors R1 to R3 that detect the emitter currents of the switching elements Q1 to Q3 and the single smoothing capacitor C that is charged when the diodes D1 to D3 are conducted are mainly configured.

  In this embodiment, an insulated gate bipolar transistor IGBT (Insulated Gate Bipolar Transistor) is used as the switching elements Q1 to Q3, but they are all the same element. The same applies to the coils L1 to L3 and the diodes D1 to D3, and the coils L1 to L3, the diodes D1 to D3, and the shunt resistors R1 to R3 are the same element. However, since the characteristics of the elements do not necessarily match, in this embodiment, unique control is executed to compensate for the mismatch of characteristics.

  As shown in FIG. 1, the coils L1 to L3 and the switching elements Q1 to Q3 are connected in series. The pulsating current output of the full-wave rectifier circuit 2 via the ripple suppression capacitor Cin ( Vac) is supplied. Further, three types of PWM waves (PWM1 to PWM3) having different phases are supplied to the gate terminals of the switching elements Q1 to Q3, and the collector terminals are connected to the anode terminals of the diodes D1 to D3. And the emitter terminal of each switching element Q1-Q3 is connected to shunt resistance R1-R3, and each shunt resistance R1-R3 is connected to the earth line. The cathode terminals of the diodes D1 to D3 are commonly connected to the smoothing capacitor C, and the other end of the smoothing capacitor C is connected to the ground line.

  Since the step-up chopper 4 of the embodiment is configured as described above, when any switching element Qi is turned on, the pulsating input voltage Vac is changed to the switching element Qi, the coil Li and the shunt connected in series to the switching element Qi. A short circuit occurs through the resistor Ri, and a charging current flows through the coil Li. Since the shunt resistors R1 to R3 have low resistance values, they can be almost ignored in the analysis of the circuit operation.

  In the case of the present embodiment, the switching elements Q1 to Q3 are turned on with a 120-degree phase delay, so that a charging current with a 120-degree phase delay flows through each coil Li (see FIG. 12). Then, when the switching element Qi corresponding to the coil Li changes from the ON state to the OFF state in a state where the charging current is flowing through any one of the coils Li, the corresponding diode Di is turned on and the coil Li is discharged. A current flows through a path of the coil Li → the diode Di → the smoothing capacitor C, and the smoothing capacitor C is charged. Since this operation is executed in each of the coils L1 to L3 with a phase delay of 120 degrees, a smoothed DC voltage Vdc is obtained from the smoothing capacitor C.

  Since the shunt resistor Ri is connected to each of the emitter terminals of the switching element Qi, the operating currents of the boost choppers 4a to 4c can be detected at any timing. However, in this embodiment, the current when the switching element Q1 is turned on and the current when the switching elements Q1 to Q3 are turned off are detected. That is, although the charging peak current values Ip1 to Ip3 of the coils L1 to L3 are all detected when the switching elements Q1 to Q3 are turned off (see FIG. 2A), the charging start current is turned on for the switching element Q1. Only the charging start current Is1 of the coil L1 at the time of transition is detected.

  The one-chip microcomputer 3 receives the currents Ic1 to Ic3 of the coils L1 to L3, the input AC voltage Vac, and the output DC voltage Vdc through the signal input units IN1 to IN3, respectively. Each input signal is digitally converted by converters AD1 to AD6. In this embodiment, the A / D converters AD1 to AD3 are set to function at the time of ON transition of the switching element Q1, that is, at the rising edge of the PWM1 wave, and the A / D converters AD4 to AD6 Q3) is set to function at the OFF transition, that is, at the fall of the PWM1 wave to the PWM3 wave.

  The signal input unit IN1 (= IN1a to IN1c) is configured by an OP amplifier circuit that receives the voltage across the shunt resistors R1 to R3, and functions as a current detection sensor together with the shunt resistors R1 to R3. Further, the signal input unit IN2 and the signal input unit IN3 are configured by a resistance voltage dividing circuit and an OP amplifier amplifier circuit.

  The data acquired through the signal input units IN1 to IN3 and the A / D converters AD1 to AD4 are arithmetically processed by the one-chip microcomputer 3, and the ON time of the PWM signal (hereinafter referred to as control on time) is calculated. The PWM signals (PWM1 to PWM3) output from the one-chip microcomputer 3 are supplied to the gate terminals of the switching elements Q1 to Q3 through each buffer circuit DR. The one-chip microcomputer 3 is connected to the inverter circuit 5 through the signal input unit IN4 and the signal output unit OUT2, and controls the three-phase motor M by inverter.

  Hereinafter, prior to describing the specific control operation of the one-chip microcomputer 3, the control principle of the first boost chopper 4a will be described. FIG. 3 is a time chart illustrating the relationship between the first PWM wave (PWM1) output from the one-chip microcomputer 3 and the current flowing through the coil L1 of the first boost chopper 4a. The first boost chopper 4a will be described below. The inductance values of the coils L1 to L3 are all the same, and the circuit operations of the other boost choppers 4b and 4c are the same in principle.

  As shown in the figure, a triangular wave due to a coil charging current and a coil discharging current flows through the coil L1, but the energy stored in the coil L1 is sufficient and the continuous current flows (see FIG. 3A). Since there is insufficient energy, there is a discontinuous mode (see FIG. 3B) in which the current is interrupted in the middle.

  In this embodiment, since different PWM control is performed depending on which operation mode is in use, first, a determination formula for determining the operation mode will be described. In the time chart of FIG. 3, it is assumed that the current time is the control cycle (n−1). Then, it is considered that the control on time Ton (n) in the next control cycle (n) is determined based on the measured value in the control cycle (n−1). Note that the frequency of the AC input voltage is 50 Hz or 60 Hz, but in order to control it sufficiently quickly, in this embodiment, the control cycle T is set to 45.6 μS.

  Hereinafter, the circuit equation will be described with the inductance value of the coil L1 as L. The circuit equation at the time of coil charging (switching element ON) is Vac (n−1) = L * {Ip (n−1) −Iv (n−2)} / Ton (n−1) (Equation 1 ) Here, Iv (n-2) is a coil charging start current, Ip (n-1) is a coil charging peak current, and Ton (n-1) is a control ON time, and each value in the control cycle (n-1). It is. Vac (n−1) is an input voltage in the control cycle (n−1). Since the control cycle T (= 45.6 μS) is sufficiently short with respect to the power supply frequency, Vac (n−1) is constant. Can be regarded as a value.

  On the other hand, the circuit equation at the time of coil discharge (switching element OFF) is Vdc (n−1) −Vac (n−1) = L * {Ip (n−1) −Iv (n−1)} / Toff (n -1) (Expression 2). Here, Vdc (n-1) is the voltage across the capacitor C, Iv (n-1) is the coil current at the end of the current control cycle (coil charging start current of the next control cycle), Toff (n-1). Are OFF times, which are values in the control cycle (n−1), respectively.

  When Ip (n-1) is eliminated from (Equation 1) and (Equation 2) and Iv (n-1) is solved, Iv (n-1) = Iv (n-2) + T / L * [{Vac (N-1) -Vdc (n-1)} + Ton (n-1) * Vdc (n-1)] (Equation 3). The control period T is T = Ton (n−1) + Toff (n−1).

  In the above (Formula 3), if Iv (n−1)> 0, the continuous mode is selected, and if Iv (n−1) = 0, the discontinuous mode is selected. However, (Formula 3) uses the coil charging start current Iv (n-2) in the current control cycle (n-1), and the coil charging start current Iv (n-1) in the next control cycle (n). Therefore, if the charging start current Iv (n−2) is not accurate, the determination of the continuous mode or the discontinuous mode will be wrong. That is, if Iv (n−2) is determined by a prediction calculation based on the control on time (Ton (n−2)) in the immediately preceding control cycle, an error is accumulated by the calculation of (Equation 3). As a result, the control instruction value itself may diverge from the target. Therefore, in this embodiment, the input current ad1 at the start of coil charging is measured for each control cycle.

  However, since a time delay Ts inevitably occurs from the start of the control cycle to the acquisition of the input current, the measured value ad1 is corrected in consideration of this time delay Ts to obtain the coil charging start current Iv (n-2). Yes. Now, assuming that the current measurement value at the timing Ts of the control cycle (n−1) is ad1, the inclination (Δi / Δt) of the coil charging current is Δi / Δt = e / from the relationship of L * Δi / Δt = e. L. Here, e is voltage, i is current, and t is time.

  Therefore, the amount of increase in current at the time delay Ts can be calculated as Vac (n-1) / L * Ts, and using this value, Iv (n-2) = ad1-Vac (n-1) / L * Ts (Expression 4) Substituting (Equation 4) into (Equation 3), Iv (n-1) = ad1- [Vac (n-1) * Ts + T * {Vdc (n-1) -Vac (n-1)} −Ton (n−1) * Vdc (n−1)] / L (Expression 5), and input at the final timing of the current control cycle (n−1) (= start timing of the next control cycle) The current value Iv (n−1) can be accurately determined based on the measured value ad1 of the input current at the start timing of the current control cycle (n−1).

  Then, depending on whether or not the coil charging start current Iv (n-1) of the next control cycle obtained in this way is positive, it is possible to accurately determine whether it is a continuous mode or a discontinuous mode, and an optimal control corresponding to that mode. Is possible. That is, the measured values of the AC input voltage Vac (n-1), the DC output voltage Vdc (n-1), and the input current ad1 in the current control cycle (n-1) and the previous control cycle are determined. On the basis of the control on time Ton (n−1), it can be determined whether the control for the continuous mode or the control for the discontinuous mode should be performed.

  By the way, the DC output voltage Vdc (n−1) does not necessarily need to be updated every control cycle. Therefore, in this embodiment, Vdc (i) whose value is updated every 1 mS is used ( (See step ST30 in FIG. 10). Therefore, the discriminant of the present embodiment is, precisely, Iv (n-1) = ad1- [Vac (n-1) * Ts + T * {Vdc (i) -Vac (n-1)}-Ton (n -1) * Vdc (i)] / L (Formula 5 ').

  Furthermore, the average value Vdc for the past 0.5 seconds calculated by the process of step ST38 in FIG. 10 may be used as the DC output voltage. In this case, Iv (n-1) = ad1- [Vac (n-1) * Ts + T * {Vdc-Vac (n-1)}-Ton (n-1) * Vdc] / L ... ( The discriminant of equation 5 ″) is adopted.

<Discontinuous mode>
Next, a method for calculating the control on time Ton (n) based on the coil average current Iav during each control cycle will be described. First, the control on time Ton (n) in the discontinuous mode is calculated (see FIG. 3B).

  The circuit equation at the time of coil charging is Vac (n) = L * {Ip (n) −Iv (n−1)} / Ton (n), but Iv (n−1) = 0 because of the discontinuous mode. In the end, Vac (n) = L * Ip (n) / Ton (n) (Formula 6). Here, Vac (n) is the AC input voltage, Ip (n) is the current value at the coil charging peak, Iv (n−1) is the current value at the start of coil charging, and Ton (n) is the control on time. .

  On the other hand, the circuit equation at the time of coil discharge is Vdc (n) −Vac (n) = L / Tcut (n) * {Ip (n) −Iv (n)}. Tcut (n) is a time until the current value Ip (n) in the coil charge peak state is discharged and becomes zero (see FIG. 3B). Here, since the circuit equation of the discontinuous mode is considered, Iv (n) = 0, and Vdc (n) −Vac (n) = L / Tcut (n) * Ip (n) (Expression 7) ) Also, the average value Iav (n) of the input current in this control cycle is Iav (n) = {Ip (n) * Ton (n) + Ip (n) * Tcut (n)} / (2 * T). (Formula 8)

  Then, when these (Equation 6) to (Equation 8) are solved for Ton (n), Ton (n) * Ton (n) = {2 * T * L * Iav (n) * (Vdc (n) −Vac (N))} / {Vac (n) * Vdc (n)} (Expression 9)

<Continuous mode>
Subsequently, the control on time Ton (n) in the continuous mode is calculated (see FIG. 3A). The circuit equation at the time of coil charging is Vac (n) = L * {Ip (n) −Iv (n−1)} / Ton (n) (Equation 10). On the other hand, the circuit equation at the time of coil discharge is Vdc (n) −Vac (n) = L / Toff (n) * {Ip (n) −Iv (n)} (Equation 11). Here, Toff (n) = T−Ton (n), which is the time from the start of coil discharge to the start of coil charge in the next control cycle.

  The average current Iav (n) in this control cycle is Iav (n) = [{Ip (n) + Iv (n−1)} * Ton (n) + {Ip (n) + Iv (n)} * Toff (N)] / {2 * T} (Expression 12) Here, when (Equation 10) to (Equation 12) are solved for Toff (n) while erasing Ip (n) and Iv (n), Toff (n) * Toff (n) = [2 * T * L * {Iv (n−1) −Iav (n)} / Vdc (n)] + T * T * Vac (n) / Vdc (n) (Formula 13) Therefore, Ton (n) Is calculated as Ton = T−Toff (n) (Equation 14).

  In this embodiment, the control on-time Ton (n) is calculated using (Equation 9) or (Equation 14) according to the discontinuous mode or the continuous mode. Prediction parameters for the AC input voltage Vac (n), the DC output voltage Vdc (n), and the average input current Iav (n) in (n) are required.

  The AC input voltage Vac (n) is predicted based on the current AC input voltage measurement value Vac (n-1) and the previous AC input voltage measurement value Vac (n-2). The difference between the control cycle (n-2) and the control cycle (n-1) measurement value is added to the current measurement value Vac (n-1) as follows. Vac (n) = 2 * Vac (n-1) -Vac (n-2) (Equation 15)

  On the other hand, for the DC output voltage Vdc (n), an average value Vdc of past measurement values for the DC voltage is adopted. Although the calculation method of the average value Vdc is determined as appropriate, in this embodiment, the measured values for the past 0.5 seconds are averaged by the averaging process executed every 0.5 seconds to obtain the DC output voltage Vdc. (See step ST38 in FIG. 10). This DC output voltage Vdc is stored in an appropriate work area of the memory, and the value Vdc of this work area is updated every 0.5 seconds.

  Therefore, in this case, in the discontinuous mode, Ton (n) * Ton (n) = {2 * T * L * Iav (n) * (Vdc−Vac (n))} / {Vac (n) * Vdc} (Equation 9 ′) On the other hand, in continuous mode, Toff (n) * Toff (n) = [2 * T * L * {Iv (n−1) −Iav (n)} / Vdc ] + T * T * Vac (n) / Vdc (Expression 13 ′), Ton = T−Toff (n) (Expression 14 ′).

  However, instead of using the average value Vdc for 0.5 seconds, the value of Vdc (i) obtained from the output value AD3 of the A / D converter AD3 every 1 mS may be used. In this case, in the discontinuous mode, Ton (n) * Ton (n) = {2 * T * L * Iav (n) * (Vdc (i) −Vac (n))} / {Vac (n) * Vdc (i)} (Equation 9 ″) On the other hand, in the continuous mode, Toff (n) * Toff (n) = [2 * T * L * {Iv (n−1) −Iav ( n)} / Vdc (i)] + T * T * Vac (n) / Vdc (i) (Expression 13 ″), Ton = T−Toff (n) (Expression 14 ″) Become.

  The predicted value of the average input current Iav (n) is Iav (n) = β * Vac (n) from the relationship with the predicted value of the AC input voltage Vac (n). Here, the gain β is adjusted by PI control so that the difference Verr becomes zero while comparing the reference value (target value) Vo of the DC output voltage with the above-mentioned averaged DC output voltage Vdc.

  That is, Verr = Vo−Vdc (Expression 16), and Vo = Vac (pk) + α (Expression 17). Here, the reference value Vo of the DC output voltage is set to a value obtained by adding the amount of boost α by the coil L to the peak value Vac (pk) of the AC input voltage (pulsating flow). By setting in this way, conversion with high efficiency according to the input voltage value is possible. In addition, since the amount of pressure boosted by the coil L can be reduced, it is possible to select an inexpensive and lightweight coil with an appropriate size that does not increase in size. The optimum inductance value of the coil L is generally determined based on a design formula of L = Vac * Vac * (Vdc−Vac) / {γ * Pac * Vdc / T}. Since the output voltage value Vdc is set in correspondence with the voltage value Vac, the inductance value of the coil always maintains an almost optimum value. In the above design formula, γ is the ripple content of the input current, T is the control period, Pac is the maximum input power, and Vac is the instantaneous value of the input voltage.

  As described above, the control principle of the PWM control has been described based on FIG. 3. Next, the one-chip microcomputer 3 that realizes the control operation of FIG. 3 will be specifically described.

  FIG. 4 illustrates an internal configuration diagram of the one-chip microcomputer 3. Here, a single-chip RISC microcomputer SH7046 (Renesas Technology Corp.) is used. The one-chip microcomputer 3 includes a CPU core 30, a clock generation unit 31, an AD conversion unit 32, and a multifunction timer pulse unit (MTU) 33. The clock generator 31 of this embodiment oscillates a 50 MHz system clock, and a 25 MHz peripheral clock PΦ obtained by dividing the system clock by two is supplied to the MTU 33. Then, the peripheral clock PΦ is supplied to the counter of the MTU 33 as it is as a counting clock (frequency 25 MHz) without being divided thereafter.

  FIG. 5 schematically illustrates the internal configuration of the AD conversion unit 32. The AD conversion unit 32 has 8-channel analog input terminals AN8 to AN15. The input analog signal is AD converted by a successive approximation method, and digital data after AD conversion (resolution 10 bits) is: Stored in data registers ADDR8 to ADDR15.

  In this embodiment, each analog signal indicating the operation state of the step-up chopper 4 is supplied to the above-described AD conversion unit 32 via the signal input units IN1 to IN3. It functions as three-channel A / D converters AD1 to AD3 and one-channel A / D converters AD4 to AD6 that operate in a timely manner.

  The 3-channel A / D converters AD1 to AD3 are set to operate in the continuous scan mode, and when receiving an AD conversion start trigger (see FIGS. 5 and 7) from the MTU 33 at the rising edge of the PWM1 wave, The D converters AD1 to AD3 perform AD conversion operations in that order. When the AD conversion operation is completed, an interrupt signal (ADI interrupt) is set to be output to the CPU core 30. In the ADI interrupt processing program, the CPU core 30 sets the data ad1 to AD1 after AD conversion. ad3 is acquired from the data register ADDRj of the AD converter 32 and stored in the memory.

  On the other hand, the A / D converters AD4 to AD6 are configured to receive an AD conversion start trigger due to a compare match of the corresponding general register when the PWM1 to PMW3 waves fall. When an AD conversion start trigger is received, any of the A / D converters AD4 to AD6 selected at that timing starts the AD conversion operation in the single mode. When the AD conversion operation is completed, the CPU core 30 is set to output an interrupt signal (ADI interrupt) to the CPU core 30. Therefore, the CPU core 30 sets the data adj ( j = 4 to 6) is acquired from the data register ADDRj of the AD conversion unit 32 and stored in the memory.

  FIG. 6 illustrates the internal configuration of an MTU (multifunction timer pulse unit) 33. The MTU 33 is configured by a 16-bit timer of 5 channels (channel_0 to channel_4), and can output a PWM wave having an arbitrary pulse width based on setting data to various registers.

  In the case of the present embodiment, each setting of the MTU 33 is as follows.

<Settings related to the AD conversion unit 32>
In this embodiment, the “control cycle” repeated every 45.6 μS includes a “data acquisition cycle” for operating the A / D converter and a “calculation” for calculating the control on-time Ton based on the AD-converted acquired data. The cycle is divided into “cycle”, and “data acquisition cycle” and “calculation cycle” are alternately repeated.

  In the “data acquisition cycle”, an AD conversion start trigger is generated by a compare match of TGRA — 0 (general register A of channel 0), and the A / D converters AD1 to AD3 are AD-converted in the continuous scan mode.

  In the “data acquisition cycle”, an AD conversion start trigger is generated by a compare match of TGRA_2 (general register A of channel 2) at the fall of any of the three-phase PWM waves (PWM1 to PWM3). Then, among the A / D converters AD4 to AD6, the corresponding A / D converter ADj is AD-converted. Note that the CPU core 30 appropriately sets the set values for the A / D converter ADj that starts the operation upon receiving the AD conversion start trigger and the TGRA_2 (the general register A of the channel 2) that defines the generation timing of the AD conversion start trigger. Is set to change.

<Setting of interrupt request to CPU core 30>
The CPU core 30 is caused to generate a CH0 interrupt request signal by a compare match of TGRA_0 (channel 0 general register A). In response to this interrupt request signal, the CPU core 30 executes the interrupt processing program CM_INT shown in FIG.

  The execution contents differ depending on whether the control cycle is a “data acquisition cycle” or a “calculation cycle”. In the “calculation cycle”, the data acquired in the preceding “data acquisition cycle” Based on the control ON time Ton is calculated.

  On the other hand, in the “data acquisition cycle”, the control ON time Ton is corrected for each switching element Q1 to Q3 based on the PWM duties N1, N2 and N3 of the switching elements Q1 to Q3. Here, the PWM duties N1 to N3 are correction values for making the power consumption in the switching elements Q1 to Q3 substantially coincide.

  As shown in FIG. 2, even when the control on-time Ton for turning on the switching elements Q1 to Q3 is the same, the charge peak currents Ip1 to Ip3 are usually different (in the example shown, there is a relationship of Ip1> Ip2> Ip3). , The control on time of the switching element Q2 indicating the median MID (here Ip2) is set to Ton, and the control on time of the switching element Q3 indicating the minimum value is widely set to Ton * Ip2 / Ip3, while the maximum value is set The control ON time of the switching element Q1 shown is narrowly set to Ton * Ip2 / Ip1. That is, in the case of FIG. 2, PWM duties N1 to N3 of N1 = Ip2 / Ip1, N2 = Ip2 / Ip2, and N3 = Ip2 / Ip3 are provided.

  In the “data acquisition cycle”, the control ON time Ton is corrected based on the PWM duties N1 to N3 determined in this way, and the set values such as N1 * Ton, N2 * Ton, N3 * Ton are set to the MTU 33. TGRA_0 to TGRD_0 (general registers A, B, C, D of channel 0) and TGRA_1 to TGRB_1 (general registers A, B of channel 1). These set values are numerical values that define the rising timing and falling timing of the three-phase PWM wave output from the MTU 33. In the “data acquisition cycle”, for example, the PWM duties N1 to N3 of the three switching elements Q1 to Q3 are reviewed at a rate of once every several seconds and corrected to optimum values.

<Settings related to the operation of the MTU 33>
[Setting (1)] Of channels 0 to 4, channels 0 to 2 are set to "synchronous operation". Then, the channel 0 counter clearing factor is set to “TGRA — 0 (channel 0 general register A) compare match”, and the channel 1 and 2 counter clearing factors are set to “synchronous clear”. Therefore, the timer counters TCNT_0 to TCNT_2 of the channels 0 to 2 are cleared in synchronization with the compare match of TGRA_0.

  [Setting (2)] Channels 0 to 1 are set to “PWM mode 1”. In PWM mode 1, TGRA (general register A) and TGRB (general register B) are used in pairs, and a PWM wave (PWM1 and PWM3) is output from the TIOCA_0 terminal and the TIOCA_1 terminal by a TGRA and TGRB compare match. Is done.

  Also, by using TGRC_0 (general register C of channel 0) and TGRD_0 (general register D of channel 0) in pairs, PWM2 is output from the TIOCC_0 terminal by a compare match between TGRC_0 and TGRD_0.

  [Setting (3)] TGRA_0 to TGRD_0 (channel 0 general registers A, B, C, D), TGRA_1 to TGRB_1 (channel 1 general registers A and B), and TGRA_2 (channel 2 general registers A) The CPU core 30 writes a set value in response to an interrupt request due to a TGRA_0 compare match.

  Specifically, 1140, N1 * Ton, 380, 380 + N2 * Ton are written in TGRA_0 to TGRD_0 (channel 0 general registers A, B, C, D), and TGRA_1 to TGRB_1 (channel 1 general registers A, B, C, D) are written. B) is written with 760, 760 + N3 * Ton. These are set values for generating three-phase PWM waves (PWM1 to PWM3). Here, Ton is a control on time calculated for each control cycle, and N1 to N3 are statistically and dynamically corrected PWM duty.

  In addition, any one of N1 * Ton, 380 + N2 * Ton, and 760 + N3 * Ton is written into TGRA_2 (General register A of channel 2) according to the timing at the time of the write operation. This is a set value for generating an AD conversion start trigger at the falling timing of the three-phase PWM waves (PWM1 to PWM3).

  [Setting (4)] The output level of the TIOCA terminal and the TIOCC terminal (PWM output terminal of the MTU 33) is the same as that of TGRA or TGRAC (general registers A and C) and TGRB or TGRD (general register B). Sometimes changes.

  Then, each output of TIOCA_0, TIOCC_0, and TIOCA_1 rises to an H level at the time of TGRA_0 to TGRA_1 compare match or TGRC_0 compare match by initial setting to the TIOR (timer IO control register) of each channel. It is set to fall to L level at the time of TGRB_1 compare match or TGRD_0 compare match.

  [Setting (5)] The counting clock of the timer counter TCNT is set to 25 MHz (period 40 nS), which is the same as the peripheral clock PΦ.

  The MTU 33 is set and operated as described above. FIG. 7A shows the relationship between the timer counters TCNT (TCNT_0 to TCNT_2) of the channels 0 to 2 and the general registers (TGRA_0 to TGRD_0, TGRA_1 to TGRB_1) in relation to the operation of the MTU 33, and The PWM wave output from a TIOC terminal (TIOCA_0, TIOCC_0, TIOCA_1) is illustrated.

  As described above, in this embodiment, the timer counters TCNT_0 to TCNT_2 of the channels 0 to 2 are synchronously cleared at the time of a compare match of TGRA_0 set to the fixed value 1140. Therefore, each timer counter TCNT functions as a 1140 base counter that circulates from 0 to 1139. On the other hand, since the count clock of the timer counter TCNT is 25 MHz (period 40 nS), the timer counter circulates with 45.6 μS (= 1140 * 40 nS) as one period (control period T), and PWM control is performed. The carrier frequency is about 22 KHz.

  As described above, TGRA_0 to TGRD_0 (general registers A, B, C, and D) of channel 0 are generated when TGRA (TGRA_0) of channel 0 is compared (that is, when each timer counter TCNT is synchronously cleared). Due to the interrupt, 1140, N1 * Ton, 380, 380 * N2 * Ton are written by the CPU core 30, respectively. Similarly, 760, 760 + N3 * Ton are written in TGRA_1 to TGRB_1 (general registers A and B) of channel 1 due to an interrupt generated at the time of a compare match of TGRA (TGRA_0) of channel 0.

  Due to the above settings, TIOCA_0 (the TIOCA terminal of channel 0) rises to the H level as the timer counter TCNT is cleared. Thereafter, when the timer counter TCNT_0 of the channel 0 advances and coincides with N1 * Ton which is the value of TGRB_0 (the general register B of the channel 0), the TIOCA_0 falls to the L level.

  The same applies to the other TIOC terminals, and TIOC_0 (TIOCC terminal of channel 0) rises to the H level at the timing of timer counter TCNT_0 = 380 by the TGRC_0 compare match, and at the timing of timer counter TCNT_0 = 380 + N1 * Ton. It falls to L level by TGRD_0 compare match. Further, TIOCA_1 (TIOCA terminal of channel 1) rises to H level at the timing of timer counter TCNT_1 = 760 by the TGRA_1 compare match, and goes to L level at the timing of timer counter TCNT_1 = 760 + N3 * Ton at the timing of TGRB_1. Fall.

  Therefore, PWM waves with appropriately increased or decreased pulse widths (N1 * Ton, N2 * Ton, N3 * Ton) are output with a phase delayed by 120 degrees from TIOCA_0, TICC_0, and TIOCA_1 which are output terminals of each channel. Therefore, the switching elements Q1 to Q3 perform the ON operation based on the three-phase PWM waves whose phases are shifted. The control on time Ton is a value calculated in the immediately preceding control cycle.

  FIG. 7B illustrates an interrupt process of the CPU core 30 based on a compare match of TGRA_0 (channel 0 general register A). As described above, at the first timing of each control cycle (at the time of a TGRA_0 compare match), the CPU core 30 writes an appropriate set value to each general register of the MTU 33.

  FIG. 7C illustrates the AD conversion start trigger by the compare match of TGRA_0 (channel 0 general register A). As shown in the figure, at the first timing of each control cycle (when a compare match of TGRA_0), an AD conversion start trigger is supplied from the MTU 33 to the AD conversion unit 32, and in response, the A / D converters AD1 to AD3 are continuously provided. The AD conversion operation is executed in this order by operating in the scan mode. When the A / D converter AD4 finishes AD conversion, it outputs an AD conversion end interrupt signal to the CPU core 30.

  Further, at the time of a TGARA_2 compare match, an AD conversion start trigger is supplied from the MTU 33 to the AD conversion unit 32, and in response to this, any of the A / D converters AD4 to AD6 operates in a single mode, and an AD conversion operation is performed. Execute. When the corresponding A / D converter ADj finishes AD conversion, it outputs an AD conversion end interrupt signal to the CPU core 30.

  As described above, the MTU 33 cooperates with the CPU core 30 and the AD conversion unit 32 to output three PWM waves whose phases are different by 120 degrees with a control period T of about 50 μS. 8 to 9 are flowcharts showing the processing contents of the one-chip microcomputer 3 that realizes the control operation of FIG. 3 includes a PWM wave output operation (see FIG. 8A) repeated by the MTU 33 every 45.6 μS, and an AD conversion end interrupt AD_INT (FIG. 8 (FIG. 8) activated when the AD conversion operation is completed. b)), interrupt processing CM_INT (FIG. 9) repeated every 45.6 μs in synchronization with the operation of the MTU 33, and timer interrupt TM_INT (FIG. 10) started every 1 mS. .

<Operation of MTU 33 (FIG. 8A)>
Hereinafter, the operation content of the MTU 33 is confirmed based on FIG. The timer counter TCNT is cleared synchronously every 45.6 μS (= 1140 count clocks) by a TRGA_0 compare match. At the time of clearing, the CPU core 30 is interrupted, an AD conversion start trigger is supplied to the AD conversion unit 33, and the A / D converters AD1 to AD3 start AD conversion operations in the continuous scan mode. When the AD conversion process by the TRGA_0 compare match is completed, an AD conversion end interrupt is generated for the CPU core.

  In parallel with these operations, three types of PWM waves PWM1 to PWM3 are automatically generated after the timer counter TCNT is cleared. Also, at the time of a TGARA_2 compare match, an AD conversion start trigger is supplied to the AD converter 33, and any of the A / D converters AD4 to AD6 starts an AD conversion operation. Also in this case, an AD conversion end interrupt is generated for the CPU core after AD conversion ends.

<AD conversion end interrupt AD_INT>
As described above, when the AD conversion operation based on the TGRA_0 compare match ends or the AD conversion operation based on the TGRA_2 compare match ends, the interrupt processing AD_INT shown in FIG. 8B is started. In the interrupt process AD_INT, first, the value of the management flag FLG is checked (ST1). The management flag FLG is a flag for separating the above-described two types of AD conversion end interrupts, and FLG = 0 in the initial state.

  Here, the case of FLG = 0 means that the current interrupt request is caused by the end of the AD conversion operation in the continuous scan mode due to the TGRA_0 compare match. Therefore, when FLG = 0, the conditions for generating the next AD conversion start trigger, the conversion mode to be set to the single mode, and the A / D converter to be started by the conversion start trigger are set (ST2).

  In the case of this embodiment, the AD conversion start trigger generation condition is specifically TGRA_2 compare match, and an A / D converter that operates in a single mode is AD4 → AD5 → AD6 → AD4. To change cyclically. Which A / D converter is to be operated is managed by a variable j having an initial value = 4. Accordingly, appropriate setting data is written in the AD converter 32 so as to satisfy these conditions.

  As described above, when the initial setting for the next AD conversion start trigger is completed, the conversion operation of the AD conversion operation in the continuous scan mode that has already been completed is acquired. Specifically, the conversion values ad1 to ad3 obtained by the A / D converters AD1 to AD3 are obtained from the data register ADDR of the AD conversion unit 32 and temporarily stored in the memory (ST3). Then, the value of the management flag FLG is rewritten to 1 to finish the interrupt process (ST4).

  The processing in the case of FLG = 0 has been described above. However, if it is determined in the processing of step ST1 that FLG = 1, this interrupt is sent to any of the three A / D converters (AD4 to AD6). This is a conversion end interrupt. Therefore, the conversion value adj of the A / D converter ADj determined by the variable j is acquired from the data register ADDR of the AD conversion unit 32 and temporarily stored in the memory (ST5). Each time the conversion values ad4, ad5, ad6 reach the predetermined number N, the respective average values Σad4 / N, Σad5 / N, Σad6 / N are calculated and stored, and when the PWM duties N1 to N3 are updated ( ST22) A plurality of average values are read out, and overall average values AV (ad4), AV (ad5), and AV (ad6) are calculated for each conversion value. Since the conversion values ad4, ad5, and ad6 are proportional to the charging peak values Ip1, Ip2, and Ip3 of the coil current, AV (ad4), AV (ad5), and AV (ad6) are hereinafter referred to as AV (Ip1 ), AV (Ip2), AV (Ip3). AV means an average calculation value.

  When the processing of step ST5 as described above is completed, the variable j is then circulated in the range of 4 to 6 (ST6 to ST8), and the value of the management flag FLG is rewritten to 0 (ST9). Finally, at the next TGRA_0 compare match, an appropriate set value is written in the MTU 33 so as not to generate an AD conversion start trigger, and the interrupt process is completed (ST10). In this embodiment, such processing is provided when the control cycle repeats a “data acquisition cycle” and an “arithmetic cycle”, and the “arithmetic cycle” next to the “data acquisition cycle” in which an AD conversion end interrupt occurs. This is because the AD conversion process is unnecessary.

  FIG. 9 is a flowchart showing a CH0 interrupt processing program based on a TGRA_0 compare match. Also here, the value of the management flag CONV is first checked (ST20). The management flag CONV is a flag indicating whether the current operation cycle is “calculation cycle: CONV = 1” or “data acquisition cycle: CONV = 0”, and the initial value is set to CONV = 0.

  If CONV = 0, it is next determined whether or not the update timing of the PWM duties N1 to N3 has been reached (ST21). The update timing is set to about several seconds, for example. If the update timing has been reached, the average values Σad4 / N, Σad5 / N, and Σad6 / N accumulated in the processing of step ST5 are read from the memory, and the overall average value AV ( Ip1), AV (Ip2), AV (Ip3) are calculated, and PWM duties N1 to N3 are reset (ST22).

  Specifically, N1 * AV (Ip1), N2 * AV (based on the overall average values AV (Ip1), AV (Ip2), AV (Ip3) and the PWM duties N1, N2, N3 so far. Ip2), N3 * AV (Ip3) are calculated, and the median value MID is specified (ST221). Based on the specified median MID, N1 ← MID / (N1 * AV (Ip1)), N2 ← MID / (N2 * AV (Ip2)), N3 ← MID / (N3 * AV (Ip3)) From the above calculation, the PWM duties N1 to N3 are updated (ST222). Since the initial values of the PWM duties N1 to N3 are all 1, N1 ← MID / AV (Ip1), N2 ← MID / AV (Ip2), N3 ← MID / AV (Ip3) in the first update process. (See FIG. 2).

  When the updating of the PWM duties N1 to N3 is completed as described above, the control on time Ton (n) stored in the PWM buffer is then corrected based on the PWM duties N1 to N3 (ST23). Specifically, the control ON time for the switching elements Q1 to Q3 is corrected to N1 * Ton (n), N2 * Ton (n), and N3 * Ton (n).

  Then, a predetermined value is written in each general register of the MTU 33 (ST4). Specifically, as shown in FIG. 6, TGRA_0 = 1140, TGRB_0 = N1 * Ton, TGRC_0 = 380, TGRD_0 = 380 + N2 * Ton, TGRA_1 = 760, TGRB_1 = 760 + N3 * Ton are set. For TGRA_2, any one of N1 * Ton, 380 + N2 * Ton, and 760 + N3 * Ton is written according to the value of variable j (j = 4 to 6) at that time. Then, the value of the management flag CONV is changed from 0 to 1, and the interrupt process is finished (ST25).

  On the other hand, in the process of step ST20, when it is determined that the management flag CONV = 1, the calculation operation of the control on time Ton is executed. First, the output values ad1 and ad4 (input currents to the coil L) of the A / D converters AD1 and AD4 are acquired from the memory, and the input current in the control cycle (n−1) is calculated by averaging (ad1 + ad4) / 2. The average value Iav (n-1) is calculated (ST26). When the average value Iav (n−1) of the input current is obtained, the inductance value of the coil L1 mounted on the circuit is specified based on the current value Iav (n−1) (ST26). As shown in FIG. 11, the inductance value of the coil L1 often changes in accordance with the DC superimposed current (average current) flowing therethrough. Therefore, in this embodiment, the characteristics of the coil L1 mounted on the circuit are stored in advance in the memory, and the inductance value corresponding to the average value Iav (n−1) of the input current is used in each arithmetic expression. I am doing so.

  Subsequently, the output value AD2 (AC input voltage Vac (n−1)) of the A / D converter AD2 is acquired from the memory, and the voltage prediction formula Vac (n) = 2 * Vac (n−1) −Vac (n− Vac (n) is calculated based on 2) (ST27). Further, the output value AD3 (DC output voltage Vdc (n−1)) of the A / D converter AD3 is acquired, and the input current command value Iav (n) is calculated by calculating Iav (n) = β * Vac (n). Is calculated (ST28). Note that. The necessary value of the integration parameter β is updated every 1 mS in the timer interrupt process TM_INT shown in FIG. 10 and stored in an appropriate work area.

  Next, the acquired value ad1 from the A / D converter AD1, the inductance value L of the coil corrected in the process of step ST26, the AC input voltage value Vac (n−1) acquired in the process of step ST27, Based on the control ON time Ton (n-1) and the DC output voltage value Vdc (i) in this control cycle, and based on the discriminant of (Expression 5 ′), the coil charging start current Iv (n−1) Is calculated (ST29). Then, according to the value (whether positive or not) of the coil charging start current Iv (n−1), it is determined whether the control should be controlled as the continuous mode or the discontinuous mode (ST30). As described above, the discriminant of (Expression 5 ″) may be used instead of (Expression 5 ′).

  Here, when Iv (n−1) ≦ 0 and the discontinuous mode is set, Iv (n−1) = 0 is set and the calculation of (Expression 9 ′) or (Expression 9 ″) is performed. Based on the equation, the control ON time Ton (n) is calculated (ST31). On the other hand, if Iv (n−1)> and the continuous mode is set, the control on-time Ton (n) is calculated based on the arithmetic expression of (Expression 14 ′) (Expression 14 ″) (ST32). ).

  Then, on the condition that the calculated control ON time Ton (n) does not exceed the control upper limit value and the control lower limit value, the Ton in the PWM buffer area is set as the control ON time of the next control cycle (n). The value of (n) is set (ST33). The Ton (n) written in the PWM buffer in this way is used at the time of interruption at the start of the next control cycle, and an appropriate set value is written in each general register of the MTU 33.

  However, when the calculated control ON time Ton (n) exceeds the upper limit value or the lower limit value, the control upper limit value or the control lower limit value is set in the PWM buffer. The upper limit value is T / 3 with respect to the control cycle T. In this case, a control upper limit value that is less than T / 3 is used. The reason for providing such a restriction is that if the operation is performed in a state where Ton ≧ T / 3, a plurality of step-up choppers are operated in an overlapping manner, and the object of the present invention such as suppression of heat generation is hindered. is there.

  When the above processing is completed, the management flag CONV is set to 0 (ST34), and various settings are made to generate an AD conversion start trigger at the next TGRA_0 compare match (ST35). This corresponds to the process of step ST10 in FIG. 8 and is for shifting to the “data acquisition cycle” following the “calculation cycle” for executing the processes of steps ST26 to ST33. Specifically, (a) an AD conversion start trigger is generated by a TGRA_0 compare match, and (b) the three A / D converters AD1 to AD3 are operated in the continuous scan mode due to the AD conversion start trigger. (C) Generation of a conversion end interrupt after completion of AD conversion is set.

<Timer interrupt TM_INT>
Next, the timer interrupt TM_INT that is started every 1 mS independently of the above-described AD conversion end interrupt AD_INT will be described with reference to the flowchart of FIG.

  In the timer interrupt TM_INT, first, Vdc (i), which is the output of the A / D converter AD3, is acquired (ST30). Note that the A / D converter AD3 performs an AD conversion operation every 45.6 μS, but the timer interrupt CM_INT acquires an AD converted output DC voltage every 1 mS. Hereinafter, the acquired DC voltage is expressed as Vdc (i).

  Next, the calculation of SUM ← SUM + Vdc (i) is executed, and the acquired value of the output DC voltage Vdc (i) is added to the average calculation buffer SUM in the work area (ST31). Also, the AC input voltage Vac (i), which is the output of the A / D converter AD2, is acquired (ST32), and the AC input voltage Vac (i) and the peak value Vac (pk) stored in the memory are obtained. Contrast (ST33).

  If Vac (i)> Vac (pk), the maximum wave height value Vac (pk) stored in the memory is updated by calculating Vac (pk) ← Vac (i) (ST34). After obtaining the peak value Vac (pk) of the AC input voltage in this way, the counter CT is decremented (−1) (ST35), and it is determined whether or not the counter value CT is zero (ST36).

  Here, when the counter value CT becomes CT = 0, the average value of the output DC voltage Vdc (i) is obtained by multiplying the value of the average calculation buffer SUM by 1/500 (ST37). Then, the DC output voltage Vdc is specified by this average value (ST38).

  When the DC output voltage Vdc is obtained in this way, the values of the average calculation buffer SUM and the counter CT are initialized (ST39), and the reference value (target value) Vo of the output DC voltage is calculated by calculating Vo ← Vac (pk) + α. Is calculated (ST40). α is a boosted amount in the coil L when compared with the peak value Vac (pk) of the input AC voltage. Then, the difference between the output reference voltage Vo and the output average voltage Vdc obtained from the measured value is calculated (ST41). Specifically, Verr (i) ← Vo−Vdc is calculated.

  Based on the above result, the command value β by PI control is calculated, and the timer interrupt process CM_INT is ended (ST42). Here, the calculation of the command value β is based on the arithmetic expression of β = Verr (i) * Kp + {Verr (i) * Ki + Verr (i−1) ′ * Ki}, where Verr (i−1) ′ * Ki is The integration control value of (i−1) last time, which is a value calculated as Verr (i−1) ′ * Ki = Verr (i−1) * Ki + Verr (i−2) ′ * Ki.

  As described above, in the digital converter 1 according to the embodiment, the three step-up choppers 4a to 4c are connected in parallel, and the switching elements Q1 to Q3 are sequentially turned on with delay, so that the switching elements are distributed and mounted. This makes it possible to effectively disperse the heat generation. In addition, since the control on times N1 * Ton to N3 * Ton are appropriately increased or decreased in accordance with the characteristics of the switching elements Q1 to Q3, the capability of each switching element can be utilized to the maximum. Further, not only the switching elements but also the circuit pattern and wiring capability can be optimally utilized, so that the degree of freedom in design can be increased.

Further, since the ripple of the input current is reduced, the capacitor Cin on the input side can be reduced in size. FIG. 12 illustrates this relationship, and shows the relationship between the currents I _{L1 to} I _L3 of the coils _{L1 to L3} and the output current I _ALL of the rectifier circuit 2, which is the sum of these.

  By the way, in said Example, although the collector current of each switching element Q1-Q3 was detected by shunt resistance R1-R3, if the Vce-Ic characteristic of each switching element is utilized, shunt resistance R1-R3 will be abbreviate | omitted. You can also

  FIG. 14 is a circuit diagram showing this modification, and the Vce (collector-emitter voltage) of each switching element Q1 to Q3 is measured by the A / D converters AD4 to AD6 at the fall of each PWM wave PWM1 to PWM3. Is done. Further, Vce1 of the switching element Q1 is measured by the A / D converter AD1 even when the PWM1 wave rises, and the coil charging start current Iv (n−2) is specified.

  As shown in FIG. 15, although the saturation characteristics differ according to the gate voltage Vge applied between the gate terminal and the emitter terminal of the IGBT, it is almost linear in the low current region (about 0 to 30 A) for the switching element. Vce-Ic characteristics. Further, it has been experimentally confirmed that the variation in the Vce-Ic characteristic between the elements is relatively small, and the characteristic variation between the elements can be appropriately calibrated at the time of product shipment. .

  Therefore, in the embodiment of FIG. 14, the collector-emitter voltages Vce1 to Vce3 of the switching element Q are measured at the fall of each of the PWM waves PWM1 to PWM3, and the conversion table TBL is referred to based on the measured values, The coil charging peak currents Ip1 to Ip3 at each timing are specified. This eliminates the need for a shunt resistor, reduces manufacturing costs, and eliminates the problem of wasted power consumption.

As shown in FIG. 14, the collector-emitter voltages Vce1 to Vce3 are supplied to the A / D converters AD1 and AD4 to AD6 through the signal input units IN1 to IN3. The signal input units IN1 to IN3 include a delay circuit DLY. Provided, the input signals (Vce1 to Vce3) are delayed by Ts (see FIG. 14B). Since the delay time Ts is made to coincide with the time delay Ts generated from the start of the control cycle to the time of acquisition of the input signal, in this embodiment, the conversion table TBL is referred to based on the output value ad1 of the AD converter AD1. For example, the coil charging start current Iv (n-2) can be specified, and the coil charging start current Iv (n-1) of the next cycle can be estimated by the following (formula 3).
Iv (n−1) = Iv (n−2) + T / L × [{Vac (n−1) −Vdc (n−1)} + Ton (n−1) × Vdc (n−1)]... (Formula 3)

In this embodiment, for the switching element Q1, the collector-emitter voltage Vce1 is measured at the rise and fall of the PWM1 wave. Therefore, by searching a conversion table TBL, based on the output value ad1 at the rise of the PWM1 wave, it is identified coil charge starting current _{I ST,} a conversion table TBL, based on the output value ad4 during the fall of the PWM wave 1 By searching, the coil peak current I _ED is specified (see FIG. 14B).

Accordingly, the inductance value L of the coil can be calculated as L = Vac × Ton / (I _ED −I _ST ), and accurate calculation is possible by substituting this inductance value into the above (Equation 3). Become. Also, the inductance value calculated by the calculation of L = Vac × Ton / (I _ED −I _ST ) can be used in the calculation of the control ON time Ton.

  The PWM duty N1 to N3 is determined based on the coil charge peak currents Ip1 to Ip3 specified from the measured values ad4 to ad6 from the A / D converters AD4 to AD6, and the control on time of each of the switching elements Q1 to Q3 is determined. Is N1 * Ton, N2 * Ton, N3 * Ton, as in the first embodiment.

  The two embodiments of the present invention have been described in detail above. However, the specific description does not particularly limit the present invention and can be appropriately changed.

  For example, in each embodiment, the number of switching elements is three. However, the number of switching elements is not limited at all, and may be two or four or more. Further, although one switching element is provided corresponding to each of the coils L1 to L3, the coil charging current may be divided into a plurality of switching elements.

  FIG. 13 shows an embodiment in which the charging current of the coil L is shunted to the two switching elements Q1 and Q2, and the PWM duty is determined based on the coil charging peak currents Ip1 and Ip2 of the two elements specified statistically. N1 and N2 are determined. Specifically, for example, N2 = N1 * Ip1 / Ip2 is set with reference to the switching element Q1 (N1 = 1). When the switching element Q2 is used as a reference (N2 = 1), N1 = N2 * Ip2 / Ip1 is set. When three or more switching elements are used, the median value MID may be used as a reference.

  By the way, it is not always necessary to use the coil charging peak current Ip of the switching element to determine the PWM duties N1 to Ni, and the temperature of the switching element may be directly measured. For this temperature measurement, a dedicated element such as a thermistor may be used, or a temperature detection element such as a diode built in the switching element may be used.

  FIG. 16 is a diagram for explaining temperature detection by a diode. Since this built-in diode has a temperature Tch [° C.]-Forward voltage VF characteristic as shown in the figure, it is possible to grasp the heat generation state of each switching element by grasping the forward voltage VF. Become. Therefore, the PWM duty Ni of the switching element with high heat generation is set to Ni <1, while the PWM duty Nj of the switching element with low heat generation is set to Nj> 1, thereby realizing an operation corresponding to each element. be able to.

  Further, in each of the above-described embodiments, the PWM duty Ni is changed during the driving operation. However, the PWM duty Ni may be fixedly determined and written to the ROM based on the test operation at the time of factory shipment. . Alternatively, the PWM duty Ni may be fixedly determined by executing a test operation every time the power is turned on.

It is a circuit block diagram which shows the digital converter which concerns on an Example. It is drawing explaining the principle of operation of this invention. It is a time chart explaining the relationship between a control period and the charging / discharging operation | movement of a coil. It is a block diagram which shows the internal structure of a one-chip microcomputer. It is a block diagram which shows the internal structure of an AD conversion part. It is a block diagram which shows the internal structure of MTU. It is a time chart explaining operation | movement of MTU. It is a flowchart which shows the operation | movement content of MTU and AD conversion interruption. It is a flowchart which shows the operation | movement content of CH0 interruption by a compare match. It is a flowchart which shows the operation | movement content of a timer interruption. It is a characteristic view which shows the relationship between the inductance value of a coil, and an average current. It is drawing explaining reduction of a ripple. It is an example of a circuit which connects a switching element in parallel. It is a circuit block diagram which shows the digital converter which concerns on a modification. The Vce-Ic characteristic of IGBT is illustrated. The characteristic of the diode for heat_generation | fever detection is illustrated.

Explanation of symbols

L1 to L3 Coils Q1 to Q3 Switching element 1 Digital converter 2 Rectifier circuit 3 Computer circuit (one-chip microcomputer)
4a-4c Booster chopper

Claims (10)

A step-up chopper configured by connecting a plurality of n sets of circuits each having a coil and a switching element connected in parallel, a rectifier circuit for supplying an input current to each coil, and PWM control of each switching element in a predetermined control cycle A digital converter configured with a computer circuit to perform,
While determining whether the input current to the coil is a continuous mode that is not interrupted during a control cycle or a discontinuous mode that is interrupted in the middle of a control cycle, the PWM control is executed with a different algorithm based on the determination result,
Each of the switching elements Qi is driven by a PWM wave having a pulse width Ni * Ton corrected according to each characteristic.   2. The digital converter according to claim 1, wherein the switching elements are sequentially driven with a phase shift of 360 / n degrees. A step-up chopper configured by connecting a plurality of n switching elements connected in parallel and a coil, a rectifier circuit that supplies an input current to the coil, and a computer that performs PWM control of the switching elements in a predetermined control cycle A digital converter configured with a circuit,
While determining whether the input current to the coil is a continuous mode that is not interrupted during a control cycle or a discontinuous mode that is interrupted in the middle of a control cycle, the PWM control is executed with a different algorithm based on the determination result,
Each of the switching elements Qi is driven by a PWM wave having a pulse width Ni * Ton corrected according to each characteristic.   The digital converter according to any one of claims 1 to 3, wherein a DC output voltage of the step-up chopper is obtained from a single capacitor that is charged when each switching element is turned off.   Whether the current mode is the continuous mode or the discontinuous mode is determined in the current control cycle by measuring each value of the charging start current of the coil, the AC input voltage to the boost chopper, and the DC output voltage of the boost chopper, and the current control. The digital converter according to claim 1, wherein the digital converter is determined based on a PMW wave control time in a cycle and an inductance value of the coil. The charging start current of the coil is
The digital converter according to claim 5, wherein the digital converter is specified based on a voltage value between an output terminal and a common terminal of the switching element at the timing. The inductance of the coil is
The voltage value between the output terminal and the common terminal of the switching element at the start and end of charging of the coil,
The digital converter of Claim 5 or 6 specified based on the registration value stored beforehand about the voltage-current characteristic of the said switching element. The correction value Ni (i = 1 to n) that defines the pulse width Ni * Ton is:
8. The digital converter according to claim 1, wherein Ni = MID / Ipi is set based on a current value Ipi at the time of OFF transition of each switching element.
MID: average value or median value of Ip1 to Ipn The correction value Ni (i = 1 to n) that defines the pulse width Ni * Ton is:
Claims 1 to 7 updated during the driving operation by calculating Ni = MID / (Ni * TYP (Ipi)) based on the statistical value TYP (Ipi) of the current value Ipi at the OFF transition time of each switching element. The digital converter in any one of.
MID: average value or median value of N1 * TYP (Ip1) to Nn * TYP (Ipn) The correction value Ni (i = 1 to n) that defines the pulse width Ni * Ton is:
The digital converter in any one of Claims 1-7 determined based on the heat_generation | fever state of each said switching element.