JP2009246014A - Manufacturing method of semiconductor device, and semiconductor device - Google Patents

Abstract

In a method of manufacturing a semiconductor device for forming a first conductivity type MOS transistor, a second conductivity type transistor and a MOS capacitor on the same semiconductor substrate, the threshold voltage of the MOS transistor is added without adding a manufacturing process. A MOS capacitor having a stable capacitance in the vicinity is manufactured.
In step (2), boron ions for adjusting the threshold voltage of the NchMOS transistor 9n are simultaneously implanted into the P-type well 3 in the formation region of the NchMOS transistor 9n and the N-type well 5 in the formation region of the MOS capacitor 11. Further, the boron ions are not implanted into the N-type well 5 in the formation region of the Pch MOS transistor 9p, and the impurity ion concentration profiles near the surface of the N-type well 5 are made different between the MOS capacitor 11 and the Pch MOS transistor 9p.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly, to a semiconductor device manufacturing method and a manufacturing method thereof for forming a first conductivity type MOS transistor, a second conductivity type transistor and a MOS capacitor on the same semiconductor substrate. The present invention relates to a semiconductor device formed by.

  The structure of metal (metal) -insulator (semiconductor) -semiconductor is generally called a MIS structure. In the MIS structure, the MOS structure is particularly limited to an oxide (Oxide film). When a gate voltage VG is applied to the gate electrode of the MOS structure, it can be used as a capacitive element, and the MOS structure for such use is called a MOS diode or a MOS capacitor.

  If two impurity ion diffusion layer regions are provided on both sides of the gate electrode of the MOS capacitor, a MOS transistor structure is obtained. However, the MOS capacitor structure can be used as a MOS capacitor by connecting and shorting the source and drain. There is also a MOS capacitor having a structure similar to the MOS transistor structure, in which the semiconductor layer and the source and drain have the same conductivity type (see, for example, Patent Document 1).

Japanese Patent No. 3745951

Usually, the MOS capacitor is formed simultaneously with the MOS transistor formed on the same semiconductor substrate, and has the same structure as the MOS transistor.
FIG. 13 shows the CV characteristic (capacitance-gate voltage characteristic) of the Nch MOS transistor. The vertical axis represents capacity (F (farad)), and the horizontal axis represents gate voltage (V (volt)).

  When the gate voltage is sufficiently negative, there is no depletion layer, and only the capacity of the gate insulating film is obtained. When the gate voltage is around 0 V, the depletion layer spreads, and the gate insulating film and the depletion layer become series capacitance, and the capacitance drops. When the gate voltage is on the plus side, carriers accumulate in the inversion layer and the capacitance increases. Thus, the capacitance of the MOS capacitor changes due to the spread of the depletion layer when a voltage is applied to the gate electrode. In particular, the capacitance decreases near the threshold voltage (Vth) of the MOS transistor. The MOS capacitor having the same conductivity type as the semiconductor layer and the source and drain disclosed in Patent Document 1 also has the same CV characteristic as that shown in FIG.

  Usually, the threshold value of the MOS transistor is less than 1V, and if it is less than 1V, the capacitance is lowered due to the spread of the depletion layer. Therefore, in order to obtain a stable capacity with the conventional MOS capacitor, it was necessary to use it in a gate voltage region of 1 V or more.

In order to obtain a stable capacitance at less than 1 V in the capacitor, for example, there is a method of using a capacitor having a PIP (Poly silicon-Insulator-Poly silicon) structure.
However, since a dedicated process for forming the PIP structure is required, there is a problem that the manufacturing cost increases. Furthermore, since the PIP structure capacitor has a smaller unit capacity than the MOS capacitor, there is a problem that the chip area increases.

  The present invention provides a method for manufacturing a semiconductor device for forming a first conductivity type MOS transistor, a second conductivity type transistor, and a MOS capacitor on the same semiconductor substrate, and a manufacturing process for the semiconductor device formed by the method. Accordingly, an object of the present invention is to manufacture a MOS capacitor having a stable capacitance near the threshold voltage of the MOS transistor.

A first aspect of a method for manufacturing a semiconductor device according to the present invention includes the following steps in a method for manufacturing a semiconductor device for forming a first conductivity type MOS transistor, a second conductivity type transistor, and a MOS capacitor on the same semiconductor substrate. A method of manufacturing a semiconductor device including (A) to (E) in that order.
(A) forming a first conductive type semiconductor layer in which a second conductive type MOS transistor is formed and a second conductive type semiconductor layer in which a first conductive type MOS transistor and a MOS capacitor are formed on the same semiconductor substrate;
(B) Impurity ions for adjusting the threshold voltage of the second conductivity type MOS transistor are simultaneously applied to the first conductivity type semiconductor layer in the second conductivity type MOS transistor formation region and the second conductivity type semiconductor layer in the MOS capacitor formation region. The impurity ions for adjusting the threshold voltage of the second conductivity type MOS transistor are not implanted into the second conductivity type semiconductor layer of the first conductivity type MOS transistor formation region and the MOS capacitor formation region and the first conductivity type are not implanted. Differentiating impurity ion concentration profiles near the surface of the second conductivity type semiconductor layer in the one conductivity type MOS transistor formation region;
(C) After forming a gate insulating film on the first conductive type semiconductor layer and the second conductive type semiconductor layer, on the gate insulating film in the first conductive type MOS transistor forming region and the MOS capacitor forming region. The first conductivity type gate electrode made of the first conductivity type semiconductor film is simultaneously formed, and the second conductivity type gate electrode made of the second conductivity type semiconductor film is formed on the gate insulating film in the second conductivity type MOS transistor formation region. Forming a process,
(D) At the same time as forming the first conductivity type MOS transistor by forming the first conductivity type source and the first conductivity type drain in the second conductivity type semiconductor layer of the first conductivity type MOS transistor formation region, the MOS A MOS capacitor is formed by forming a first conductivity type source and a first conductivity type drain in the second conductivity type semiconductor layer of the capacitor formation region, and separately, the first conductivity type of the second conductivity type MOS transistor formation region. Forming a second conductivity type MOS transistor by forming a second conductivity type source and a second conductivity type drain in the semiconductor layer;
(E) forming an interlayer insulating film covering the first conductive type MOS transistor, the second conductive type transistor and the MOS capacitor; forming a contact hole in the interlayer insulating film; and in the contact hole and the interlayer insulating film Forming a metal wiring made of a metal material on the MOS capacitor to short-circuit the first conductivity type source and the first conductivity type drain of the MOS capacitor;

  In the claims and the specification of the present application, the first conductivity type means P type or N type, and the second conductivity type means N type or P type opposite to the first conductivity type. The first conductivity type MOS transistor means a PchMOS transistor or an NchMOS transistor, and the second conductivity type transistor means an NchMOS transistor or a PchMOS transistor.

  A first aspect of the semiconductor device according to the present invention is formed by the first aspect of the method of manufacturing a semiconductor device according to the present invention, wherein the second conductivity type includes the MOS capacitor and the first conductivity type MOS transistor. The impurity ion concentration profiles near the surface of the semiconductor layer are different.

  In the first aspect of the semiconductor device manufacturing method of the present invention and the first mode of the semiconductor device, the impurity ion concentration profiles in the vicinity of the surface of the second conductivity type semiconductor layer are different between the MOS capacitor and the first conductivity type MOS transistor. As a result, the CV characteristics of the MOS capacitor and the first conductivity type MOS transistor are different from each other, and the MOS capacitor has a stable capacitance near the threshold voltage of the first conductivity type MOS transistor.

  Further, the method of making the impurity ion concentration profile near the surface of the second conductivity type semiconductor layer different between the MOS capacitor and the first conductivity type MOS transistor is the first step of the second conductivity type MOS transistor formation region in the step (B). When the impurity ions for adjusting the threshold voltage of the second conductivity type MOS transistor are implanted into the conductive semiconductor layer, the impurity ions for adjusting the threshold voltage are simultaneously implanted into the second conductivity type semiconductor layer in the MOS capacitor forming region. In addition, since the threshold voltage adjusting impurity ions are not implanted into the second conductive semiconductor layer in the first conductive MOS transistor formation region, the manufacturing process does not increase. .

  In the first aspect of the method for manufacturing a semiconductor device of the present invention, the first step may be performed in place of the step (B) or in addition to the step (B) between the step (A) and the step (C). Impurity ions for adjusting the threshold voltage of the first conductivity type MOS transistor are implanted into the second conductivity type semiconductor layer in the conductivity type MOS transistor formation region, and the first conductivity type semiconductor in the second conductivity type MOS transistor formation region The impurity ions for adjusting the threshold voltage of the first conductivity type MOS transistor are not implanted into the second conductivity type semiconductor layer of the layer and the MOS capacitor formation region, and the MOS capacitor formation region and the first conductivity type MOS are not implanted. You may make it perform the process (B ') which makes the impurity ion concentration profile near the surface of the said 2nd conductivity type semiconductor layer differ in a transistor formation area. Also in this aspect, the impurity ion concentration profiles in the vicinity of the surface of the second conductivity type semiconductor layer can be made different between the MOS capacitor and the first conductivity type MOS transistor without increasing the number of manufacturing steps.

  In the step (D), the first conductivity type MOS and the first conductivity type drain are formed in the second conductivity type semiconductor layer of the first conductivity type MOS transistor formation region to form the first conductivity type MOS. When the transistor is formed, the first conductivity type source and the first conductivity type drain are not formed in the MOS capacitor formation region, and the first conductivity type semiconductor layer in the second conductivity type MOS transistor formation region is not formed. At the same time when the second conductivity type source and the second conductivity type drain are formed, the second conductivity type source and the second conductivity type drain are formed in the second conductivity type semiconductor layer of the MOS capacitor formation region to form a MOS capacitor. In the step (E), the second conductive type source and the second conductive type drain of the MOS capacitor are short-circuited by the metal wiring. It may be. The CV characteristics are also different from each other by changing the source and drain conductivity types of the MOS capacitor and the first conductivity type MOS transistor.

  In the step (C), the gate electrode of the MOS capacitor is formed with a second conductivity type instead of the first conductivity type simultaneously with the second conductivity type gate electrode of the second conductivity type MOS transistor. You may do it. The CV characteristics are also different from each other by changing the conductivity type of the gate electrode between the MOS capacitor and the first conductivity type MOS transistor.

A second aspect of the method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device for forming a first conductivity type MOS transistor, a second conductivity type transistor, and a MOS capacitor on the same semiconductor substrate. A method for manufacturing a semiconductor device including the steps (A) to (D) in that order.
(A) forming a first conductive type semiconductor layer in which a second conductive type MOS transistor is formed and a second conductive type semiconductor layer in which a first conductive type MOS transistor and a MOS capacitor are formed on the same semiconductor substrate;
(B) After forming a gate insulating film on the first conductive type semiconductor layer and the second conductive type semiconductor layer, a second insulating layer is formed on the gate insulating film in the second conductive type MOS transistor forming region and the MOS capacitor forming region. Forming a second conductivity type gate electrode made of a two conductivity type semiconductor film, and forming a first conductivity type gate electrode made of the first conductivity type semiconductor film on the gate insulating film in the first conductivity type MOS transistor formation region; ,
(C) forming a second conductivity type source and a second conductivity type drain in the first conductivity type semiconductor layer of the second conductivity type MOS transistor formation region, and separately forming the first conductivity type MOS transistor formation region in the first conductivity type; The first conductive type source and the first conductive type drain are formed in the two conductive type semiconductor layer to form the first conductive type MOS transistor, and at the same time, the first conductive type is formed in the second conductive type semiconductor layer in the MOS capacitor forming region. Forming a MOS source by forming a type source and a first conductivity type drain;
(D) forming an interlayer insulating film covering the first conductive type MOS transistor, the second conductive type transistor and the MOS capacitor, forming a contact hole in the interlayer insulating film, and in the contact hole and on the interlayer insulating film; Forming a metal wiring made of a metal material to short-circuit the first conductivity type source and the first conductivity type drain of the MOS capacitor.

  According to a second aspect of the semiconductor device of the present invention, the MOS capacitor includes the second conductivity type gate electrode made of a second conductivity type semiconductor film, and the first conductivity type MOS transistor consists of a first conductivity type semiconductor film. The first conductivity type gate electrode is provided.

  In the second aspect of the semiconductor device manufacturing method of the present invention and the second embodiment of the semiconductor device, the conductivity type of the gate electrode differs between the MOS capacitor and the first conductivity type MOS transistor. As a result, the CV characteristics of the MOS capacitor and the first conductivity type MOS transistor are different from each other, and the MOS capacitor has a stable capacitance near the threshold voltage of the first conductivity type MOS transistor.

  Further, the method of making the conductivity type of the gate electrode different between the MOS capacitor and the first conductivity type MOS transistor is that the MOS transistor is formed at the same time as the second conductivity type gate electrode of the second conductivity type MOS transistor is formed in the step (B). Since the process is performed by forming the second conductivity type gate electrode of the capacitor, the manufacturing process does not increase.

  In the second aspect of the method for manufacturing a semiconductor device of the present invention, in the step (C), the first conductivity type source and the first conductivity are formed on the second conductivity type semiconductor layer in the first conductivity type MOS transistor formation region. When the first conductivity type MOS transistor is formed by forming the type drain, the first conductivity type source and the first conductivity type drain are not formed in the MOS capacitor formation region, but the second conductivity type MOS is formed. The second conductivity type source is formed in the second conductivity type semiconductor layer of the MOS capacitor formation region simultaneously with the formation of the second conductivity type source and the second conductivity type drain in the first conductivity type semiconductor layer of the transistor formation region. And a second conductivity type drain is formed to form a MOS capacitor, and in the step (D), the second conductivity type source of the MOS capacitor is formed by metal wiring. May be short fine said second conductivity type drain. The CV characteristics are also different from each other by changing the source and drain conductivity types of the MOS capacitor and the first conductivity type MOS transistor.

In the first aspect of the method for manufacturing a semiconductor device of the present invention, in step (B), the second conductivity type semiconductor layer in the second conductivity type MOS transistor formation region and the second conductivity type semiconductor layer in the MOS capacitor formation region are subjected to the second conductivity. Impurity ions for adjusting the threshold voltage of the MOS transistor are implanted at the same time, and the impurity ions for adjusting the threshold voltage of the second conductivity type MOS transistor are implanted into the second conductivity type semiconductor layer of the first conductivity type MOS transistor formation region. The impurity ion concentration profiles in the vicinity of the surface of the second conductivity type semiconductor layer are made different between the MOS capacitor formation region and the first conductivity type MOS transistor formation region.
According to a first aspect of the semiconductor device of the present invention, the surface of the second conductivity type semiconductor layer is formed by the first aspect of the method of manufacturing a semiconductor device of the present invention and includes a MOS capacitor and a first conductivity type MOS transistor. The impurity ion concentration profiles in the vicinity were made different.
As described above, in the first aspect of the method for manufacturing a semiconductor device and the first embodiment of the semiconductor device of the present invention, the MOS capacitor and the first conductivity type MOS transistor can form the second conductivity type semiconductor layer without increasing the number of manufacturing steps. Since the impurity ion concentration profiles in the vicinity of the surface are different, the CV characteristics of the MOS capacitor and the first conductivity type MOS transistor can be made different from each other. A stable capacity can be provided near the value voltage.

  In the first aspect of the method for manufacturing a semiconductor device of the present invention, a first conductivity type MOS transistor is formed between step (A) and step (C) instead of step (B) or in addition to step (B). Impurity ions for adjusting the threshold voltage of the first conductivity type MOS transistor are implanted into the second conductivity type semiconductor layer in the region, and the first conductivity type semiconductor layer and the MOS capacitor formation region in the second conductivity type MOS transistor formation region are implanted. The second conductivity type semiconductor layer is not implanted with impurity ions for adjusting the threshold voltage of the first conductivity type MOS transistor, and the surface of the second conductivity type semiconductor layer is formed in the MOS capacitor formation region and the first conductivity type MOS transistor formation region. You may make it perform the process (B ') which changes the impurity ion concentration profile of the vicinity. This also makes it possible to make the impurity ion concentration profiles near the surface of the second conductivity type semiconductor layer different between the MOS capacitor and the first conductivity type MOS transistor without increasing the number of manufacturing steps. Further, when the step (B ′) is performed in addition to the step (B), the CV characteristics can be made different from each other in the MOS capacitor and the first conductivity type MOS transistor. A more stable capacitance can be provided near the threshold voltage of the MOS transistor.

  In the first aspect of the method for manufacturing a semiconductor device of the present invention, in step (D), the first conductivity type source and the first conductivity type drain are provided in the second conductivity type semiconductor layer of the first conductivity type MOS transistor formation region. When forming the first conductivity type MOS transistor, the first conductivity type source and the first conductivity type drain are not formed in the MOS capacitor formation region, but the first conductivity type of the second conductivity type MOS transistor formation region is not formed. The second conductivity type source and the second conductivity type drain are formed in the semiconductor layer, and at the same time, the second conductivity type source and the second conductivity type drain are formed in the second conductivity type semiconductor layer in the MOS capacitor formation region to form the MOS capacitor. In step (E), the second conductivity type source and the second conductivity type drain of the MOS capacitor may be short-circuited by the metal wiring. By differentiating the source and drain conductivity types of the MOS capacitor and the first conductivity type MOS transistor, the CV characteristics of the MOS capacitor and the first conductivity type MOS transistor can be made greatly different from each other. A more stable capacitance can be provided in the vicinity of the threshold voltage of the first conductivity type MOS transistor.

  Further, in the first aspect of the method for manufacturing a semiconductor device of the present invention, in the step (C), the second conductivity type instead of the first conductivity type is used as the gate electrode of the MOS capacitor in the second conductivity type MOS transistor. It may be formed simultaneously with the second conductivity type gate electrode. By differentiating the conductivity type of the gate electrode between the MOS capacitor and the first conductivity type MOS transistor, the CV characteristics can be further greatly different between the MOS capacitor and the first conductivity type MOS transistor. A more stable capacitance can be provided in the vicinity of the threshold voltage of the one conductivity type MOS transistor.

In the second aspect of the method of manufacturing a semiconductor device of the present invention, after forming a gate insulating film on the first conductive type semiconductor layer and the second conductive type semiconductor layer in the step (B), the second conductive type MOS transistor is formed. A second conductive type gate electrode made of a second conductive type semiconductor film is formed on the gate insulating film in the forming region and the MOS capacitor forming region, and the first conductive type semiconductor is formed on the gate insulating film in the first conductive type MOS transistor forming region. A first conductivity type gate electrode made of a film was formed.
According to a second aspect of the semiconductor device of the present invention, the MOS capacitor is formed by the second aspect of the method of manufacturing a semiconductor device of the present invention, and the MOS capacitor includes a second conductivity type gate electrode made of a second conductivity type semiconductor film. The first conductivity type MOS transistor includes a first conductivity type gate electrode made of a first conductivity type semiconductor film.
Thus, in the second aspect of the semiconductor device manufacturing method of the present invention and the second embodiment of the semiconductor device, the conductivity type of the gate electrode differs between the MOS capacitor and the first conductivity type MOS transistor without increasing the number of manufacturing steps. Therefore, the CV characteristics of the MOS capacitor and the first conductivity type MOS transistor can be made different from each other, and the MOS capacitor can have a stable capacitance near the threshold voltage of the first conductivity type MOS transistor. be able to.

  In the second aspect of the semiconductor device manufacturing method of the present invention, in step (C), a first conductivity type source and a first conductivity type drain are formed in the second conductivity type semiconductor layer of the first conductivity type MOS transistor formation region. When forming the first conductivity type MOS transistor, the first conductivity type source and the first conductivity type drain are not formed in the MOS capacitor formation region, and the first conductivity type semiconductor layer in the second conductivity type MOS transistor formation region is not formed. Forming a second conductivity type source and a second conductivity type drain simultaneously with forming a second conductivity type source and a second conductivity type drain in the second conductivity type semiconductor layer of the MOS capacitor formation region to form a MOS capacitor. In the step (D), the second conductivity type source and the second conductivity type drain of the MOS capacitor may be short-circuited by the metal wiring. By differentiating the source and drain conductivity types of the MOS capacitor and the first conductivity type MOS transistor, the CV characteristics of the MOS capacitor and the first conductivity type MOS transistor can be made greatly different from each other. A more stable capacitance can be provided in the vicinity of the threshold voltage of the first conductivity type MOS transistor.

FIG. 1 is a schematic process cross-sectional view for explaining an embodiment of a first aspect of a method for manufacturing a semiconductor device. FIG. 1 (5) shows an embodiment of the first aspect of the semiconductor device. The parenthesized numerals (1) to (5) in FIG. 1 correspond to the steps (1) to (5) described below.
First, an embodiment of the first aspect of the semiconductor device will be described with reference to FIG.

  For example, a P-type well (PW, first conductive semiconductor layer) 3 and an N-type well (NW, second conductive semiconductor layer) 5 are formed on a P-type silicon substrate (Psub) 1 having a resistivity of 20Ω (ohms). Has been. On the surface of the P-type well 3 and the N-type well 5, for example, a field oxide film 7 having a film thickness of 500 nm (nanometer) is used. The field oxide film 7 defines an Nch MOS transistor (second conductivity type MOS transistor) 9n formation region in the P type well 3, and an MOS capacitor 11 formation region and a Pch MOS transistor (first conductivity type MOS transistor) in the N type well 5. ) A 9p formation region is defined.

  On the P-type well 3 in the formation region of the Nch MOS transistor 9n, for example, an N-type gate made of an N-type polysilicon film (second conductivity type semiconductor film) through a gate oxide film (gate insulating film) 13a having a thickness of 6 nm, for example. An electrode (second conductivity type gate electrode) 15n is formed. The N-type gate electrode 15n is formed by a laminated film of an N-type polysilicon film and tungsten silicide, but FIG. 1 shows the N-type polysilicon film and tungsten silicide integrally. An N-type source and an N-type drain (second conductivity-type source and second conductivity-type drain) are sandwiched between the P-type well 3 in the formation region of the Nch MOS transistor 9n with the N-type gate electrode 15n being viewed from above. A type high concentration diffusion layer (N +) 17n is formed. Thus, an Nch MOS transistor 9n is formed.

  On the N-type well 5 in the formation region of the MOS capacitor 11, for example, a P-type gate electrode (first conductive type film) made of a P-type polysilicon film (first conductive type semiconductor film) through a gate oxide film 13b having a film thickness of 13 nm, for example. Type gate electrode) 15p is formed. The P-type gate electrode 15p is formed by a laminated film of a P-type polysilicon film and tungsten silicide, but FIG. 1 shows the P-type polysilicon film and tungsten silicide integrally. A P-type source and a P-type drain (first conductivity type source and first conductivity type drain) are formed by sandwiching a P-type gate electrode 15p as viewed from above the N-type well 5 in the formation region of the MOS capacitor 11. A type high-concentration diffusion layer (P +) 17p is formed. Thereby, the MOS capacitor 11 is formed.

  A P-type gate electrode 15p made of a P-type polysilicon film is formed on the N-type well 5 in the formation region of the Pch MOS transistor 9p via a gate oxide film 13b. A P-type high-concentration diffusion layer 17p constituting a P-type source and a P-type drain is formed in the N-type well 5 in the formation region of the Pch MOS transistor 9p with the P-type gate electrode 15p interposed therebetween as viewed from above. As a result, a PchMOS transistor 9p is formed.

  An interlayer insulating film 19 is formed to cover the formation region of the Nch MOS transistor 9n, the formation region of the Pch MOS transistor 9p, and the formation region of the MOS capacitor 11. Contact holes are formed in the interlayer insulating film 19. A metal wiring 21 made of a metal material is formed in the contact hole and on the interlayer insulating film 19. The two P-type high concentration diffusion layers 17p, 17p of the MOS capacitor 11 are connected by a metal wiring 21 and are short-circuited.

  In this embodiment, the impurity ion concentration profiles in the vicinity of the surface of the N-type well 5 under the gate oxide film 13b are different between the MOS capacitor 11 and the Pch MOS transistor 9p.

An embodiment of the first aspect of the semiconductor device manufacturing method will be described with reference to FIG.
(1) For example, a P-type well 3 having a boron ion concentration appropriate for forming the NchMOS transistor 9n and a phosphorus ion concentration appropriate for forming the PchMOS transistor 9p on the P-type silicon substrate 1 having a resistivity of 20Ω. The N-type well 5 is formed by a normal method. A field oxide film 7 is formed on the surfaces of the P-type well 3 and the N-type well 5 to use the elements. Here, BF ₂ ions are implanted into the formation region of the Nch MOS transistor 9n under the condition of an acceleration energy of 180 KeV and a dose of 1.0 × 10 ¹³ / cm ² for forming the P-type well 3 by ion implantation. In order to form the N-type well 5, phosphorus ions are implanted into the formation region of the Pch MOS transistor 9p and the MOS capacitor 11 under the condition of an acceleration energy of 180 KeV and a dose amount of 4.0 × 10 ¹² / cm ² . Thermal diffusion treatment was performed under conditions of 60 minutes. The field oxide film 7 is formed by a normal LOCOS (Local Oxidation of Silicon) method.

(2) Photoresist technology is used to form a photoresist 23 which covers the formation region of the Pch MOS transistor 9p and has openings in the formation region of the Nch MOS transistor 9n and the MOS capacitor 11. Boron ions for adjusting the threshold voltage of the Nch MOS transistor 9n are formed in the P type well 3 in the formation region of the Nch MOS transistor 9n and the N type well 5 in the formation region of the MOS capacitor 11 by the ion implantation method using the photoresist 23 as a mask. Inject at the same time. Here, since the N-type well 5 in the formation region of the PchMOS transistor 9p is covered with the photoresist 23, boron ions are not implanted into the N-type well 5 in the formation region of the PchMOS transistor 9p. For example, boron ions for threshold voltage adjustment are implanted under the conditions that the implantation type is BF ₂ ions, the acceleration energy is 80 KeV, and the dose is 4.0 × 10 ¹² / cm ² .

(3) The photoresist 23 is removed. A pre-gate oxide film is formed by performing a thermal oxidation process. The pre-gate oxide film in the formation region of the Nch MOS transistor 9n is removed by photolithography and wet etching techniques. In a state where the pre-gate oxide film in the formation region of the Pch MOS transistor 9p and the MOS capacitor 11 remains, a thermal oxidation process is performed to form a gate oxide film 13a having a thickness of 6 nm on the P-type well 3 in the formation region of the Nch MOS transistor 9n. A gate oxide film 13b having a film thickness of 13 nm is formed on the N-type well 5 in the formation region of the Pch MOS transistor 9p and the MOS capacitor 11. For example, a polysilicon film having a thickness of 250 nm is deposited, and tungsten silicide having a thickness of 80 nm is deposited thereon. By photolithography and ion implantation, phosphorus ions are implanted into the polysilicon film in the formation region of the Nch MOS transistor 9n to be N-type, and boron ions are implanted into the polysilicon film in the formation region of the Pch MOS transistor 9p and the MOS capacitor 11. Use P type. The silicide film and the polysilicon film are patterned by photolithography and etching techniques, and an N-type gate electrode 15n is formed on the P-type well 3 in the formation region of the NchMOS transistor 9n via the gate oxide film 13a. The PchMOS transistor 9p A P-type gate electrode 15p is formed on the N-type well 5 in the formation region of the MOS capacitor 11 via a gate oxide film 13b. The thickness of the gate oxide film is two kinds here, that is, the gate oxide films 13a and 13b, but may be one kind in the formation region of the Pch MOS transistor 9p, the Nch MOS transistor 9n, and the MOS capacitor 11.

(4) Boron ions for forming P type high concentration diffusion layers 17p and 17p for the P type source and P type drain are formed in the N type well 5 in the formation region of the Pch MOS transistor 9p by photolithography and ion implantation. Simultaneously with the implantation, boron ions for forming P-type high concentration diffusion layers 17p and 17p for the P-type source and P-type drain are implanted into the N-type well 5 in the formation region of the MOS capacitor 11. In addition, arsenic ions for forming N-type high-concentration diffusion layers 17n and 17n for the N-type source and N-type drain in the P-type well 3 in the formation region of the Nch MOS transistor 9n separately by photolithography and ion implantation. Inject. Thereafter, a thermal diffusion process is performed to form a P-type high concentration diffusion layer 17p and an N-type high concentration diffusion layer 17n. For example, boron ions are implanted under the conditions that the implantation type is BF ₂ ions, the acceleration energy is 20 KeV, and the dose is 3.0 × 10 ¹⁵ / cm ² . The arsenic ion implantation conditions are an acceleration energy of 50 KeV and a dose of 4.0 × 10 ¹⁵ / cm ² .

(5) By an ordinary semiconductor device manufacturing process, an interlayer insulating film 19 is formed, a contact hole is formed in the interlayer insulating film 19, and a metal wiring 21 made of a metal material is formed in the contact hole and on the interlayer insulating film. At this time, the P-type high concentration diffusion layers 17p, 17p constituting the P-type source and the P-type drain of the MOS capacitor 11 are short-circuited by the metal wiring 21 so that the MOS capacitor 11 functions as a MOS capacitor.

  In this way, the MOS capacitor 11 including the enhancement type NchMOS transistor 9n having a breakdown voltage of about 3V, the enhancement type PchMOS transistor 9p having a breakdown voltage of about 6V, and the depletion type PchMOS transistor having a breakdown voltage of about 6V was formed.

  In this embodiment, the impurity ion concentration profiles in the vicinity of the surface of the N-type well 5 under the gate oxide film 13b are different between the MOS capacitor 11 and the Pch MOS transistor 9p. The MOS capacitor 11 is a depletion type PchMOS transistor. The depletion type PchMOS transistor forming the MOS capacitor 11 does not operate as a MOS transistor because a larger amount of boron ions are implanted under the gate oxide film 13b and the channel is conducted than the PchMOS transistor 9p. However, since the CV characteristic of the gate capacitance shows a stable capacitance on the minus side, it has a stable capacitance near the threshold voltage of the Pch MOS transistor 9p and is useful as a MOS capacitor.

FIG. 2 is a schematic process cross-sectional view for explaining another embodiment of the first aspect of the semiconductor device manufacturing method. FIG. 2 (5) shows another embodiment of the first aspect of the semiconductor device. The parenthesized numerals (1) to (5) in FIG. 2 correspond to the steps (1) to (5) described below. 2, parts having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.
First, another embodiment of the first aspect of the semiconductor device will be described with reference to FIG.

  A P-type well 3, an N-type well 5, and a field oxide film 7 are formed on a P-type silicon substrate 1. The field oxide film 7 defines the formation region of the Nch MOS transistor 9n, the Pch MOS transistor 9p, and the MOS capacitor 11.

  In this embodiment, the MOS capacitor 11 includes an N-type high concentration diffusion layer (N +) constituting an N-type source and an N-type drain instead of the P-type high concentration diffusion layers 17p and 17p shown in FIG. 17n. The Nch MOS transistor 9n includes a gate oxide film 13b having a thickness of 13 nm in place of the gate oxide film 13a shown in FIG. The structure of the Pch MOS transistor 9p is the same as that shown in FIG.

  In this embodiment, the impurity ion concentration profiles in the vicinity of the surface of the N-type well 5 under the gate oxide film 13b are different between the MOS capacitor 11 and the Pch MOS transistor 9p. Furthermore, the conductivity types of the diffusion layers 17p and 19n constituting the source and drain are different between the MOS capacitor 11 and the Pch MOS transistor 9p.

With reference to FIG. 2, another embodiment of the first aspect of the semiconductor device manufacturing method will be described.
(1) A P-type well 3, an N-type well 5, and a field oxide film 7 are formed on a P-type silicon substrate 1 in the same process as the process (1) described with reference to FIG.

(2) A photoresist 23 is formed in the same process as the process (2) described with reference to FIG. 1B, and the photoresist 23 is used as a mask to form a P-type well in the formation region of the Nch MOS transistor 9n. 3 and boron ions for adjusting the threshold voltage of the Nch MOS transistor 9n are simultaneously implanted into the N-type well 5 in the formation region of the MOS capacitor 11. For example, boron ions for threshold voltage adjustment are implanted under the conditions that the implantation type is BF ₂ ions, the acceleration energy is 15 KeV, and the dose is 8.0 × 10 ¹¹ / cm ² .

(3) The photoresist 23 is removed. A gate oxide film 13b having a thickness of 13 nm is formed on the P-type well 3 in the formation region of the Nch MOS transistor 9n and on the N-type well 5 in the formation region of the Pch MOS transistor 9p and the MOS capacitor 11 by thermal oxidation. In the same step as the step of forming the gate electrodes 15p and 15n in the step (3) described with reference to FIG. 1 (3), the gate oxide film 13b is interposed on the P-type well 3 in the formation region of the NchMOS transistor 9n. N-type gate electrode 15n is formed, and P-type gate electrode 15p is formed on N-type well 5 in the formation region of PchMOS transistor 9p and MOS capacitor 11 via gate oxide film 13b. Here, similarly to the gate oxide films 13a and 13b in the step (3) described with reference to FIG. 1 (3), the gate oxide film thicknesses of the Nch MOS transistor 9n, the MOS capacitor 11, and the Pch MOS transistor 9p are different from each other. It may be allowed.

(4) Arsenic ions for forming N-type high-concentration diffusion layers 17n and 17n for the N-type source and N-type drain are formed in the P-type well 3 in the formation region of the Nch MOS transistor 9n by photolithography and ion implantation. Simultaneously with the implantation, arsenic ions for forming the N-type high concentration diffusion layers 17n and 17n for the N-type source and N-type drain are implanted into the N-type well 5 in the formation region of the MOS capacitor 11. Separately, boron ions for forming P-type high-concentration diffusion layers 17p, 17p for the P-type source and P-type drain are implanted into the N-type well 5 in the formation region of the Pch MOS transistor 9p. Thereafter, a thermal diffusion process is performed to form a P-type high concentration diffusion layer 17p and an N-type high concentration diffusion layer 17n. For example, boron ions are implanted under the conditions that the implantation type is BF ₂ ions, the acceleration energy is 20 KeV, and the dose is 3.0 × 10 ¹⁵ / cm ² . The arsenic ion implantation conditions are an acceleration energy of 50 KeV and a dose of 4.0 × 10 ¹⁵ / cm ² .

(5) By an ordinary semiconductor device manufacturing process, an interlayer insulating film 19 is formed, a contact hole is formed in the interlayer insulating film 19, and a metal wiring 21 made of a metal material is formed in the contact hole and on the interlayer insulating film. At this time, the N-type high concentration diffusion layers 17n and 17n constituting the N-type source and the N-type drain of the MOS capacitor 11 are short-circuited by the metal wiring 21, so that the MOS capacitor 11 functions as a MOS capacitor.

  In this manner, the enhancement type NchMOS transistor 9n having a breakdown voltage of about 6V, the enhancement type PchMOS transistor 9p having a breakdown voltage of about 6V, and the MOS capacitor 11 including a depletion type NchMOS transistor having a breakdown voltage of about 6V were formed.

  In this embodiment, the impurity ion concentration profiles in the vicinity of the surface of the N-type well 5 under the gate oxide film 13b are different between the MOS capacitor 11 and the Pch MOS transistor 9p. Furthermore, the conductivity types of the diffusion layers 17p and 19n constituting the source and drain are different between the MOS capacitor 11 and the Pch MOS transistor 9p. Since the MOS capacitor 11 has the same conductivity type as the substrate, the source and the drain, the source and the drain are conductive, and the MOS capacitor 11 does not operate as a MOS transistor. However, since the CV characteristic of the gate capacitance of the MOS capacitor 11 shows a stable capacitance on the plus side, the MOS capacitor 11 has a stable capacitance near the threshold voltage of the Nch MOS transistor 9n and is useful as a MOS capacitor. is there.

  In the embodiment shown in FIG. 1 and the embodiment shown in FIG. 2, boron ion implantation is performed only once in the N-type well 5 in the formation region of the MOS capacitor 11 in the step (2). If there is a device using boron ion implantation, boron ion implantation may be simultaneously performed on the N-type well 5 in the formation region of the MOS capacitor 11 at the time of boron ion implantation of the device. By doing so, the CV characteristics can be made greatly different between the MOS capacitor 11 and the Pch MOS transistor 9p, and the MOS capacitor 11 can have a more stable capacitance near the threshold voltage of the Pch MOS transistor 9p.

  Further, in the embodiment shown in FIG. 1 and the embodiment shown in FIG. 2, both the MOS capacitor 11 and the Pch MOS transistor 9p are provided with the P-type gate electrode 15p, but the NchMOS transistor 9n is used as the gate electrode of the MOS capacitor 11. An N-type gate electrode formed simultaneously with the N-type gate electrode 15n may be provided.

FIG. 3 is a sectional view schematically showing still another embodiment of the first aspect of the semiconductor device of the semiconductor device.
In this embodiment, as compared with the embodiment shown in FIG. 1 (5), the MOS capacitor 11 includes an N-type gate electrode 15n formed simultaneously with the N-type gate electrode 15n of the Nch MOS transistor 9n. By forming the N-type gate electrode 15n in the formation region of the MOS capacitor 11 simultaneously with the N-type gate electrode 15n of the NchMOS transistor 9n in the step (3) described with reference to FIG. A structure can be obtained.

  According to this embodiment, compared with the embodiment shown in FIG. 1 (5), the CV characteristics can be made different from each other by the MOS capacitor 11 and the Pch MOS transistor 9p. A more stable capacity can be provided in the vicinity of the threshold voltage of 9p.

  It can be easily estimated that the structure in which the MOS capacitor 11 includes the N-type gate electrode 15n formed simultaneously with the N-type gate electrode 15n of the NchMOS transistor 9n can be applied to the embodiment shown in FIG.

  When impurity ion implantation for adjusting the threshold voltage of the Pch MOS transistor 9p is performed, it is performed between the steps (1) and (2) described with reference to FIG. 1 or the step (2). And (3), as shown in FIG. 4, a step of implanting impurity ions, for example, phosphorus ions, for adjusting the threshold voltage of the PchMOS transistor 9p into the N-type well 5 in the formation region of the PchMOS transistor 9p (see FIG. 2 ′) may be performed. At this time, as shown in FIG. 4, if the photoresist 25 having an opening is formed in the formation region of the PchMOS transistor 9p so as to cover the formation region of the NchMOS transistor 9n and the MOS capacitor 11, the formation of the MOS capacitor 11 is performed. By blocking the implantation of phosphorus ions into the N-type well 5 in the region, the impurity ion concentration profiles near the surface of the N-type well 5 can be made different between the MOS capacitor 11 and the Pch MOS transistor 9p.

Further, when the impurity ion implantation for adjusting the threshold voltage of the Nch MOS transistor 9n is not performed, the step (2) described with reference to FIG. 1 (2) is not performed, and the description will be given with reference to FIG. By performing the above step (2 ′), the impurity ion concentration profiles in the vicinity of the surface of the N-type well 5 can be made different between the MOS capacitor 11 and the Pch MOS transistor 9p.
Further, it can be easily estimated that the step (2 ′) described with reference to FIG. 4 can be applied to the embodiment shown in FIG.

Although the MOS capacitor is formed in the N-type well 5 in the above embodiment, it can be formed in the P-type well 3.
FIG. 5 is a schematic process cross-sectional view for explaining still another embodiment of the first aspect of the semiconductor device manufacturing method. FIG. 5 (5) shows still another embodiment of the first mode of the semiconductor device. The parenthesized numerals (1) to (5) in FIG. 5 correspond to the steps (1) to (5) described below. 5, parts having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
First, another embodiment of the first aspect of the semiconductor device will be described with reference to FIG.

  A P-type well 3, an N-type well 5, and a field oxide film 7 are formed on a P-type silicon substrate 1. The field oxide film 7 defines the formation region of the Nch MOS transistor 9n, the Pch MOS transistor 9p, and the MOS capacitor 11. The formation region of the MOS capacitor 11 is provided in the P-type well 3.

  In this embodiment, the MOS capacitor 11 is formed in a P-type well 3 and includes an N-type gate electrode 15n and an N-type high concentration diffusion layer (N +) 17n constituting an N-type source and an N-type drain. . The Nch MOS transistor 9n includes a gate oxide film 13b having a thickness of 13 nm in place of the gate oxide film 13a shown in FIG. The structure of the Pch MOS transistor 9p is the same as that shown in FIG.

  In this embodiment, the MOS capacitor 11 and the Nch MOS transistor 9n have different impurity ion concentration profiles in the vicinity of the surface of the P-type well 3 under the gate oxide film 13b.

Still another embodiment of the first aspect of the semiconductor device manufacturing method will be described with reference to FIG.
(1) A P-type well 3, an N-type well 5, and a field oxide film 7 are formed on a P-type silicon substrate 1 in the same process as the process (1) described with reference to FIG. The formation region of the MOS capacitor 11 is formed in the P-type well 3.

(2) Photoresist technology is used to form a photoresist 27 that covers the formation region of the Pch MOS transistor 9p and the MOS capacitor 11 and has an opening in the formation region of the Nch MOS transistor 9n. Boron ions for adjusting the threshold voltage of the Nch MOS transistor 9n are implanted by ion implantation into the P-type well 3 in the formation region of the Nch MOS transistor 9n using the photoresist 27 as a mask. Here, since the N-type well 5 in the formation region of the PchMOS transistor 9p and the P-type well 3 in the formation region of the MOS capacitor 11 are covered with the photoresist 27, the N-type well 5 and the MOS in the formation region of the PchMOS transistor 9p are covered. Boron ions are not implanted into the P-type well 3 in the formation region of the capacitor 11. Thus, the impurity ion concentration profiles in the vicinity of the surface of the P-type well 3 are different between the MOS capacitor 11 and the Nch MOS transistor 9n. For example, boron ions for threshold voltage adjustment are implanted under the conditions that the implantation type is BF ₂ ions, the acceleration energy is 80 KeV, and the dose is 4.0 × 10 ¹² / cm ² .

(3) The photoresist 27 is removed. By thermal oxidation, a gate oxide film 13b having a thickness of 13 nm is formed on the P-type well 3 in the formation region of the Nch MOS transistor 9n and the MOS capacitor 11 and on the N-type well 5 in the formation region of the Pch MOS transistor 9p. The gate electrodes 15p and 15n are formed in the same process as the formation process of the gate electrodes 15p and 15n in the process (3) described with reference to FIG. However, N-type gate electrodes 15n and 15n are simultaneously formed on the P-type well 3 in the formation region of the Nch MOS transistor 9n and the MOS capacitor 11 via the gate oxide film 13b, and the N-type well 5 in the formation region of the PchMOS transistor 9p. A P-type gate electrode 15p is formed through the gate oxide film 13b. Here, the PchMOS transistor 9p, the MOS capacitor 11, and the NchMOS transistor 9n may have different gate oxide film thicknesses.

(4) Arsenic ions for forming N-type high-concentration diffusion layers 17n and 17n for the N-type source and N-type drain are formed in the P-type well 3 in the formation region of the Nch MOS transistor 9n by photolithography and ion implantation. Simultaneously with the implantation, arsenic ions for forming the N-type high concentration diffusion layers 17n and 17n for the N-type source and N-type drain are implanted into the N-type well 5 in the formation region of the MOS capacitor 11. Separately, boron ions for forming P-type high-concentration diffusion layers 17p, 17p for the P-type source and P-type drain are implanted into the N-type well 5 in the formation region of the Pch MOS transistor 9p. Thereafter, a thermal diffusion process is performed to form a P-type high concentration diffusion layer 17p and an N-type high concentration diffusion layer 17n. For example, boron ions are implanted under the conditions that the implantation type is BF ₂ ions, the acceleration energy is 20 KeV, and the dose is 3.0 × 10 ¹⁵ / cm ² . The arsenic ion implantation conditions are an acceleration energy of 50 KeV and a dose of 4.0 × 10 ¹⁵ / cm ² .

(5) By an ordinary semiconductor device manufacturing process, an interlayer insulating film 19 is formed, a contact hole is formed in the interlayer insulating film 19, and a metal wiring 21 made of a metal material is formed in the contact hole and on the interlayer insulating film. At this time, the N-type high concentration diffusion layers 17n and 17n constituting the N-type source and the N-type drain of the MOS capacitor 11 are short-circuited by the metal wiring 21, so that the MOS capacitor 11 functions as a MOS capacitor.

  In this manner, the enhancement type NchMOS transistor 9n having a breakdown voltage of about 6V, the enhancement type PchMOS transistor 9p having a breakdown voltage of about 6V, and the enhancement type NchMOS transistor having a breakdown voltage of about 6V were formed.

  In this embodiment, the MOS capacitor 11 and the Nch MOS transistor 9n have different impurity ion concentration profiles in the vicinity of the surface of the P-type well 3 under the gate oxide film 13b. The NchMOS transistor forming the MOS capacitor 11 has a lower boron ion concentration under the gate oxide film 13b than the NchMOS transistor 9n, and the NchMOS transistor forming the MOS capacitor 11 and the NchMOS transistor 9n have different threshold voltages, and the gate capacitance The CV characteristics are also different. Therefore, the Nch MOS transistor forming the MOS capacitor 11 has a stable capacitance near the threshold voltage of the Nch MOS transistor 9n, and is useful as a MOS capacitor.

FIG. 6 is a schematic process cross-sectional view for explaining still another embodiment of the first aspect of the semiconductor device manufacturing method. FIG. 6 (5) shows still another embodiment of the first mode of the semiconductor device. The parenthesized numerals (1) to (5) in FIG. 6 correspond to the steps (1) to (5) described below. 6, parts having the same functions as those in FIGS. 1 and 5 are denoted by the same reference numerals, and detailed description thereof is omitted.
First, another embodiment of the first aspect of the semiconductor device will be described with reference to FIG.

  A P-type well 3, an N-type well 5, and a field oxide film 7 are formed on a P-type silicon substrate 1. The field oxide film 7 defines the formation region of the Nch MOS transistor 9n, the Pch MOS transistor 9p, and the MOS capacitor 11.

  In this embodiment, the MOS capacitor 11 includes a P-type high concentration diffusion layer (P +) constituting a P-type source and a P-type drain instead of the N-type high concentration diffusion layers 17n and 17n shown in FIG. 17p. The structures of the Pch MOS transistor 9p and the Nch MOS transistor are the same as those shown in FIG.

  In this embodiment, the MOS capacitor 11 and the Nch MOS transistor 9n have different impurity ion concentration profiles in the vicinity of the surface of the P-type well 3 under the gate oxide film 13b. Furthermore, the conductivity types of the diffusion layers 17p and 19n constituting the source and drain are different between the MOS capacitor 11 and the Nch MOS transistor 9n.

Still another embodiment of the first aspect of the semiconductor device manufacturing method will be described with reference to FIG.
(1) A P-type well 3, an N-type well 5, and a field oxide film 7 are formed on a P-type silicon substrate 1 in the same process as the process (1) described with reference to FIG. The formation region of the MOS capacitor 11 is formed in the P-type well 3.

(2) The photoresist 27 is formed in the same step (2) described with reference to FIG. 5B, and the P-type well 3 in the formation region of the Nch MOS transistor 9n is formed using the photoresist 27 as a mask. Then, boron ions for adjusting the threshold voltage of the Nch MOS transistor 9n are implanted. For example, boron ions for threshold voltage adjustment are implanted under the conditions that the implantation type is BF ₂ ions, the acceleration energy is 15 KeV, and the dose is 8.0 × 10 ¹¹ / cm ² .

(3) In the same process as the process (2) described with reference to FIG. 5 (3), the photoresist 27 is removed, the gate oxide film 13b is formed, and the NchMOS transistor 9n and the MOS capacitor 11 are formed. N-type gate electrodes 15n and 15n are simultaneously formed on P-type well 3 via gate oxide film 13b, and P-type gate electrode 15p is formed on N-type well 5 in the formation region of PchMOS transistor 9p via gate oxide film 13b. Form. Here, the PchMOS transistor 9p, the MOS capacitor 11, and the NchMOS transistor 9n may have different gate oxide film thicknesses.

(4) Boron ions for forming P type high concentration diffusion layers 17p and 17p for the P type source and P type drain are formed in the N type well 5 in the formation region of the Pch MOS transistor 9p by photolithography and ion implantation. Simultaneously with the implantation, boron ions for forming the P-type high concentration diffusion layers 17p, 17p for the P-type source and P-type drain are implanted into the P-type well 3 in the formation region of the MOS capacitor 11. Separately, arsenic ions for forming N-type high concentration diffusion layers 17n and 17n for the N-type source and N-type drain are implanted into the P-type well 3 in the formation region of the Nch MOS transistor 9n. Thereafter, a thermal diffusion process is performed to form a P-type high concentration diffusion layer 17p and an N-type high concentration diffusion layer 17n. For example, boron ions are implanted under the conditions that the implantation type is BF ₂ ions, the acceleration energy is 20 KeV, and the dose is 3.0 × 10 ¹⁵ / cm ² . The arsenic ion implantation conditions are an acceleration energy of 50 KeV and a dose of 4.0 × 10 ¹⁵ / cm ² .

(5) By an ordinary semiconductor device manufacturing process, an interlayer insulating film 19 is formed, a contact hole is formed in the interlayer insulating film 19, and a metal wiring 21 made of a metal material is formed in the contact hole and on the interlayer insulating film. At this time, the P-type high concentration diffusion layers 17p, 17p constituting the P-type source and the P-type drain of the MOS capacitor 11 are short-circuited by the metal wiring 21 so that the MOS capacitor 11 functions as a MOS capacitor.

  In this manner, the enhancement type NchMOS transistor 9n having a breakdown voltage of about 6V, the enhancement type PchMOS transistor 9p having a breakdown voltage of about 6V, and the depletion type PchMOS transistor having a breakdown voltage of about 6V were formed.

  In this embodiment, the MOS capacitor 11 and the Nch MOS transistor 9n have different impurity ion concentration profiles in the vicinity of the surface of the P-type well 3 under the gate oxide film 13b. Furthermore, the conductivity types of the diffusion layers 17p and 19n constituting the source and drain are different between the MOS capacitor 11 and the Nch MOS transistor 9n. The MOS capacitor 11 has the same conductivity type as the substrate, the source and the drain, so that the source and the drain are conductive, and does not operate as a MOS transistor. However, the CV characteristic of the gate capacitance of the MOS capacitor 11 is significantly different from the CV characteristic of the gate capacitance of the PchMOS transistor 9p, and shows a stable capacitance on the minus side. It has a stable capacitance near the threshold voltage and is useful as a MOS capacitor.

  In the embodiment shown in FIG. 5 and the embodiment shown in FIG. 6, both the MOS capacitor 11 and the Nch MOS transistor 9n are provided with the N type gate electrode 15n, but the P type of the Pch MOS transistor 9p is used as the gate electrode of the MOS capacitor 11. A P-type gate electrode formed simultaneously with the gate electrode 15p may be provided.

FIG. 7 is a cross-sectional view schematically showing still another embodiment of the first aspect of the semiconductor device of the semiconductor device.
In this embodiment, as compared with the embodiment shown in FIG. 5 (5), the MOS capacitor 11 includes a P-type gate electrode 15p formed simultaneously with the P-type gate electrode 15p of the PchMOS transistor 9p. By forming the P-type gate electrode 15p in the formation region of the MOS capacitor 11 at the same time as the P-type gate electrode 15p of the PchMOS transistor 9p in the step (3) described with reference to FIG. A structure can be obtained.

  According to this embodiment, compared with the embodiment shown in FIG. 5 (5), the CV characteristics can be made different from each other in the MOS capacitor 11 and the Nch MOS transistor 9n. A more stable capacity can be provided in the vicinity of the threshold voltage of 9n.

  It can be easily estimated that the structure in which the MOS capacitor 11 includes the P-type gate electrode 15p formed simultaneously with the P-type gate electrode 15p of the PchMOS transistor 9p can be applied to the embodiment shown in FIG.

  Further, when impurity ion implantation for adjusting the threshold voltage of the PchMOS transistor 9p is performed, it is performed between the steps (1) and (2) described with reference to FIG. 5 or the step (2). And (3), as shown in FIG. 8, a step of implanting impurity ions for adjusting the threshold voltage of the PchMOS transistor 9p, for example, phosphorus ions, into the N-type well 5 in the formation region of the PchMOS transistor 9p (see FIG. 2 ′) may be performed. At this time, as shown in FIG. 8, if the photoresist 29 having an opening is formed in the formation region of the PchMOS transistor 9p and the MOS capacitor 11 so as to cover the formation region of the NchMOS transistor 9n, the formation of the MOS capacitor 11 is performed. Phosphorus ions are also implanted into the P-type well 3 in the region, and the impurity ion concentration profiles in the vicinity of the surface of the P-type well 3 can be made different between the MOS capacitor 11 and the Nch MOS transistor 9n. Thereby, the Nch MOS transistor constituting the MOS capacitor 11 becomes a depletion type.

Further, when the impurity ion implantation for adjusting the threshold voltage of the Nch MOS transistor 9n is not performed, the step (2) described with reference to FIG. 5 (2) is not performed, and the description will be given with reference to FIG. By performing the above step (2 ′), the impurity ion concentration profiles in the vicinity of the surface of the P-type well 3 can be made different between the MOS capacitor 11 and the Nch MOS transistor 9n.
Further, it can be easily estimated that the step (2 ′) described with reference to FIG. 8 can be applied to the embodiment shown in FIG.

FIG. 9 is a schematic process cross-sectional view for explaining an example of the second aspect of the method for manufacturing a semiconductor device. FIG. 9 (5) shows an embodiment of the second mode of the semiconductor device. The parenthesized numerals (1) to (5) in FIG. 8 correspond to the steps (1) to (5) described below.
First, an example of the second mode of the semiconductor device will be described with reference to FIG.

  For example, a P-type well (PW, first conductive semiconductor layer) 33 and an N-type well (NW, second conductive semiconductor layer) 35 are formed on a P-type silicon substrate (Psub) 31 having a resistivity of 20Ω (ohms). Has been. On the surface of the P-type well 33 and the N-type well 35, for example, a field oxide film 37 for a device having a film thickness of 500 nm (nanometer) is formed. The field oxide film 37 defines a formation region of an Nch MOS transistor (second conductivity type MOS transistor) 39n in the P type well 33, and a formation region of the MOS capacitor 41 and a Pch MOS transistor (first conductivity type MOS transistor) in the N type well 35. ) 39p formation region is defined.

  On the P-type well 33 in the formation region of the Nch MOS transistor 39n, for example, an N-type gate made of an N-type polysilicon film (second conductivity type semiconductor film) through a gate oxide film (gate insulating film) 43 having a thickness of 6 nm, for example. An electrode (second conductivity type gate electrode) 45n is formed. The N-type gate electrode 45n is formed by a laminated film of an N-type polysilicon film and tungsten silicide, but FIG. 9 shows the N-type polysilicon film and tungsten silicide integrally. An N-type source and an N-type drain (second-conductivity-type source and second-conductivity-type drain) sandwiching an N-type gate electrode 45n as viewed from above the P-type well 33 in the formation region of the NchMOS transistor 39n. A type high-concentration diffusion layer (N +) 47n is formed. Thereby, an Nch MOS transistor 39n is formed.

  An N-type gate electrode 45 n made of an N-type polysilicon film is formed on the N-type well 35 in the formation region of the MOS capacitor 41 via a gate oxide film 43. A P-type source and a P-type drain (first conductivity type source and first conductivity type drain) are formed by sandwiching a P-type gate electrode 45p as viewed from above the N-type well 35 in the formation region of the MOS capacitor 41. A mold high-concentration diffusion layer (P +) 47p is formed. Thereby, the MOS capacitor 41 is formed.

  A P-type gate electrode (first conductivity type gate electrode) 45p made of a P-type polysilicon film (first conductivity type semiconductor film) is formed on the N-type well 35 in the formation region of the Pch MOS transistor 39p via a gate oxide film 43. Has been. The P-type gate electrode 45p is formed by a laminated film of a P-type polysilicon film and tungsten silicide, but FIG. 9 shows the P-type polysilicon film and tungsten silicide integrally. A P-type high-concentration diffusion layer 47p constituting a P-type source and a P-type drain is formed in the N-type well 35 in the formation region of the Pch MOS transistor 39p with the P-type gate electrode 45p as viewed from above. Thereby, the Pch MOS transistor 39p is formed.

An interlayer insulating film 49 is formed to cover the formation region of the Nch MOS transistor 39n, the formation region of the Pch MOS transistor 39p, and the formation region of the MOS capacitor 41. Contact holes are formed in the interlayer insulating film 49. A metal wiring 51 made of a metal material is formed in the contact hole and on the interlayer insulating film 49. The two P-type high concentration diffusion layers 47p, 47p of the MOS capacitor 41 are connected by a metal wiring 51 and are short-circuited.
In this embodiment, the conductivity types of the gate electrodes 45p and 45n are different between the MOS capacitor 41 and the Pch MOS transistor 39p.

An embodiment of the second aspect of the semiconductor device manufacturing method will be described with reference to FIG.
(1) For example, on a P-type silicon substrate 1 having a resistivity of 20Ω, a P-type well 33 having a boron ion concentration appropriate for forming the NchMOS transistor 39n and a phosphorus ion concentration appropriate for forming the PchMOS transistor 39p The N-type well 35 is formed by a usual method. A field oxide film 37 is formed on the surface of the P-type well 33 and the N-type well 35. Here, BF ₂ ions are implanted into the formation region of the Nch MOS transistor 39n under the condition of an acceleration energy of 180 KeV and a dose amount of 1.0 × 10 ¹³ / cm ² for forming the P-type well 33 by ion implantation. In order to form the N-type well 35, phosphorus ions are implanted into the formation region of the Pch MOS transistor 39p and the MOS capacitor 41 under the condition of an acceleration energy of 180 KeV and a dose amount of 4.0 × 10 ¹² / cm ² . Thermal diffusion treatment was performed under conditions of 60 minutes. The field oxide film 37 was formed by a normal LOCOS method.

(2) Photoresist technology is used to form a photoresist 53 that covers the formation region of the Pch MOS transistor 39p and the MOS capacitor 41 and has an opening in the formation region of the Nch MOS transistor 39n. Boron ions for adjusting the threshold voltage of the P-type well 33NchMOS transistor 39n in the formation region of the NchMOS transistor 39n are simultaneously implanted by the ion implantation method using the photoresist 53 as a mask. Here, since the N-type well 35 in the formation region of the PchMOS transistor 39p and the MOS capacitor 41 is covered with the photoresist 53, boron ions are not implanted into the N-type well 35 in the formation region of the PchMOS transistor 39p. For example, boron ions for threshold voltage adjustment are implanted under the conditions that the implantation type is BF ₂ ions, the acceleration energy is 80 KeV, and the dose is 4.0 × 10 ¹² / cm ² .

(3) The photoresist 53 is removed. By thermal oxidation, a gate oxide film 43 having a film thickness of 13 nm is formed on the P-type well 33 in the formation region of the Nch MOS transistor 39n and on the N-type well 35 in the formation region of the Pch MOS transistor 39p and the MOS capacitor 41. For example, a polysilicon film having a thickness of 250 nm is deposited, and tungsten silicide having a thickness of 80 nm is deposited thereon. By photolithography and ion implantation, phosphorus ions are implanted into the polysilicon film in the formation region of the Nch MOS transistor 39n and the MOS capacitor 41 to form an N type, and boron ions are implanted into the polysilicon film in the formation region of the Pch MOS transistor 39p. Use P type. The silicide film and the polysilicon film are patterned by photolithography and etching techniques, and the gate oxide film 43 is interposed on the P-type well 33 in the formation region of the NchMOS transistor 39n and on the N-type well 35 in the formation region of the MOS capacitor 41. The N-type gate electrode 45n is formed, and the P-type gate electrode 45p is formed on the N-type well 35 in the formation region of the PchMOS transistor 39p via the gate oxide film 43. Here, the NchMOS transistor 39n, the MOS capacitor 41, and the PchMOS transistor 39p may have different gate oxide film thicknesses. In this way, the PchMOS transistor 39p and the MOS capacitor 41 make the conductivity types of the gate electrodes 45p and 45n different from each other.

(4) Boron ions for forming P-type high concentration diffusion layers 47p and 47p for the P-type source and P-type drain are formed in the N-type well 35 in the formation region of the Pch MOS transistor 39p by photolithography and ion implantation. Simultaneously with the implantation, boron ions for forming P-type high concentration diffusion layers 47p and 47p for the P-type source and P-type drain are implanted into the N-type well 35 in the formation region of the MOS capacitor 41. Separately, arsenic ions for forming N-type high-concentration diffusion layers 47n and 47n for the N-type source and N-type drain in the P-type well 33 in the formation region of the Nch MOS transistor 39n by photolithography and ion implantation. Inject. Thereafter, a thermal diffusion process is performed to form a P-type high concentration diffusion layer 47p and an N-type high concentration diffusion layer 47n. For example, boron ions are implanted under the conditions that the implantation type is BF ₂ ions, the acceleration energy is 20 KeV, and the dose is 3.0 × 10 ¹⁵ / cm ² . The arsenic ion implantation conditions are an acceleration energy of 50 KeV and a dose of 4.0 × 10 ¹⁵ / cm ² .

(5) By an ordinary semiconductor device manufacturing process, an interlayer insulating film 49 is formed, a contact hole is formed in the interlayer insulating film 49, and a metal wiring 51 made of a metal material is formed in the contact hole and on the interlayer insulating film. At this time, the P-type high concentration diffusion layers 47p, 47p constituting the P-type source and P-type drain of the MOS capacitor 41 are short-circuited by the metal wiring 51 so that the MOS capacitor 41 functions as a MOS capacitor.

  In this manner, the enhancement type NchMOS transistor 39n having a breakdown voltage of about 6V, the enhancement type PchMOS transistor 39p having a breakdown voltage of about 6V, and the MOS capacitor 41 including the enhancement type PchMOS transistor having a breakdown voltage of about 6V were formed.

  In this embodiment, the conductivity types of the gate electrodes 45p and 45n are different between the MOS capacitor 41 and the Pch MOS transistor 39p. Since the PchMOS transistor constituting the MOS capacitor 41 includes the N-type gate electrode 45n, the threshold voltage is higher than that of the PchMOS transistor 39p having the P-type gate electrode 45p. In this embodiment, the threshold voltage of the Pch MOS transistor constituting the MOS capacitor 41 is -1.5V, and the threshold voltage of the Pch MOS transistor 39p is -1V or more. Since the CV characteristic of the gate capacitance of the PchMOS transistor constituting the MOS capacitor 41 shows a stable capacitance on the plus side, it has a stable capacitance near the threshold voltage of the PchMOS transistor 39p and is useful as a MOS capacitor.

FIG. 10 is a schematic process cross-sectional view for explaining another embodiment of the second aspect of the semiconductor device manufacturing method. FIG. 10 (5) shows another embodiment of the second mode of the semiconductor device. The parenthesized numerals (1) to (5) in FIG. 10 correspond to the steps (1) to (5) described below. 10, parts having the same functions as those in FIG. 9 are denoted by the same reference numerals, and detailed description thereof is omitted.
First, another embodiment of the first aspect of the semiconductor device will be described with reference to FIG.

  A P-type well 33, an N-type well 35, and a field oxide film 37 are formed on the P-type silicon substrate 1. The field oxide film 37 defines the formation region of the Nch MOS transistor 39n, the Pch MOS transistor 39p, and the MOS capacitor 41.

  In this embodiment, the MOS capacitor 41 includes an N-type high concentration diffusion layer (N +) constituting an N-type source and an N-type drain instead of the P-type high concentration diffusion layers 47p and 47p shown in FIG. 47n. The structures of the Pch MOS transistor 39p and the Nch MOS transistor 39n are the same as those shown in FIG.

  In this embodiment, the conductivity types of the gate electrodes 45p and 45n are different between the MOS capacitor 41 and the Pch MOS transistor 39p. Furthermore, the conductivity types of the diffusion layers 47p and 49n constituting the source and drain are different between the MOS capacitor 41 and the Pch MOS transistor 39p.

Another embodiment of the second aspect of the semiconductor device manufacturing method will be described with reference to FIG.
(1) The P-type well 33, the N-type well 35, and the field oxide film 37 are formed on the P-type silicon substrate 1 by the same process as the process (1) described with reference to FIG.

(2) The photoresist 53 is formed in the same step (2) described with reference to FIG. 9B, and the P-type well 33 in the formation region of the Nch MOS transistor 39n is formed using the photoresist 53 as a mask. Are simultaneously implanted with boron ions for adjusting the threshold voltage of the Nch MOS transistor 39n.

(3) In the same step (1) described with reference to FIG. 9 (1), the photoresist 53 is removed, a gate oxide film 43 is formed, and gate electrodes 45p and 45n are formed. Here, the NchMOS transistor 39n, the MOS capacitor 41, and the PchMOS transistor 39p may have different gate oxide film thicknesses.

(4) Arsenic ions for forming N-type high-concentration diffusion layers 47n and 47n for the N-type source and N-type drain are formed in the P-type well 33 in the formation region of the Nch MOS transistor 39n by photolithography and ion implantation. Simultaneously with the implantation, arsenic ions for forming N-type high concentration diffusion layers 47n and 47n for the N-type source and N-type drain are implanted into the N-type well 35 in the formation region of the MOS capacitor 41. Separately, boron ions for forming P-type high-concentration diffusion layers 47p and 47p for the P-type source and P-type drain are implanted into the N-type well 35 in the formation region of the Pch MOS transistor 39p. Thereafter, a thermal diffusion process is performed to form a P-type high concentration diffusion layer 47p and an N-type high concentration diffusion layer 47n. For example, boron ions are implanted under the conditions that the implantation type is BF ₂ ions, the acceleration energy is 20 KeV, and the dose is 3.0 × 10 ¹⁵ / cm ² . The arsenic ion implantation conditions are an acceleration energy of 50 KeV and a dose of 4.0 × 10 ¹⁵ / cm ² .

(5) By an ordinary semiconductor device manufacturing process, an interlayer insulating film 49 is formed, a contact hole is formed in the interlayer insulating film 49, and a metal wiring 51 made of a metal material is formed in the contact hole and on the interlayer insulating film. At this time, the N-type high concentration diffusion layers 47n and 47n constituting the N-type source and the N-type drain of the MOS capacitor 41 are short-circuited by the metal wiring 51 so that the MOS capacitor 41 functions as a MOS capacitor.

  In this way, the enhancement type NchMOS transistor 39n having a breakdown voltage of about 6V, the enhancement type PchMOS transistor 39p having a breakdown voltage of about 6V, and the MOS capacitor 41 including a depletion type NchMOS transistor having a breakdown voltage of about 6V were formed.

  In this embodiment, the conductivity types of the gate electrodes 45p and 45n are different between the MOS capacitor 41 and the Pch MOS transistor 39p. Furthermore, the conductivity types of the diffusion layers 47p and 49n constituting the source and drain are different between the MOS capacitor 41 and the Pch MOS transistor 39p. The MOS capacitor 41 has the same conductivity type as the substrate, and the source and drain are conductive, so that the MOS capacitor 41 does not operate as a MOS transistor. However, since the CV characteristic of the gate capacitance of the MOS capacitor 41 shows a stable capacitance on the plus side, the MOS capacitor 41 has a stable capacitance near the threshold voltage of the Nch MOS transistor 39n and is useful as a MOS capacitor. is there.

  9 and 10, the MOS capacitor is formed in the N-type well 35. However, the MOS capacitor may be formed in a P-type well. The embodiment will be described with reference to an example using a triple well. However, the mode of forming the MOS capacitor in the P-type well is not limited to that using a triple well.

FIG. 11 is a schematic process cross-sectional view for explaining still another embodiment of the second aspect of the semiconductor device manufacturing method. FIG. 11 (5) shows still another embodiment of the second mode of the semiconductor device. The parenthesized numerals (1) to (5) in FIG. 11 correspond to the steps (1) to (5) described below. 11, parts having the same functions as those in FIG. 9 are denoted by the same reference numerals, and detailed description thereof is omitted.
First, another embodiment of the second aspect of the semiconductor device will be described with reference to FIG.

  A P-type well 33, an N-type well 35, and a field oxide film 37 are formed on a P-type silicon substrate 31. The P-type well 33 is formed in an N-type well 55 formed in the P-type silicon substrate 31. The field oxide film 37 defines the formation region of the Nch MOS transistor 39n, the Pch MOS transistor 39p, and the MOS capacitor 41. The formation region of the MOS capacitor 41 is provided in the P-type well 33.

In this embodiment, the MOS capacitor 41 is formed in a P-type well 33, and includes a P-type gate electrode 45p and an N-type high concentration diffusion layer 47n constituting an N-type source and an N-type drain. The structures of the Pch MOS transistor 39p and the Nch MOS transistor 39n are the same as those shown in FIG.
In this embodiment, the conductivity types of the gate electrodes 45p and 45n are different between the MOS capacitor 41 and the Nch MOS transistor 39n.

Still another embodiment of the second aspect of the semiconductor device manufacturing method will be described with reference to FIG.
(1) An N-type well 35 having a phosphorus ion concentration suitable for forming a PchMOS transistor 39p on a P-type silicon substrate 1 having a resistivity of 20Ω, for example, and an N-type well for a triple well by a normal semiconductor device manufacturing process 55 is formed, and a P-type well 33 having an appropriate boron ion concentration is formed in the N-type well 55 to form the NchMOS transistor 39n. A field oxide film 37 is formed on the surfaces of the P-type well 33, the N-type well 35, and the N-type well 55. Here, phosphorous ions are formed in the formation region of the Pch MOS transistor 39p and the MOS capacitor 41 under the condition of an acceleration energy of 180 KeV and a dose amount of 2.0 × 10 ¹³ / cm ² for forming the N-type well 55 by ion implantation. After the injection, thermal diffusion treatment was performed at 1000 ° C. for 120 minutes, and further, thermal diffusion treatment was performed at 1200 ° C. for 300 minutes. Further, the formation region of the Nch MOS transistor 39n and the MOS capacitor 41 is formed by ion implantation with BF ₂ ions at the acceleration energy of 180 KeV and the dose amount of 3.5 × 10 ¹² / cm ² for forming the P-type well 33. In order to form the N-type well 35, phosphorus ions are implanted into the formation region of the PchMOS transistor 39p under the condition of an acceleration energy of 180 KeV and a dose amount of 1.0 × 10 ¹³ / cm ^2. The thermal diffusion treatment was performed under the condition of minutes. The field oxide film 37 was formed by a normal LOCOS method.

(2) Photoresist technology is used to form a photoresist 57 that covers the formation region of the Pch MOS transistor 39p and has openings in the formation region of the Nch MOS transistor 39n and the MOS capacitor 41. Boron ions for adjusting the threshold voltage of the Nch MOS transistor 39n are implanted by ion implantation into the P-type well 33 in the formation region of the Nch MOS transistor 39n and the MOS capacitor 41 using the photoresist 57 as a mask. For example, boron ions for threshold voltage adjustment are implanted under the conditions that the implantation type is BF ₂ ions, the acceleration energy is 15 KeV, and the dose is 8.3 × 10 ¹¹ / cm ² .

(3) The photoresist 57 is removed. By thermal oxidation, a gate oxide film 43 having a thickness of 13 nm is formed on the P-type well 33 in the formation region of the Nch MOS transistor 39n and the MOS capacitor 41 and on the N-type well 35 in the formation region of the Pch MOS transistor 39p. The gate electrodes 45p and 45n are formed in the same process as the formation process of the gate electrodes 45p and 45n in the process (3) described with reference to FIG. 9 (3). However, N-type gate electrodes 45n and 45n are formed on the P-type well 33 in the formation region of the Nch MOS transistor 39n via the gate oxide film 43, and on the N-type well 35 in the formation region of the Pch MOS transistor 39p and the MOS capacitor 41. A P-type gate electrode 45 p is formed through the gate oxide film 43. Here, the gate oxide film thickness may be different between the Pch MOS transistor 39p, the MOS capacitor 41, and the Nch MOS transistor 39n.

(4) Arsenic ions for forming N-type high-concentration diffusion layers 47n and 47n for the N-type source and N-type drain are formed in the P-type well 33 in the formation region of the Nch MOS transistor 39n by photolithography and ion implantation. Simultaneously with the implantation, arsenic ions for forming N-type high concentration diffusion layers 47n and 47n for the N-type source and N-type drain are implanted into the N-type well 35 in the formation region of the MOS capacitor 41. Separately, boron ions for forming P-type high-concentration diffusion layers 47p and 47p for the P-type source and P-type drain are implanted into the N-type well 35 in the formation region of the Pch MOS transistor 39p. Thereafter, a thermal diffusion process is performed to form a P-type high concentration diffusion layer 47p and an N-type high concentration diffusion layer 47n. For example, boron ions are implanted under the conditions that the implantation type is BF ₂ ions, the acceleration energy is 20 KeV, and the dose is 3.0 × 10 ¹⁵ / cm ² . The arsenic ion implantation conditions are an acceleration energy of 50 KeV and a dose of 4.0 × 10 ¹⁵ / cm ² .

(5) By an ordinary semiconductor device manufacturing process, an interlayer insulating film 19 is formed, a contact hole is formed in the interlayer insulating film 19, and a metal wiring 21 made of a metal material is formed in the contact hole and on the interlayer insulating film. At this time, the N-type high concentration diffusion layers 47n and 47n constituting the N-type source and the N-type drain of the MOS capacitor 41 are short-circuited by the metal wiring 21, so that the MOS capacitor 41 functions as a MOS capacitor.

  In this manner, the enhancement type NchMOS transistor 39n having a breakdown voltage of about 6V, the enhancement type PchMOS transistor 39p having a breakdown voltage of about 6V, and the MOS capacitor 41 including the enhancement type NchMOS transistor having a breakdown voltage of about 6V were formed.

  In this embodiment, the conductivity types of the gate electrodes 45p and 45n are different between the MOS capacitor 41 and the Nch MOS transistor 39n. Since the Nch MOS transistor constituting the MOS capacitor 41 includes the P-type gate electrode 45p, the threshold voltage is higher than that of the Nch MOS transistor 39n having the N-type gate electrode 45n. In this embodiment, the threshold voltage of the Nch MOS transistor constituting the MOS capacitor 41 is 1.5V, and the threshold voltage of the Nch MOS transistor 39n is 1V or less. Since the CV characteristic of the gate capacitance of the NchMOS transistor constituting the MOS capacitor 41 shows a stable capacitance on the minus side, it has a stable capacitance near the threshold voltage of the NchMOS transistor 39n, and is useful as a MOS capacitor.

FIG. 12 is a cross-sectional view schematically showing still another embodiment of the second aspect of the semiconductor device of the semiconductor device.
In this embodiment, as compared with the embodiment shown in FIG. 11 (5), the MOS capacitor 11 includes a P-type high concentration diffusion layer 47 formed simultaneously with the P-type high concentration diffusion layer 47 of the Pch MOS transistor 39p. Yes. In the step (4) described with reference to FIG. 11 (4), the P-type high concentration diffusion layers 47p and 47p for the P-type source and the P-type drain are formed in the N-type well 35 in the formation region of the PchMOS transistor 39p. Boron ions for forming P type high concentration diffusion layers 47p and 47p for the P type source and P type drain in the N type well 35 in the formation region of the MOS capacitor 41 are simultaneously implanted with boron ions for This structure is separately implanted by implanting arsenic ions for forming N-type high-concentration diffusion layers 47n and 47n for the N-type source and N-type drain into the P-type well 33 in the formation region of the Nch MOS transistor 39n. Can be obtained.

  According to this embodiment, compared to the embodiment shown in FIG. 1 (5), the CV characteristics can be made different from each other in the MOS capacitor 41 and the Nch MOS transistor 39n. A more stable capacitance can be provided in the vicinity of the 39n threshold voltage.

  In the embodiment shown in FIG. 11 and FIG. 12, since the MOS capacitor 41 is formed in the triple well, it can be used on the minus side. However, the MOS capacitor 41 is not necessarily formed in the triple well. Also in the embodiment shown in FIGS. 1 to 10, the MOS capacitors 11 and 41 can be formed in the triple well.

  As mentioned above, although the Example of this invention was described, material, a shape, arrangement | positioning, etc. are examples, this invention is not limited to these, Various within the range of this invention described in the claim Can be changed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic process cross-sectional view for explaining an embodiment of a first aspect of a method for manufacturing a semiconductor device, and (5) shows an embodiment of the first mode of the semiconductor device. It is a schematic process sectional drawing for demonstrating the other Example of the 1st aspect of the manufacturing method of a semiconductor device, (5) has shown the other Example of the 1st aspect of a semiconductor device. It is sectional drawing which shows schematically the further another Example of the 1st aspect of the semiconductor device of a semiconductor device. It is a schematic process sectional drawing for explaining a part of other example of the 1st phase of a manufacturing method of a semiconductor device. It is a schematic process sectional drawing for demonstrating the further another Example of the 1st aspect of the manufacturing method of a semiconductor device, (5) has shown the further another Example of the 1st aspect of a semiconductor device. It is a schematic process sectional drawing for demonstrating the further another Example of the 1st aspect of the manufacturing method of a semiconductor device, (5) has shown the further another Example of the 1st aspect of a semiconductor device. It is sectional drawing which shows schematically the further another Example of the 1st aspect of the semiconductor device of a semiconductor device. It is a schematic process sectional drawing for explaining a part of other example of the 1st phase of a manufacturing method of a semiconductor device. It is a schematic process sectional drawing for demonstrating one Example of the 2nd aspect of the manufacturing method of a semiconductor device, (5) has shown one Example of the 2nd aspect of the semiconductor device. It is a schematic process sectional drawing for demonstrating the other Example of the 2nd aspect of the manufacturing method of a semiconductor device, (5) has shown the other Example of the 2nd aspect of the semiconductor device. It is a schematic process sectional drawing for demonstrating the further another Example of the 2nd aspect of the manufacturing method of a semiconductor device, (5) has shown the further another Example of the 2nd aspect of a semiconductor device. It is sectional drawing which shows schematically the further another Example of the 2nd aspect of the semiconductor device of a semiconductor device. It is a figure which shows the CV characteristic of a Nch MOS transistor, A vertical axis | shaft shows a capacity | capacitance (F) and a horizontal axis shows a gate voltage (V).

Explanation of symbols

1, 31 P-type silicon substrate 3, 33 P-type well 5, 35 N-type well 9n, 39n Nch MOS transistor 9p, 39p Pch MOS transistor 11, 41 MOS capacitors 13a, 13b, 43 Gate oxide film 15n, 45n N-type gate electrode 15p , 45p P-type gate electrodes 17n, 47n N-type high-concentration diffusion layers 17p, 47p P-type high-concentration diffusion layers 19, 49 Interlayer insulating films 21, 51 Metal wirings 23, 25, 27 Photoresist

Claims (8)

In a method of manufacturing a semiconductor device for forming a first conductivity type MOS transistor, a second conductivity type transistor and a MOS capacitor on the same semiconductor substrate, the manufacture of a semiconductor device including the following steps (A) to (E) in that order: Method.
(A) forming a first conductive type semiconductor layer in which a second conductive type MOS transistor is formed and a second conductive type semiconductor layer in which a first conductive type MOS transistor and a MOS capacitor are formed on the same semiconductor substrate;
(B) Impurity ions for adjusting the threshold voltage of the second conductivity type MOS transistor are simultaneously applied to the first conductivity type semiconductor layer in the second conductivity type MOS transistor formation region and the second conductivity type semiconductor layer in the MOS capacitor formation region. The impurity ions for adjusting the threshold voltage of the second conductivity type MOS transistor are not implanted into the second conductivity type semiconductor layer of the first conductivity type MOS transistor formation region, and the MOS capacitor formation region and the first conductivity type are not implanted. Differentiating impurity ion concentration profiles in the vicinity of the surface of the second conductivity type semiconductor layer in the one conductivity type MOS transistor formation region;
(C) After forming a gate insulating film on the first conductive type semiconductor layer and the second conductive type semiconductor layer, on the gate insulating film in the first conductive type MOS transistor forming region and the MOS capacitor forming region. A first conductivity type gate electrode made of a first conductivity type semiconductor film is simultaneously formed, and a second conductivity type gate electrode made of a second conductivity type semiconductor film is formed on the gate insulating film in the second conductivity type MOS transistor formation region. Forming a process,
(D) forming the first conductivity type MOS transistor by forming the first conductivity type source and the first conductivity type drain in the second conductivity type semiconductor layer of the first conductivity type MOS transistor forming region to form the MOS at the same time A MOS transistor is formed by forming a first conductivity type source and a first conductivity type drain in the second conductivity type semiconductor layer of the capacitor formation region, and separately, the first conductivity type of the second conductivity type MOS transistor formation region. Forming a second conductivity type MOS transistor by forming a second conductivity type source and a second conductivity type drain in the semiconductor layer;
(E) forming an interlayer insulating film covering the first conductive type MOS transistor, the second conductive type transistor and the MOS capacitor; forming a contact hole in the interlayer insulating film; and in the contact hole and the interlayer insulating film Forming a metal wiring made of a metal material thereon to short-circuit the first conductivity type source and the first conductivity type drain of the MOS capacitor;   Between the step (A) and the step (C), instead of the step (B) or in addition to the step (B), the second conductive semiconductor layer in the first conductive type MOS transistor formation region Impurity ions for adjusting a threshold voltage of the first conductivity type MOS transistor are implanted into the first conductivity type semiconductor layer in the second conductivity type MOS transistor formation region and the second conductivity type semiconductor in the MOS capacitor formation region. The impurity ions for adjusting the threshold voltage of the first conductivity type MOS transistor are not implanted into the layer, and in the vicinity of the surface of the second conductivity type semiconductor layer in the MOS capacitor formation region and the first conductivity type MOS transistor formation region. The method of manufacturing a semiconductor device according to claim 1, wherein the step (B ′) of changing the impurity ion concentration profile of the semiconductor device is performed. In the step (D), the first conductive type MOS transistor is formed by forming the first conductive type source and the first conductive type drain in the second conductive type semiconductor layer of the first conductive type MOS transistor forming region. During the formation, the first conductive type source and the first conductive type drain are not formed in the MOS capacitor forming region, and the first conductive type semiconductor layer in the second conductive type MOS transistor forming region is formed in the first conductive type semiconductor layer. A MOS capacitor is formed by forming a second conductivity type source and a second conductivity type drain in the second conductivity type semiconductor layer of the MOS capacitor formation region simultaneously with forming a two conductivity type source and the second conductivity type drain. And
3. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step (E), the second conductivity type source and the second conductivity type drain of the MOS capacitor are short-circuited by a metal wiring.   The step (C) forms a second conductivity type, not a first conductivity type, as the gate electrode of the MOS capacitor simultaneously with the second conductivity type gate electrode of the second conductivity type MOS transistor. The manufacturing method of the semiconductor device as described in any one of 1, 2, or 3. In a semiconductor device comprising a first conductivity type MOS transistor, a second conductivity type transistor and a MOS capacitor on the same semiconductor substrate,
It is formed by the manufacturing method of the semiconductor device according to any one of claims 1 to 4,
A semiconductor device, wherein the MOS capacitor and the first conductivity type MOS transistor have different impurity ion concentration profiles near the surface of the second conductivity type semiconductor layer. In a method of manufacturing a semiconductor device for forming a first conductivity type MOS transistor, a second conductivity type transistor, and a MOS capacitor on the same semiconductor substrate, the manufacture of a semiconductor device including the following steps (A) to (D) in that order: Method.
(A) forming a first conductive type semiconductor layer in which a second conductive type MOS transistor is formed and a second conductive type semiconductor layer in which a first conductive type MOS transistor and a MOS capacitor are formed on the same semiconductor substrate;
(B) After forming a gate insulating film on the first conductive type semiconductor layer and the second conductive type semiconductor layer, a second insulating layer is formed on the gate insulating film in the second conductive type MOS transistor forming region and the MOS capacitor forming region. Forming a second conductivity type gate electrode made of a two conductivity type semiconductor film, and forming a first conductivity type gate electrode made of the first conductivity type semiconductor film on the gate insulating film in the first conductivity type MOS transistor formation region; ,
(C) forming a second conductivity type source and a second conductivity type drain in the first conductivity type semiconductor layer of the second conductivity type MOS transistor formation region, and separately forming the first conductivity type MOS transistor formation region in the first conductivity type; The first conductive type source and the first conductive type drain are formed in the two conductive type semiconductor layer to form the first conductive type MOS transistor, and at the same time, the first conductive type is formed in the second conductive type semiconductor layer in the MOS capacitor forming region. Forming a MOS source by forming a type source and a first conductivity type drain;
(D) forming an interlayer insulating film covering the first conductive type MOS transistor, the second conductive type transistor and the MOS capacitor; forming a contact hole in the interlayer insulating film; and in the contact hole and on the interlayer insulating film Forming a metal wiring made of a metal material on the first capacitor and short-circuiting the first conductivity type source and the first conductivity type drain of the MOS capacitor. In the step (C), the first conductive type MOS transistor is formed by forming the first conductive type source and the first conductive type drain in the second conductive type semiconductor layer of the first conductive type MOS transistor forming region. During the formation, the first conductive type source and the first conductive type drain are not formed in the MOS capacitor forming region, and the first conductive type semiconductor layer in the second conductive type MOS transistor forming region is formed in the first conductive type semiconductor layer. A MOS capacitor is formed by forming a second conductivity type source and a second conductivity type drain in the second conductivity type semiconductor layer of the MOS capacitor formation region simultaneously with forming a two conductivity type source and the second conductivity type drain. And
The method of manufacturing a semiconductor device according to claim 6, wherein in the step (D), the second conductivity type source and the second conductivity type drain of the MOS capacitor are short-circuited by a metal wiring. In a semiconductor device comprising a first conductivity type MOS transistor, a second conductivity type transistor and a MOS capacitor on the same semiconductor substrate,
It is formed by the method for manufacturing a semiconductor device according to claim 6 or 7,
The MOS capacitor has the second conductivity type gate electrode made of a second conductivity type semiconductor film, and the first conductivity type MOS transistor has the first conductivity type gate electrode made of a first conductivity type semiconductor film. A semiconductor device characterized by the above.

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