JP2009135329A - Electrical fuse circuit and semiconductor chip - Google Patents

Abstract

An object of the present invention is to provide an electric fuse circuit with a reduced circuit scale.
An electric fuse circuit includes a plurality of cell circuits each including a first switch circuit and a fuse connected in series between a first end and a second end, and a plurality of first circuits of the plurality of cell circuits. Between one node whose ends are commonly coupled, one second switch circuit coupled between one node and one data output end, and between one node and the first power supply voltage One of the plurality of first switch circuits of the plurality of cell circuits is configured to be selectively conductive.
[Selection] Figure 4

Description

  The present invention generally relates to an electric circuit, and particularly relates to an electric fuse circuit provided in a semiconductor chip.

  In a semiconductor device such as a semiconductor memory device, a fuse circuit is provided inside the device, and the fuse of this fuse circuit is selectively cut at the time of shipment from the factory, thereby specifying a chip ID, a memory redundancy target address, and an input / output interface configuration. Etc. At the time of operation, the semiconductor device refers to this fuse information, and operates according to the set chip ID, redundant address, input / output interface configuration, and the like.

  As a method for cutting the fuse, there are a method in which the fuse is blown by a laser beam and a method in which a high current is applied and a large current is applied to cut the fuse. FIG. 1 is a diagram showing a schematic configuration of a conventional electric fuse circuit that blows a fuse by flowing a large current by applying a high voltage.

  The electric fuse circuit 10 of FIG. 1 includes n cell circuits 11-1 to 11-n, a pad 12, a PMOS transistor 13, and a latch 14. Each of the cell circuits 11-1 to 11-n has a function of storing 1-bit information by fuse cutting / non-cutting, and includes an NMOS transistor 20, an NMOS transistor 21, and a fuse 23. The NMOS transistors 20 and 21 indicated by thick lines are, for example, high breakdown voltage transistors having a breakdown voltage of 3.3V, and the PMOS transistor 13 indicated by a thin line is, for example, a low breakdown voltage transistor having a breakdown voltage of 1.2V.

  When writing information, a high voltage is applied to the pad 12. When an address signal is input from the outside in a state where a high voltage is applied, the NMOS transistor 21 is turned on in one cell circuit corresponding to the specified address. Thereby, a large current can be passed through the fuse 23 in one cell circuit corresponding to the designated address, and the fuse 23 can be cut. By sequentially specifying desired addresses, the fuse 23 may be cut at the desired addresses.

  When reading fuse information, the pad 12 is connected to the ground voltage VSS. When an address is specified in this state, any one of the signals ADR [0] to ADR [n] becomes HIGH in accordance with the address specification, so that the NMOS transistor 20 becomes conductive in one cell circuit corresponding to the specified address. . When the fuse 23 is not cut, the input side of the latch 14 is pulled down to the ground voltage VSS, and LOW data is latched in the latch 14. When the fuse 23 is disconnected, the input side of the latch 14 is maintained at the power supply voltage VDD (HIGH), and HIGH data is latched in the latch 14. In this way, 1-bit information stored in the designated address can be read.

  FIG. 2 is a diagram showing an example of a more specific configuration of a conventional electric fuse circuit. The electric fuse circuit 30 in FIG. 2 includes a plurality of (for example, 64) cell circuits 31-1 for storing information of the first bit with respect to a plurality of (for example, 64) addresses, and a plurality of addresses for the plurality of addresses (for example, 64). A plurality of cell circuits 31-2 for storing 2-bit information, a PMOS transistor 32-1 corresponding to the first bit, a PMOS transistor 32-2 corresponding to the second bit, a pad 33, and a first bit of input data , A latch 34-2 corresponding to the second bit of the input data, a latch 35-1 corresponding to the first bit of the output data, a latch 35-2 corresponding to the second bit of the output data, A level shifter circuit (LS) 36-1 corresponding to the first bit of the input data, a level shifter circuit (LS) 36-2 corresponding to the second bit of the input data, a plurality (for example, Address decoder 37 of the plurality respectively provided to the address of four) (for example, 64), and an address signal line 38. FIG. 2 shows only the circuit portion corresponding to the first bit and the circuit portion corresponding to the second bit, but if the stored data stored in each address is n bits long, it is the same as the circuit portion corresponding to the first bit. N sets are provided corresponding to the first to nth bits.

  Each of the cell circuits 31-1 and 31-2 has a function of storing 1-bit information by fuse cutting / non-cutting, and includes an NMOS transistor 40, an NMOS transistor 41, a NOR circuit 42, and a fuse 43. The NMOS transistors 40 and 41 indicated by thick lines are high breakdown voltage transistors having a breakdown voltage of 3.3V, for example, and the PMOS transistors 32-1 and 32-2 indicated by thin lines are low breakdown voltage transistors having a breakdown voltage of 1.2V, for example. It is.

  Each address decoder 37 includes NAND circuits 50 to 52, inverters 53 and 54, and a level shifter circuit (LS) 55. By selectively connecting the input of the NAND circuit 50 to a predetermined signal line of the address signal line 38, the output of the NAND circuit 50 becomes LOW only when a predetermined address is designated on the address signal line 38. It can be comprised so that it may become. By changing the connection between the input of the NAND circuit 50 and the address signal line 38 for each address decoder 37, one corresponding to the designated address is designated when one of a plurality of (for example, 64) different addresses is designated. One address decoder 37 is configured such that the output of the NAND circuit 50 is LOW.

  At the time of writing information, a high voltage is applied to the pad 33. The write enable signal WE is set to HIGH, and the read sense signal SENSE is set to LOW. Since the read sense signal SENSE is LOW, the output of the inverter 54 of the address decoder 37 is fixed to LOW regardless of the address. Therefore, the NMOS transistor 40 is non-conductive in all cell circuits.

  In this state, when an address signal is input from the outside and an address is designated, the level shifter circuit 55 of one address decoder 37 corresponding to the designated address outputs LOW (0 V). The level shifter circuit 55 of another address decoder 37 corresponding to an address other than the designated address outputs HIGH (for example, 3.3 V).

  In response to this, in the cell circuit corresponding to the designated address, one input of the NOR circuit 42 becomes LOW. When “1” is stored in the latch 34-1 corresponding to the first bit of the input data, the output of the level shifter circuit 36-1 becomes LOW. In this case, in the cell circuit 31-1 corresponding to the designated address, both inputs of the NOR circuit 42 are LOW, and the NMOS transistor 41 is turned on. In the cell circuit 31-1 corresponding to another address, the input to the NOR circuit 42 from the address decoder 37 is HIGH, so that the NMOS transistor 41 is non-conductive. As described above, a large current can be passed through the fuse 43 and the fuse 43 can be cut only in the cell circuit corresponding to the designated address among the plurality of cell circuits 31-1 corresponding to the first bit. When “0” is stored in the latch 34-1 corresponding to the first bit of the input data, the output of the level shifter circuit 36-1 becomes HIGH, and the fuse 43 is also formed in the cell circuit corresponding to the designated address. Not cut.

  As described above, cutting / non-cutting of the fuse 43 of the cell circuit 31-1 at the designated address can be determined according to the data stored in the latch 34-1 corresponding to the first bit. Similarly, cutting / non-cutting of the fuse 43 of the cell circuit 31-2 at the designated address can be determined according to the data stored in the latch 34-2 corresponding to the second bit. If n latches 34-1 to 34-n are provided corresponding to n-bit length data, the n-bit data is stored in these latches and a desired address is designated. N-bit data can be stored in the address. Further, by storing different n-bit data in the latch and designating a different address, different data can be stored at different addresses.

  When reading fuse information, the pad 33 is connected to the ground voltage VSS. The write enable signal WE is set to LOW, and the read sense signal SENSE is set to HIGH. Since the write enable signal WE is LOW, the output of the level shifter circuit 55 of the address decoder 37 is fixed to HIGH regardless of the address. Therefore, the NMOS transistor 41 is non-conductive in all cell circuits.

  When an address is designated in this state, the inverter 54 of one address decoder 37 corresponding to the designated address outputs HIGH (for example, 1.2 V). The inverters 54 of other address decoders 37 corresponding to addresses other than the designated address output LOW (0 V).

  In response to this, in the cell circuit corresponding to the designated address, the NMOS transistor 40 becomes conductive. When the fuse 43 of the cell circuit 31-1 corresponding to the first bit of the designated address is not cut, the bit line BL1 is pulled down to the ground voltage VSS, and the LOW data (“0”) is stored in the latch 35-1. Is latched. When the fuse 43 of the cell circuit 31-1 corresponding to the first bit of the designated address is cut, the bit line BL1 is maintained at the power supply voltage VDD (HIGH) and the HIGH data (“ 1 ") is latched. In this way, the first bit information of the data stored at the designated address can be read.

  Similarly, when the fuse 43 of the cell circuit 31-2 corresponding to the second bit of the designated address is not cut, the bit line BL2 is pulled down to the ground voltage VSS, and the LOW data (“ 0 ") is latched. When the fuse 43 of the cell circuit 31-2 corresponding to the second bit of the designated address is cut, the bit line BL2 is maintained at the power supply voltage VDD (HIGH), and the HIGH data (“ 1 ") is latched. In this way, the information of the second bit of the data stored at the designated address can be read out.

  If n latches 35-1 to 35-n are provided corresponding to n-bit data, n-bit data is read from the cell circuit by designating a desired address, and latch 35-1 The read data can be stored in 35 to n. By designating another address, different data can be read from different addresses.

In recent years, it has become necessary to embed a chip ID or password in a chip in order to realize encrypted communication. The electric fuse circuit configured as described above is also used for applications for storing these chip IDs and passwords. For this reason, a macro of a larger capacity fuse circuit is required, and an increase in the area of the electric fuse circuit is a problem.
JP 60-080200 A JP-A-5-144283

  In view of the above, an object of the present invention is to provide an electric fuse circuit with a reduced circuit scale.

  The electric fuse circuit includes a plurality of cell circuits each including a first switch circuit and a fuse connected in series between a first end and a second end, and a plurality of the first ends of the plurality of cell circuits One node coupled in common, one second switch circuit coupled between the one node and one data output terminal, and between the one node and the first power supply voltage And a third switch circuit coupled thereto, wherein one of the plurality of first switch circuits of the plurality of cell circuits is configured to be selectively conductive.

  The semiconductor chip includes an electric fuse circuit and a logic circuit that receives data output from the data output terminal of the electric fuse circuit in accordance with a designated address, and the electric fuse circuit is between the first end and the second end. A plurality of cell circuits each including a first switch circuit and a fuse connected in series to each other, a node to which the plurality of first ends of the plurality of cell circuits are commonly coupled, and the one node One second switch circuit coupled between the one data output terminal and one third switch circuit coupled between the one node and the first power supply voltage; One of the plurality of first switch circuits of the plurality of cell circuits is configured to be selectively conductive according to the designated address.

  According to at least one embodiment of the invention, in the electrical fuse circuit, only one NMOS transistor is provided for each cell circuit that is selectively turned on in response to addressing. The one transistor functions as an address selection transistor both at the time of reading and at the time of writing. In addition, one cutting transistor and one reading transistor are provided in common for a plurality of cells corresponding to a plurality of addresses. When writing, the cutting transistor is made conductive to form a path through which a current for blowing the fuse flows. By conducting the reading transistor at the time of reading, the cell circuit is connected to the output terminal for reading, and data can be read from the output terminal. With such a configuration, the number of transistors required for each cell circuit can be reduced, and the circuit scale of the electric fuse circuit can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 3 is a diagram showing a schematic configuration of a semiconductor chip according to the present invention. The semiconductor chip 60 of FIG. 3 includes an electric fuse circuit 61, a logic circuit 62, a selector 63, a latch 64, and a pad 65.

  When data is written to the electric fuse circuit 61, the input data DIN is written to the latch 64 from the outside of the semiconductor chip 60, and the address signal ADR from the outside is selected by the selector 63 and supplied to the electric fuse circuit 61. Furthermore, when a high voltage for fuse blowing is applied to the pad 65 and the write enable signal WE is set to the asserted state from the outside, the input data DIN is written to the address specified by the address signal ADR. That is, if the data width is n bits, the n fuses designated by the address signal ADR are determined to be cut or not cut according to n bits “1” / “0” of the input data DIN. . The fuse is cut by fusing the fuse with a high voltage applied to the pad 65.

  When reading data from the electric fuse circuit 61, the write enable signal WE is set to the negated state from the outside of the semiconductor chip 60, and the read sense signal SENSE is set to the asserted state by the logic circuit 62. The selector 63 selects the address signal ADR from the logic circuit 62 and supplies it to the electric fuse circuit 61. A ground voltage is applied to the pad 65 in advance. As a result, the output data DOUT is read from the address specified by the address signal ADR. The read output data DOUT is supplied to the logic circuit 62. For example, if the data width is n bits, n bits “1” / “0” of the output data DOUT are determined according to the cutting / non-cutting of the n fuses designated by the address signal ADR.

  FIG. 4 is a diagram showing a schematic configuration of an electric fuse circuit according to the present invention. The electric fuse circuit 70 in FIG. 4 includes n cell circuits 71-1 to 71-n, a pad 72, a PMOS transistor 73, a latch 74, an NMOS transistor 75, and an NMOS transistor 76. Each of the cell circuits 71-1 to 71-n has a function of storing 1-bit information by fuse cutting / non-cutting, and includes an NMOS transistor 80 and a fuse 81. The NMOS transistors 75, 76, and 80 indicated by thick lines are, for example, high breakdown voltage transistors having a breakdown voltage of 3.3V, and the PMOS transistor 73 indicated by a thin line is, for example, a low breakdown voltage transistor having a breakdown voltage of 1.2V. The NMOS transistors 75, 76, and 80 are not limited to NMOS transistors as long as they have a function of controlling conduction / cutoff as a switch circuit.

  As described above, the electric fuse circuit 70 includes a plurality of cell circuits 71-1 to 71-71 each including the first switch circuit (NMOS transistor 80) and the fuse 81 connected in series between the first end and the second end. -N and one node A to which a plurality of first ends of the plurality of cell circuits 71-1 to 71-n are commonly coupled, and one node A coupled between the node A and the data output end B 2 switch circuits (NMOS transistor 76) and one third switch circuit (NMOS transistor 75) coupled between node A and the first power supply voltage (ground voltage). The electric fuse circuit 70 is configured to be able to selectively conduct one of the plurality of first switch circuits (NMOS transistors 80) of the cell circuits 71-1 to 71-n.

  When writing information, a high voltage is applied to the pad 72. Further, the NMOS transistor 75 is turned on by setting the write enable signal WE to the asserted state (HIGH). Further, by setting the read sense signal SENSE to the negated state (LOW), the NMOS transistor 76 is turned off. When an address signal is input from the outside and an address is designated, one of the signals ADR [0] to ADR [n] becomes HIGH in accordance with the address designation, so that one cell circuit corresponding to the designated address NMOS transistor 80 is turned on. Thus, a large current can be passed through the fuse 81 in one cell circuit corresponding to the designated address, and the fuse 81 can be cut. Note that the fuse 81 may be cut at a desired address by sequentially specifying the desired address.

  At the time of writing information, the NMOS transistor 75 functions as a disconnecting transistor (a transistor controlled by a write enable signal). In order to reduce the voltage drop in the NMOS transistor 75 as much as possible, a transistor having a large gate width is used as the NMOS transistor 75. For example, the conventional NMOS transistor 21 has a gate width W = 35 μm, whereas the NMOS transistor 75 of the present invention has a gate width W = 100 μm.

  When reading fuse information, the pad 72 is connected to the ground voltage VSS. Also, the NMOS transistor 75 is turned off by setting the write enable signal WE to a negated state (LOW). Also, the NMOS transistor 76 is turned on by setting the read sense signal SENSE to the asserted state (HIGH). When the address is designated, any one of the signals ADR [0] to ADR [n] becomes HIGH in accordance with the address designation, so that the NMOS transistor 80 becomes conductive in one cell circuit corresponding to the designated address. When the fuse 81 is not cut, the input side of the latch 74 is pulled down to the ground voltage VSS, and LOW data is latched in the latch 74. When the fuse 81 is disconnected, the input side of the latch 74 is maintained at the power supply voltage VDD (HIGH), and HIGH data is latched in the latch 74. In this way, 1-bit information stored in the designated address can be read.

  FIG. 5 is a diagram showing an example of a more specific configuration of the electric fuse circuit according to the present invention. The electric fuse circuit 80 of FIG. 5 includes a plurality of (for example, 64) cell circuits 81-1 for storing information of the first bit with respect to a plurality of (for example, 64) addresses, and a plurality of addresses for the plurality of addresses (for example, 64). A plurality of cell circuits 81-2 for storing 2-bit information, a PMOS transistor 82-1 corresponding to the first bit, a PMOS transistor 82-2 corresponding to the second bit, a pad 83, and a first bit of input data , A latch 84-2 corresponding to the second bit of the input data, a latch 85-1 corresponding to the first bit of the output data, a latch 85-2 corresponding to the second bit of the output data, Level shifter circuit (LS) 86-1 corresponding to the first bit of the input data, level shifter circuit (LS) 86-2 corresponding to the second bit of the input data, a plurality (for example, A plurality of (for example, 64) address decoders 87, an address signal line 38, a read NMOS transistor 89-1 corresponding to the first bit, and a read NMOS corresponding to the second bit are provided for four addresses, respectively. The transistor 89-2 includes a cutting NMOS transistor 90-1 corresponding to the first bit, and a cutting NMOS transistor 90-2 corresponding to the second bit. FIG. 5 shows only the circuit portion corresponding to the first bit and the circuit portion corresponding to the second bit, but if the storage data stored in each address is n bits long, it is the same as the circuit portion corresponding to the first bit. N sets are provided corresponding to the first to nth bits.

  Each of the cell circuits 81-1 and 81-2 has a function of storing 1-bit information by cutting / not cutting the fuse, and includes an NMOS transistor 91, a NOR circuit 92, and a fuse 93. Note that NMOS transistors 89-1, 89-2, 90-1, 90-2, and 91 indicated by bold lines are high voltage transistors having a withstand voltage of 3.3 V, for example, and PMOS transistors 82-1 and 82 indicated by thin lines. 82-2 is a low breakdown voltage transistor having a breakdown voltage of 1.2V, for example.

  Each address decoder 87 includes a NAND circuit 95 and a level shifter circuit (LS) 96. By selectively connecting the input of the NAND circuit 95 to a predetermined signal line of the address signal line 88, the output of the NAND circuit 95 becomes LOW only when a predetermined address is designated on the address signal line 88. It can be comprised so that it may become. By changing the connection between the input of the NAND circuit 95 and the address signal line 88 for each address decoder 87, when one of a plurality of (for example, 64) different addresses is designated, 1 corresponding to the designated address. Two address decoders 87 are configured so that the output of the NAND circuit 95 is LOW.

  When writing information, a high voltage is applied to the pad 83. The write enable signal WE is set to HIGH, and the read sense signal SENSE is set to LOW. Since the write enable signal WE is HIGH, the NMOS transistors 90-1 and 90-2 are in a conductive state. Further, since the read sense signal SENSE is LOW, the NMOS transistors 89-1 and 89-2 are in a non-conductive state.

  In this state, when an address signal is input from the outside and an address is designated, the level shifter circuit 96 of one address decoder 87 corresponding to the designated address outputs LOW (0 V). The level shifter circuit 96 of another address decoder 87 corresponding to an address other than the designated address outputs HIGH (for example, 3.3 V).

  In response to this, in the cell circuit corresponding to the designated address, one input of the NOR circuit 92 becomes LOW. When “1” is stored in the latch 84-1 corresponding to the first bit of the input data, the output of the level shifter circuit 86-1 becomes LOW. In this case, in the cell circuit 81-1 corresponding to the designated address, both inputs of the NOR circuit 92 become LOW, and the NMOS transistor 91 becomes conductive. In the cell circuit 81-1 corresponding to another address, since the input to the NOR circuit 92 from the address decoder 87 is HIGH, the NMOS transistor 91 is non-conductive. As described above, only in the cell circuit corresponding to the specified address among the plurality of cell circuits 81-1 corresponding to the first bit, a large current can be passed through the fuse 93 to cut the fuse 93. When “0” is stored in the latch 84-1 corresponding to the first bit of the input data, the output of the level shifter circuit 86-1 becomes HIGH, and the fuse 93 is also formed in the cell circuit corresponding to the designated address. Not cut off.

  As described above, cutting / non-cutting of the fuse 93 of the cell circuit 81-1 at the designated address can be determined according to the data stored in the latch 84-1 corresponding to the first bit. Similarly, cutting / non-cutting of the fuse 93 of the cell circuit 81-2 at the designated address can be determined according to the data stored in the latch 84-2 corresponding to the second bit. Assuming that n latches 84-1 to 84-n are provided corresponding to n-bit length data, the n-bit data is stored in these latches and a desired address is designated. N-bit data can be stored in the address. Further, by storing different n-bit data in the latch and designating a different address, different data can be stored at different addresses.

  When reading fuse information, the pad 83 is connected to the ground voltage VSS. The write enable signal WE is set to LOW, and the read sense signal SENSE is set to HIGH. Since the write enable signal WE is LOW, the NMOS transistors 90-1 and 90-2 are nonconductive. Further, since the read sense signal SENSE is HIGH, the NMOS transistors 89-1 and 89-2 are in a conductive state.

  In this state, when an address signal is input and an address is designated, the level shifter circuit 96 of one address decoder 87 corresponding to the designated address outputs LOW (0 V). The level shifter circuit 96 of another address decoder 87 corresponding to an address other than the designated address outputs HIGH (for example, 3.3 V). Note that the outputs of the level shifter circuits 86-1 to 86-n are set to LOW by storing "1" in the latches 84-1 to 84-n corresponding to the first bit to the nth bit of the input data. Keep it.

  In response to this, in the cell circuit corresponding to the designated address, the NMOS transistor 91 becomes conductive. When the fuse 93 of the cell circuit 81-1 corresponding to the first bit of the designated address is not cut, the bit line BL1 is pulled down to the ground voltage VSS, and LOW data (“0”) is stored in the latch 85-1. Is latched. When the fuse 93 of the cell circuit 81-1 corresponding to the first bit of the designated address is cut, the bit line BL1 is maintained at the power supply voltage VDD (HIGH), and the HIGH data (“ 1 ") is latched. In this way, the first bit information of the data stored at the designated address can be read.

  Similarly, when the fuse 93 of the cell circuit 81-2 corresponding to the second bit of the designated address is not cut, the bit line BL2 is pulled down to the ground voltage VSS, and the LOW data (“ 0 ") is latched. When the fuse 93 of the cell circuit 81-2 corresponding to the second bit of the designated address is cut, the bit line BL2 is maintained at the power supply voltage VDD (HIGH), and the HIGH data (“ 1 ") is latched. In this way, the information of the second bit of the data stored at the designated address can be read out.

  When n latches 85-1 to 85-n are provided corresponding to n-bit length data, n-bit data is read from the cell circuit by designating a desired address, and latches 85-1 to 85-n are designated. Read data can be stored in 85-n. By designating another address, different data can be read from different addresses.

  In the configuration of the conventional electric fuse circuit as shown in FIGS. 1 and 2, two NMOS transistors that are selectively turned on in response to addressing are provided for each cell circuit. One is a transistor for address selection at the time of writing, and the other is a transistor for address selection at the time of reading. On the other hand, in the configuration of the electric fuse circuit according to the present invention shown in FIGS. 4 and 5, only one NMOS transistor which is selectively turned on according to the addressing is provided for each cell circuit. The one transistor functions as an address selection transistor both at the time of reading and at the time of writing. In addition, one cutting transistor and one reading transistor are provided in common for a plurality of cells corresponding to a plurality of addresses. When writing, the cutting transistor is made conductive to form a path through which a current for blowing the fuse flows. At this time, the reading transistor is turned off to protect the circuit on the output side from a high voltage. By conducting the reading transistor at the time of reading, the cell circuit is connected to the output terminal for reading, and data can be read from the output terminal. At this time, the disconnecting transistor is kept nonconductive. With such a configuration, the number of transistors required for each cell circuit can be reduced, and the circuit scale of the electric fuse circuit can be reduced.

When attention is paid only to the width W of the element for the sake of simplicity, the area reduction effect according to the present invention is as follows. First, in the configuration of the conventional example shown in FIG.
NMOS transistor 40 gate width: W = 20 um
The gate width of the NMOS transistor 41: W = 35 um
The width of the NOR circuit 42: W = 4 um
Width of fuse 43: W = 3 um
It is. Therefore, if the number of addresses that can be selected (the number of different addresses) is M, M × (20 + 35 + 4 + 3) = 62M is the circuit scale per bit. In the configuration of the present invention shown in FIG.
Gate width of NMOS transistor 91: W = 35 um
Gate width of NMOS transistor 90-1: W = 100 um
The gate width of the NMOS transistor 89-1: W = 40 um
The width of the NOR circuit 92: W = 4 um
Width of fuse 93: W = 3 um
It is. Therefore, if the number of addresses that can be selected (the number of different addresses) is M, M × (35 + 4 + 3) + 100 + 40 = 42M + 140 is the circuit scale per bit. When comparing the circuit scale of the conventional configuration with the circuit scale of the configuration of the present invention, the effect of area reduction according to the present invention becomes more prominent as the number M of different addresses increases. Further, as can be seen by comparing the configuration of FIG. 2 with the configuration of FIG. 5, in the present invention, the circuit configuration of the address decoder is also simplified, so that an area reduction effect can also be obtained for this portion.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

Hereinafter, various aspects of the present invention will be summarized as additional notes.
(Appendix 1)
A plurality of cell circuits each including a first switch circuit and a fuse connected in series between a first end and a second end;
One node to which the plurality of first ends of the plurality of cell circuits are coupled in common;
One second switch circuit coupled between the one node and one data output;
A third switch circuit coupled between the one node and a first power supply voltage;
And an electric fuse circuit configured to selectively conduct one of the plurality of first switch circuits of the plurality of cell circuits.
(Appendix 2)
The second power supply voltage is applied to the second ends of the plurality of cell circuits, the second switch circuit is turned off, and the third switch circuit is turned on. 2. The apparatus according to claim 1, wherein the fuse connected in series to the first switch circuit that is conducted is disconnected by selectively conducting one of the switch circuits. Electric fuse circuit.
(Appendix 3)
The first power supply voltage is applied to the plurality of second ends of the plurality of cell circuits, the third switch circuit is turned off, and the second switch circuit is turned on. By selectively conducting one of the switch circuits of one, data corresponding to cutting / non-cutting of the fuse connected in series to the first switch circuit that is conducted is read from the data output terminal. The electric fuse circuit according to appendix 1, wherein the electric fuse circuit is configured as described above.
(Appendix 4)
2. The electrical circuit according to claim 1, further comprising an address decoding circuit having an output side coupled to a control terminal for controlling conduction / non-conduction of the plurality of first switch circuits, and an input side coupled to an address signal line. Fuse circuit.
(Appendix 5)
5. The electric fuse circuit according to appendix 4, further comprising a logic circuit that controls conduction / non-conduction of the plurality of first switch circuits based on a logical product of input data and an output of the address decoding circuit.
(Appendix 6)
An electric fuse circuit;
A logic circuit that receives data output from a data output terminal of the electric fuse circuit in accordance with a designated address, and the electric fuse circuit includes:
A plurality of cell circuits each including a first switch circuit and a fuse connected in series between a first end and a second end;
One node to which the plurality of first ends of the plurality of cell circuits are coupled in common;
A second switch circuit coupled between the one node and the one data output;
A third switch circuit coupled between the one node and a first power supply voltage;
A semiconductor chip, wherein one of the plurality of first switch circuits of the plurality of cell circuits is selectively conductive according to the designated address.
(Appendix 7)
The second power supply voltage is applied to the second ends of the plurality of cell circuits, the second switch circuit is turned off, and the third switch circuit is turned on. 7. The appendix according to claim 6, wherein the fuse connected in series to the first switch circuit that is turned on is disconnected by selectively turning on one of the switch circuits. Semiconductor chip.
(Appendix 8)
The first power supply voltage is applied to the plurality of second ends of the plurality of cell circuits, the third switch circuit is turned off, and the second switch circuit is turned on. By selectively conducting one of the switch circuits of one, data corresponding to cutting / non-cutting of the fuse connected in series to the first switch circuit that is conducted is read from the data output terminal. The semiconductor chip according to appendix 6, which is configured as described above.
(Appendix 9)
The electric fuse circuit further includes an address decoding circuit having an output side coupled to a control terminal for controlling conduction / non-conduction of the plurality of first switch circuits and an input side coupled to an address signal line. The semiconductor chip according to appendix 6.
(Appendix 10)
The electrical fuse circuit further includes a logic circuit that controls conduction / non-conduction of the plurality of first switch circuits based on a logical product of input data and an output of the address decoding circuit. The semiconductor chip described.

It is a figure which shows schematic structure of the conventional electric fuse circuit. It is a figure which shows an example of the specific structure of the conventional electric fuse circuit. It is a figure which shows schematic structure of the semiconductor chip by this invention. It is a figure which shows schematic structure of the electric fuse circuit by this invention. It is a figure which shows an example of the more concrete structure of the electric fuse circuit by this invention.

Explanation of symbols

60 Semiconductor chip 61 Electric fuse circuit 62 Logic circuit 63 Selector 64 Latch 65 Pad 70 Electric fuse circuit 71-1 to 71-n Cell circuit 72 Pad 73 PMOS transistor 74 Latch 75 NMOS transistor 76 NMOS transistor

Claims (6)

A plurality of cell circuits each including a first switch circuit and a fuse connected in series between a first end and a second end;
One node to which the plurality of first ends of the plurality of cell circuits are coupled in common;
One second switch circuit coupled between the one node and one data output;
A third switch circuit coupled between the one node and a first power supply voltage;
And an electric fuse circuit configured to selectively conduct one of the plurality of first switch circuits of the plurality of cell circuits.   The second power supply voltage is applied to the second ends of the plurality of cell circuits, the second switch circuit is turned off, and the third switch circuit is turned on. 2. The fuse connected in series with the first switched switch circuit is disconnected by selectively conducting one of the switch circuits. Electric fuse circuit.   The first power supply voltage is applied to the plurality of second ends of the plurality of cell circuits, the third switch circuit is turned off, and the second switch circuit is turned on. By selectively conducting one of the switch circuits of one, data corresponding to cutting / non-cutting of the fuse connected in series to the first switch circuit that is conducted is read from the data output terminal. The electric fuse circuit according to claim 1, wherein the electric fuse circuit is configured as described above.   2. The address decoding circuit according to claim 1, further comprising an address decoding circuit having an output side coupled to a control terminal for controlling conduction / non-conduction of the plurality of first switch circuits, and an input side coupled to an address signal line. Electric fuse circuit. An electric fuse circuit;
A logic circuit that receives data output from a data output terminal of the electric fuse circuit in accordance with a designated address, and the electric fuse circuit includes:
A plurality of cell circuits each including a first switch circuit and a fuse connected in series between a first end and a second end;
One node to which the plurality of first ends of the plurality of cell circuits are coupled in common;
A second switch circuit coupled between the one node and the one data output;
A third switch circuit coupled between the one node and a first power supply voltage;
A semiconductor chip, wherein one of the plurality of first switch circuits of the plurality of cell circuits is selectively conductive according to the designated address.   The second power supply voltage is applied to the second ends of the plurality of cell circuits, the second switch circuit is turned off, and the third switch circuit is turned on. 6. The fuse connected in series with the first switched switch circuit is disconnected by selectively conducting one of the switch circuits. Semiconductor chip.

Images