JP2009130005A - Display device - Google Patents

Abstract

In an organic EL display device, it is possible to prevent a short circuit due to foreign matter of parallel wirings.
An inner layer of a pixel circuit P of a power supply line 105DSL and a video signal line 106HS is used as an upper layer wiring. The write scan line 104WS is used as a lower layer wiring. Since the video signal line 106HS needs to overlap a portion intersecting with the power supply line 105DSL in the same layer, it is made a lower layer wiring. The upper layer wiring of the video signal line 106HS extends to the boundary of the adjacent pixel circuit P in the next row, and is overlapped at a portion intersecting with the power supply line 105DSL in the same layer in the next row. The write scan line 104WS and the power supply line 105DSL are laid out in different wiring layers, and the write scan line 104WS and the power supply line 105DSL are foreign matter even if conductive foreign matter is placed on one of the layers. There will be no connection.
[Selection] Figure 9

Description

  The present invention relates to a display device having a pixel array section in which pixel circuits (also referred to as pixels) having electro-optical elements (also referred to as display elements and light-emitting elements) are arranged in a matrix. More specifically, pixel circuits having electro-optic elements whose luminance changes depending on the magnitude of the drive signal as display elements are arranged in a matrix, each pixel circuit has an active element, and the active element is used for each pixel. The present invention relates to an active matrix display device in which display driving is performed.

  As a display element of a pixel, there is a display device using an electro-optical element whose luminance changes depending on an applied voltage or a flowing current. For example, a liquid crystal display element is a typical example of an electro-optical element whose luminance changes depending on an applied voltage, and an organic electroluminescence (Organic Electro Luminescence, Organic EL, Organic) (Light Emitting Diode, OLED; hereinafter referred to as “organic EL”) A typical example is an element. The organic EL display device using the latter organic EL element is a so-called self-luminous display device using an electro-optic element which is a self-luminous element as a pixel display element.

  An organic EL device has an organic thin film (organic layer) made by laminating an organic hole transport layer and an organic light emitting layer between the lower electrode and the upper electrode, and utilizes the phenomenon that light is emitted when an electric field is applied to the organic thin film. In this electro-optical element, the gradation of color is obtained by controlling the current value flowing through the organic EL element.

  Since the organic EL element can be driven with a relatively low applied voltage (for example, 10 V or less), the power consumption is low. Further, since the organic EL element is a self-luminous element that emits light by itself, an auxiliary illumination member such as a backlight that is required in a liquid crystal display device is not required, and the weight and thickness can be easily reduced. Furthermore, since the response speed of the organic EL element is very high (for example, about several μs), an afterimage at the time of displaying a moving image does not occur. Because of these advantages, development of flat self-luminous display devices using organic EL elements as electro-optical elements has been actively performed in recent years.

  By the way, in a display device using an electro-optic element such as a liquid crystal display device using a liquid crystal display element and an organic EL display device using an organic EL element, a simple (passive) matrix method and an active device are used as the driving method. A matrix method can be adopted. However, a simple matrix display device has problems such as a simple structure and a difficulty in realizing a large and high-definition display device.

  Therefore, in recent years, a pixel signal supplied to a light emitting element in a pixel has been converted into an active element, for example, an insulated gate field effect transistor (generally a thin film transistor (TFT)) as a switching transistor. Active matrix systems that are used and controlled have been actively developed.

  Here, when the electro-optic element in the pixel circuit emits light, the input image signal supplied via the video signal line is supplied to the gate end (control input terminal) of the drive transistor by a switching transistor (referred to as a sampling transistor). The image is taken into a provided storage capacitor (also referred to as a pixel capacitor), and a drive signal corresponding to the input image signal taken in is supplied to the electro-optical element.

  In a liquid crystal display device using a liquid crystal display element as an electro-optical element, the liquid crystal display element is a voltage-driven element, and thus the liquid crystal display element is driven with a voltage signal itself corresponding to an input image signal taken into the storage capacitor. On the other hand, in an organic EL display device using a current-driven element such as an organic EL element as an electro-optical element, a drive signal (voltage signal) corresponding to an input image signal taken into a storage capacitor is supplied to the current signal by a drive transistor. And the drive current is supplied to an organic EL element or the like.

  In a current-driven electro-optical element, typically an organic EL element, the light emission luminance varies depending on the drive current value. Therefore, in order to emit light with stable luminance, it is important to supply a stable drive current to the electro-optical element. For example, driving methods for supplying a driving current to the organic EL element can be broadly classified into a constant current driving method and a constant voltage driving method (this is a well-known technique, and publicly known literature is not presented here).

  Since the voltage-current characteristic of the organic EL element has a large inclination, when constant voltage driving is performed, a slight voltage variation or a variation in element characteristics causes a large current variation, resulting in a large luminance variation. Therefore, generally, constant current driving using a driving transistor in a saturation region is used. Of course, even with constant current driving, if there is a current variation, luminance variations will be caused, but if the current variation is small, only small luminance variations will occur.

  In other words, even in the constant current driving method, the driving signal written and held in the holding capacitor according to the input image signal may be constant because the light emission luminance of the electro-optic element is unchanged. It becomes important. For example, in order that the light emission luminance of the organic EL element remains unchanged, it is important that the drive current corresponding to the input image signal is constant.

  However, the threshold voltage and mobility of an active element (driving transistor) that drives the electro-optical element vary due to process variations. In addition, characteristics of electro-optical elements such as organic EL elements vary with time. If there is such a variation in characteristics of the active element for driving or a characteristic variation of the electro-optical element, even the constant current driving method affects the light emission luminance.

  Therefore, in order to uniformly control the light emission luminance over the entire screen of the display device, a mechanism for correcting the luminance variation caused by the characteristic variation of the driving active element and the electro-optical element described above in each pixel circuit. Various studies have been made.

JP 2006-215213 A

  For example, in the mechanism described in Patent Document 1, as a pixel circuit for an organic EL element, a threshold correction function for making the drive current constant even when the threshold voltage of the drive transistor varies or changes over time, In order to keep the driving current constant even when the mobility-correction function for making the driving current constant even when the mobility of the organic EL element varies or changes with time, or when the current-voltage characteristic of the organic EL element changes with time A bootstrap function has been proposed.

  However, in order to activate the threshold value correction function, the mobility correction function, and the bootstrap function, it is necessary to turn on / off various transistors, and for this purpose, various scanning lines are placed in the pixel array portion in the vertical direction and the horizontal direction. Need to be formed in the direction.

  When scanning lines extending in the same direction are run side by side in the same wiring layer, if the spacing between the wirings is narrow, that is, if they run close to each other, the wirings are electrically connected by foreign substances having conductivity during manufacturing. The yield may be reduced. The longer the scan line, the higher the possibility.

  Further, the mechanism described in Patent Document 1 adopts the 5TR drive configuration as described above, and the configuration of the pixel circuit is complicated. Since there are many components of a pixel circuit, it becomes a hindrance to high definition of a display apparatus. As a result, the 5TR drive configuration makes it difficult to apply to a display device used in a small electronic device such as a portable device (mobile device).

  For this reason, there is a demand for development of a mechanism that prevents the parallel scanning lines from being connected by foreign substances while simplifying the pixel circuit. At this time, it is possible to prevent the parallel scanning lines from being connected by foreign matter, and to prevent a new problem from occurring in the 5TR drive configuration as the pixel circuit is simplified. Should be considered.

  The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a mechanism capable of preventing connection of parallel scanning lines due to foreign matter and improving display characteristics.

  More preferably, it is an object of the present invention to provide a mechanism that enables high definition display devices by simplifying pixel circuits.

  Further, in order to simplify the pixel circuit, it is preferable to provide a mechanism capable of suppressing a change in luminance due to variation in characteristics of a drive transistor or an electro-optical element.

  One embodiment of a display device according to the present invention is a display device that emits electro-optic elements in a pixel circuit based on a video signal. First, in a pixel circuit arranged in a matrix in a pixel array unit, At least a drive transistor that generates a drive current, an electro-optical element connected to the output end of the drive transistor, a storage capacitor that holds information according to the signal potential of a video signal supplied via a video signal line, And a sampling transistor for writing information corresponding to the signal potential in the video signal to the storage capacitor. In this pixel circuit, the electro-optic element is caused to emit light by generating a drive current based on information held in the holding capacitor by the drive transistor and flowing it through the electro-optic element.

  Since the sampling transistor writes information corresponding to the signal potential into the holding capacitor, the sampling transistor takes in the signal potential at its input end (one of the source end or drain end) and outputs it (the other end of the source end or drain end) Information corresponding to the signal potential is written into the storage capacitor connected to the. Of course, the output terminal of the sampling transistor is also connected to the control input terminal of the drive transistor.

  The connection configuration of the pixel circuit shown here is the most basic 2TR configuration including two transistors such as a drive transistor and a sampling transistor, and the pixel circuit includes at least each of the above-described components. What is necessary is just a thing, and other than these components (namely, other components) may be included. Further, the “connection” is not limited to being directly connected, but may be connected via other components.

  For example, a change such as interposing a switching transistor or a functional unit having a certain function may be added between the connections as necessary. Typically, in order to dynamically control the display period (in other words, non-light emission time), a switching transistor is provided between the output terminal of the driving transistor and the electro-optical element, or the power supply terminal of the driving transistor. In some cases, the drain terminal is disposed between the power supply line which is a power supply wiring or the output terminal of the driving transistor and the reference voltage line.

  Even in a pixel circuit having such a modified mode, as long as the configuration and operation described in this section (means for solving the problem) can be realized, these modified modes are also displayed according to the present invention. 1 is a pixel circuit that implements an embodiment of an apparatus.

  Further, in the peripheral portion for driving the pixel circuit, for example, the pixel circuit is line-sequentially scanned by sequentially controlling the sampling transistors in the horizontal period, and the signal potential of the video signal is set to each holding capacitor for one row A writing scanning unit for writing the corresponding information and a control unit including a horizontal driving unit for controlling the video signal to be supplied to the sampling transistor in accordance with the line sequential scanning in the writing scanning unit are provided.

  In addition, the display device includes a drive signal stabilizing circuit that maintains the drive current constant. The drive signal stabilizing circuit is configured by a combination of connection modes of elements constituting the pixel circuit and a scanning unit that scans and drives the pixel circuit. Correspondingly, the control unit is provided with a scanning unit for controlling the drive signal stabilizing circuit.

  The drive signal stabilizing circuit means a circuit that tries to keep the drive current of the drive transistor constant even when the current-voltage characteristic of the electro-optic element changes with time or the drive transistor changes. The specific circuit configuration may be any. In addition to the sampling transistor (an example of a switching transistor) and a driving transistor, another switching transistor for performing control to keep the driving current constant may be provided.

  For example, preferably, the control unit performs control so as to perform a threshold correction operation for holding a voltage corresponding to the threshold voltage of the driving transistor in the holding capacitor. In the case of the 2TR configuration, it is preferable that a voltage corresponding to the first potential used to flow the driving current to the electro-optical element is supplied to the power supply terminal of the driving transistor and the reference potential in the video signal is supplied to the sampling transistor. When the sampling transistor is turned on during a certain time period, a voltage corresponding to the threshold voltage is held in the holding capacitor.

  For this reason, in the case of the 2TR configuration, it is preferable to output a scanning drive pulse for controlling the power supply applied to the power supply end of each drive transistor for one row in accordance with the line sequential scanning in the writing scanning unit. A drive scanning unit is provided in the control unit, and the horizontal drive unit supplies the sampling transistor with a video signal that is switched between the reference potential and the signal potential within each horizontal period. The sampling transistor functions as a switching transistor related to the drive signal stabilization function, and the on / off operation is controlled to realize the function.

  The threshold value correcting operation may be repeatedly executed at a plurality of horizontal periods preceding the writing of the signal potential to the storage capacitor as necessary. Here, “as necessary” means a case where a voltage corresponding to the threshold voltage of the driving transistor cannot be sufficiently held in the storage capacitor in the threshold correction period within one horizontal cycle. By executing the threshold correction operation a plurality of times, a voltage corresponding to the threshold voltage of the drive transistor is reliably held in the holding capacitor.

  More preferably, prior to the threshold value correcting operation, the control unit initializes the potentials and holding capacitors of the control input terminal and the output terminal of the driving transistor so that the potential difference between both ends is equal to or greater than the threshold voltage. To control. In the case of the 2TR configuration, it is preferable that the voltage corresponding to the second potential is supplied to the power supply end of the driving transistor and the reference potential is supplied to the input end (one of the source end or the drain end) of the sampling transistor. Thus, the sampling transistor is turned on to set the control input terminal of the drive transistor to the reference potential and the output terminal to the second potential.

  More preferably, when the control unit writes information corresponding to the signal potential in the storage capacitor by turning on the sampling transistor after the threshold correction operation, a correction for the mobility of the driving transistor is converted into a signal written in the storage capacitor. A mobility correction function that is controlled to be added is realized. At this time, in the case of the 2TR configuration, it is preferable that the sampling transistor is made conductive at a predetermined position within a time zone in which the signal potential is supplied to the sampling transistor for a period shorter than the time zone.

  More preferably, the storage capacitor is connected between the control input terminal and the output terminal side (actually one terminal side of the electro-optic element) of the driving transistor in order to realize the bootstrap function. When the information corresponding to the signal potential is written to the storage capacitor, the control unit turns off the sampling transistor to stop the supply of the video signal to the control input terminal of the drive transistor, and the potential of the output terminal of the drive transistor Control is performed so as to perform a bootstrap operation in which the potential of the control input terminal is interlocked with the fluctuation.

  In a normal pixel circuit, a vertical wiring for horizontal scanning and a horizontal wiring for vertical scanning are required. Therefore, basically, at least two-layer wiring is used for the overlap between the vertical wiring and the horizontal wiring. I need it. Here, as a characteristic matter in one embodiment of the display device according to the present invention, scanning lines (in parallel) in the pixel circuit or between two adjacent pixel circuits using the two-layer wiring ( All or part of the adjacent wiring) is laid out in different wiring layers. For adjacent wiring portions laid out in different wiring layers, even if a foreign substance having conductivity is placed on one of the layers, a situation in which the adjacent wiring is connected by the foreign substance does not occur.

  According to an embodiment of the present invention, all or part of adjacent wirings that run close to each other are laid out in different wiring layers, so that at least the portion of the adjacent wiring laid out in different wiring layers Since the same-layer short circuit between adjacent wirings due to conductive foreign substances cannot occur, a high yield can be realized.

  By laying out adjacent wirings that run in parallel in different wiring layers, it is possible to completely eliminate the possibility of a short circuit between adjacent wirings due to conductive foreign matter.

  On the other hand, if a part of adjacent wirings that run near each other is laid out in a different wiring layer, a short circuit between adjacent wirings due to conductive foreign substances may occur in some of the wiring layers. It cannot be completely eliminated. However, in part (that is, in the same layer), either vertical wiring or horizontal wiring, and cross wiring (horizontal wiring for vertical wiring, vertical wiring for horizontal wiring) ) Can be laid out in different wiring layers. This eliminates the need to overlap the interconnect by connecting the upper wiring and the lower wiring, and reduces the number of bridges (connecting the upper wiring and the lower wiring). Can be reduced.

  Here, how many wires run in parallel in the pixel circuit depends on the configuration of the pixel circuit. At this time, in realizing the threshold correction function and the threshold correction preparation function (initialization function) and mobility correction function preceding the threshold correction function, the power supply terminal of the drive transistor is changed between the first potential and the second potential. Using the power supply voltage as a switching pulse works effectively. That is, if the power supply voltage supplied to the drive transistor of each pixel circuit is used as a switching pulse in order to incorporate the threshold correction function and the mobility correction function, the correction switching transistor and the scanning line for controlling the control input terminal thereof are unnecessary. Become.

  As a result, it is only necessary to modify the drive timing of each transistor based on the 2TR drive configuration, the number of pixel circuit components and the number of wirings can be greatly reduced, the pixel array portion can be reduced, and the display It becomes easy to achieve high definition of the apparatus. While simplifying the pixel circuit, it is possible to prevent the same layer short-circuit between adjacent wirings due to conductive foreign substances. Since the number of elements and the number of wirings are small, it is suitable for high definition, and a small display device that requires high definition display can be easily realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<Overview of display device>
FIG. 1 is a block diagram showing an outline of a configuration of an active matrix display device which is an embodiment of a display device according to the present invention. In this embodiment, for example, an organic EL element is used as a display element (electro-optic element, light emitting element) of a pixel, a polysilicon thin film transistor (TFT) is used as an active element, and an organic film is formed on a semiconductor substrate on which a thin film transistor is formed. A case where the present invention is applied to an active matrix organic EL display (hereinafter referred to as “organic EL display device”) formed with EL elements will be described as an example.

  In the following, an organic EL element will be specifically described as an example of a pixel display element. However, this is merely an example, and the target display element is not limited to an organic EL element. In general, all embodiments described later can be applied to all display elements that emit light by current drive.

  As shown in FIG. 1, the organic EL display device 1 has an aspect ratio in which a pixel circuit (also referred to as a pixel) P having organic EL elements (not shown) as a plurality of display elements has a display aspect ratio. A display panel unit 100 arranged so as to constitute an effective video area of X: Y (for example, 9:16), and a drive that is an example of a panel control unit that generates various pulse signals for driving and controlling the display panel unit 100 A signal generation unit 200 and a video signal processing unit 300 are provided. The drive signal generation unit 200 and the video signal processing unit 300 are built in a one-chip IC (Integrated Circuit).

  As shown in the figure, the product form is provided as an organic EL display device 1 in the form of a module (composite part) including all of the display panel unit 100, the drive signal generation unit 200, and the video signal processing unit 300. For example, the organic EL display device 1 can be provided only by the display panel unit 100. Such an organic EL display device 1 is used in a display unit of a portable music player or other electronic device using a recording medium such as a semiconductor memory, a mini disk (MD), or a cassette tape.

  The display panel unit 100 includes a pixel array unit 102 in which pixel circuits P are arranged in a matrix of n rows × m columns on a substrate 101, a vertical drive unit 103 that scans the pixel circuits P in the vertical direction, and pixels A horizontal driving unit (also referred to as a horizontal selector or a data line driving unit) 106 that scans the circuit P in the horizontal direction, a terminal unit (pad unit) 108 for external connection, and the like are integrated. That is, peripheral drive circuits such as the vertical drive unit 103 and the horizontal drive unit 106 are formed on the same substrate 101 as the pixel array unit 102.

  The vertical drive unit 103 includes, for example, a write scan unit (write scanner WS; Write Scan) 104 and a drive scan unit (drive scanner DS; Drive Scan) 105 that functions as a power supply scanner having power supply capability.

  The vertical drive unit 103 and the horizontal drive unit 106 constitute a control unit 109 that controls writing of a signal potential to a storage capacitor, threshold correction operation, mobility correction operation, and bootstrap operation.

  The configuration of the illustrated vertical drive unit 103 and the corresponding scanning line is shown in conformity with the case where the pixel circuit P has a 2TR configuration of the present embodiment described later. However, depending on the configuration of the pixel circuit P, other configurations may be used. A scanning unit may be provided.

  For example, the pixel array unit 102 is driven by the writing scanning unit 104 and the driving scanning unit 105 from one side or both sides in the horizontal direction shown in the figure, and driven by the horizontal driving unit 106 from one side or both sides in the vertical direction shown in the figure. It has come to be.

  Various pulse signals are supplied to the terminal unit 108 from the drive signal generation unit 200 arranged outside the organic EL display device 1. Similarly, the video signal Vsig is supplied from the video signal processing unit 300.

  As an example, necessary pulse signals such as shift start pulses SPDS and SPWS and vertical scanning clocks CKDS and CKWS, which are examples of vertical write start pulses, are supplied as pulse signals for vertical driving. Further, necessary pulse signals such as a horizontal start pulse SPH and a horizontal scanning clock CKH, which are examples of horizontal write start pulses, are supplied as pulse signals for horizontal driving.

  Each terminal of the terminal unit 108 is connected to the vertical driving unit 103 and the horizontal driving unit 106 via a wiring 199. For example, each pulse supplied to the terminal unit 108 is internally adjusted to a voltage level by a level shifter unit (not shown) as necessary, and then supplied to each unit of the vertical driving unit 103 and the horizontal driving unit 106 via a buffer. Supplied.

  Although the pixel array unit 102 is not shown in the drawing (details will be described later), pixel circuits P in which pixel transistors are provided with respect to an organic EL element as a display element are two-dimensionally arranged in a matrix form. On the other hand, scanning lines are wired for each row, and signal lines are wired for each column.

  For example, the pixel array unit 102 includes a scanning line (gate line) 104WS, a power supply line 105DSL, and a video signal line (data line) 106HS. An organic EL element (not shown) and a thin film transistor (TFT) for driving the organic EL element are formed at the intersection of the two. A pixel circuit P is configured by a combination of an organic EL element and a thin film transistor.

  Specifically, for each pixel circuit P arranged in a matrix, the write scanning lines 104WS_1 to 104WS_n for n rows driven by the write scanning unit 104 with the write drive pulse WS and the drive scanning unit Power supply lines 105DSL_1 to 105DSL_n for n rows driven by the power supply drive pulse DSL by 105 are wired for each pixel row.

  The writing scanning unit 104 and the driving scanning unit 105 sequentially select the pixel circuits P via the writing scanning line 104WS and the power supply line 105DSL based on the vertical driving system pulse signal supplied from the driving signal generation unit 200. To do. The horizontal driving unit 106 samples a predetermined potential in the video signal Vsig to the selected pixel circuit P via the video signal line 106HS based on the horizontal driving system pulse signal supplied from the driving signal generation unit 200. To write to the holding capacity.

  In the organic EL display device 1 of the present embodiment, line-sequential driving is considered as an example, and the writing scanning unit 104 and the driving scanning unit 105 of the vertical driving unit 103 are pixel-sequentially (that is, in units of rows). While scanning 102, the horizontal driving unit 106 writes an image signal to the pixel array unit 102 simultaneously for one horizontal line in synchronization with this.

  For example, the horizontal drive unit 106 is configured to include a driver circuit that simultaneously turns on the switches that are omitted from the illustration provided on the video signal lines 106HS of all the columns in order to support line-sequential driving, and the video signal processing unit A switch that omits the illustration provided on the video signal lines 106HS of all the columns in order to simultaneously write the pixel signals input from 300 to all the pixel circuits P for one line of the row selected by the vertical driving unit 103. Turn on all at once.

  Each unit of the vertical driving unit 103 is configured by a combination of logic gates (including latches) in order to support line sequential driving, and selects each pixel circuit P of the pixel array unit 102 in units of rows. FIG. 1 shows a configuration in which the vertical drive unit 103 is disposed only on one side of the pixel array unit 102. However, a configuration in which the vertical drive unit 103 is disposed on both the left and right sides with the pixel array unit 102 interposed therebetween is employed. Is also possible.

  Similarly, FIG. 1 shows a configuration in which the horizontal drive unit 106 is disposed only on one side of the pixel array unit 102, but a configuration in which the horizontal drive unit 106 is disposed on both upper and lower sides with the pixel array unit 102 interposed therebetween is employed. It is also possible.

<Pixel circuit>
FIG. 2 is a diagram showing a first comparative example for the pixel circuit P of the present embodiment that constitutes the organic EL display device 1 shown in FIG. Note that a vertical driving unit 103 and a horizontal driving unit 106 provided on the periphery of the pixel circuit P on the substrate 101 of the display panel unit 100 are also shown.

  FIG. 3 is a diagram illustrating a second comparative example for the pixel circuit P of the present embodiment. Note that a vertical driving unit 103 and a horizontal driving unit 106 provided on the periphery of the pixel circuit P on the substrate 101 of the display panel unit 100 are also shown.

  FIG. 4 is a diagram for explaining the operating points of the organic EL element and the driving transistor. FIG. 4A is a diagram for explaining the influence of variations in characteristics of organic EL elements and drive transistors on the drive current Ids.

  FIG. 5 is a diagram illustrating a configuration example of the pixel circuit P of the present embodiment. Note that a vertical driving unit 103 and a horizontal driving unit 106 provided on the periphery of the pixel circuit P on the substrate 101 of the display panel unit 100 are also shown.

<Pixel Circuit of Comparative Example: First Example>
As shown in FIG. 2, the pixel circuit P of the first comparative example is characterized in that a drive transistor is basically composed of a p-channel type thin film field effect transistor (TFT). In addition to the drive transistor, a 3Tr drive configuration using two transistors for scanning is adopted.

  Specifically, the pixel circuit P of the first comparative example is supplied with a p-channel driving transistor 121, a p-channel light emission control transistor 122 to which an active L driving pulse is supplied, and an active H driving pulse. An n-channel sampling transistor 125, an organic EL element 127 that is an example of an electro-optical element (light-emitting element) that emits light when current flows, and a storage capacitor (also referred to as a pixel capacitor) 120 are included. The drive transistor 121 supplies a drive current corresponding to the potential supplied to the gate terminal G, which is a control input terminal, to the organic EL element 127.

  In general, the sampling transistor 125 can be replaced with a p-channel type to which an active L driving pulse is supplied. The light emission control transistor 122 can be replaced with an n-channel type to which an active H driving pulse is supplied.

  The sampling transistor 125 is a switching transistor provided on the gate end G (control input terminal) side of the driving transistor 121, and the light emission control transistor 122 is also a switching transistor.

  In general, the organic EL element 127 is represented by a diode symbol because of its rectifying property. The organic EL element 127 has a parasitic capacitance Cel. In the figure, this parasitic capacitance Cel is shown in parallel with the organic EL element 127.

  The pixel circuit P is disposed at the intersection of the scanning lines 104WS and 105DS on the vertical scanning side and the video signal line 106HS which is a scanning line on the horizontal scanning side. The write scan line 104WS from the write scan unit 104 is connected to the gate terminal G of the sampling transistor 125, and the drive scan line 105DS from the drive scan unit 105 is connected to the gate terminal G of the light emission control transistor 122.

  The sampling transistor 125 is connected to the video signal line 106HS with the source terminal S as a signal input terminal, connected to the gate terminal G of the driving transistor 121 with the drain terminal D as a signal output terminal, and the connection point and the second power supply potential Vc2 ( For example, the storage capacitor 120 is provided between the positive power supply voltage and the first power supply potential Vc1. As shown in parentheses, the sampling transistor 125 reverses the source end S and the drain end D, connects the drain end D as a signal input end to the video signal line 106HS, and uses the source end S as a signal output end as a drive transistor. It can also be connected to the gate end G of 121.

  The drive transistor 121, the light emission control transistor 122, and the organic EL element 127 are connected in series in this order between the first power supply potential Vc1 (for example, a positive power supply voltage) and a ground potential GND that is an example of a reference potential. Specifically, the drive transistor 121 has a source terminal S connected to the first power supply potential Vc 1 and a drain terminal D connected to the source terminal S of the light emission control transistor 122. The drain terminal D of the light emission control transistor 122 is connected to the anode terminal A of the organic EL element 127, and the cathode terminal K of the organic EL element 127 is connected to the ground potential GND.

  As a simpler configuration, in the configuration of the pixel circuit P shown in FIG. 2, a 2Tr drive configuration in which the light emission control transistor 122 is removed can be adopted as the simplest circuit. In this case, the organic EL display device 1 has a configuration in which the drive scanning unit 105 is removed.

  In any of the 3Tr driving shown in FIG. 2 and the 2Tr driving omitted in the drawing, the organic EL element 127 is a current light emitting element, so that the color tone is obtained by controlling the amount of current flowing through the organic EL element 127. Therefore, the value of the current flowing through the organic EL element 127 is controlled by changing the voltage applied to the gate terminal G of the drive transistor 121.

  Specifically, first, an active H write drive pulse WS is supplied from the write scan unit 104 to set the write scan line 104WS in a selected state, and when the pixel signal Vsig is applied to the signal line 106HS from the horizontal drive unit 106, The n-channel sampling transistor 125 is turned on, and the pixel signal Vsig is written into the storage capacitor 120.

  The signal potential written in the storage capacitor 120 becomes the potential of the gate terminal G of the driving transistor 121. Subsequently, when the write drive pulse WS is made inactive (L level in this example) to make the write scan line 104WS in a non-selected state, the signal line 106HS and the drive transistor 121 are electrically disconnected, but the drive transistor In principle, the gate-source voltage Vgs 121 is stably held by the holding capacitor 120.

  Subsequently, when an active-L scanning drive pulse DS is supplied from the drive scanning unit 105 and the drive scanning line 105DS is selected, the p-channel type light emission control transistor 122 becomes conductive, and the ground potential GND from the first power supply potential Vc1. A drive current flows through the drive transistor 121, the light emission control transistor 122, and the organic EL element 127.

  Next, when the scanning drive pulse DS is inactive (H level in this example) and the drive scanning line 105DS is in a non-selected state, the light emission control transistor 122 is turned off and the drive current does not flow.

  The light emission control transistor 122 is inserted in order to control the light emission time (duty) of the organic EL element 127 occupying one field period. As estimated from the above description, as the pixel circuit P, It is not essential that the light emission control transistor 122 is provided.

  The current flowing through the drive transistor 121 and the organic EL element 127 has a value corresponding to the gate-source voltage Vgs of the drive transistor 121, and the organic EL element 127 continues to emit light with a luminance corresponding to the current value.

  The operation of selecting the writing scanning line 104WS and transmitting the pixel signal Vsig applied to the signal line 106HS to the inside of the pixel circuit P in this way is hereinafter referred to as “writing”. In this way, once the signal is written, the organic EL element 127 continues to emit light with a constant luminance until the next rewriting.

  Thus, in the pixel circuit P of the first comparative example, the current flowing through the EL organic EL element 127 is changed by changing the applied voltage supplied to the gate terminal G of the drive transistor 121 according to the input signal (pixel signal Vsig). The value is controlled. At this time, the source terminal S of the p-channel type driving transistor 121 is connected to the first power supply potential Vc1, and this driving transistor 121 always operates in the saturation region.

<Pixel Circuit of Comparative Example: Second Example>
Next, a pixel circuit P of the second comparative example shown in FIG. 3 will be described as a comparative example for explaining the characteristics of the pixel circuit P of the present embodiment. The organic EL display device 1 including the pixel circuit P of the second comparative example in the pixel array unit 102 is referred to as an organic EL display device 1 of the second comparative example.

  The pixel circuit P of the second comparative example and this embodiment is characterized in that a drive transistor is basically composed of an n-channel thin film field effect transistor.

  If a driving transistor can be formed of an n-channel transistor instead of a p-channel transistor, a conventional amorphous silicon (a-Si) process can be used in transistor formation. Thereby, the cost of the transistor substrate can be reduced, and the development of the pixel circuit P having such a configuration is expected.

  The pixel circuit P of the second comparative example is the same as that of the present embodiment in that the drive transistor is basically composed of an n-channel thin film field effect transistor, but the drive current due to deterioration with time of the organic EL element 127. There is no drive signal stabilization circuit for preventing the influence on Ids.

  Specifically, the pixel circuit P of the second comparative example is an n-channel driving transistor 121, a light emission control transistor 122, and a sampling transistor 125, and is an organic electro-optical element that emits light when a current flows. EL element 127.

  The drive transistor 121 has a drain terminal D connected to the first power supply potential Vc 1 and a source terminal S connected to the drain terminal D of the light emission control transistor 122. The source terminal S of the light emission control transistor 122 is connected to the anode terminal A of the organic EL element 127, and the cathode terminal K of the organic EL element 127 is connected to the ground potential GND. In such a pixel circuit P, the drain end D side of the drive transistor 121 is connected to the first power supply potential Vc1, and the source end S is connected to the anode end A side of the organic EL element 127, so that the source follower circuit as a whole. Is supposed to form.

  The sampling transistor 125 has a source terminal S connected to the video signal line HS, a drain terminal D connected to the gate terminal (control input terminal) G of the driving transistor 121, and the connection point and the second power supply potential Vc2 (for example, a positive power supply). A storage capacitor 120 is provided between a reference line for supplying a voltage, which may be the same as the first power supply potential Vc1). As shown in parentheses, the sampling transistor 125 may have a connection mode in which the source end S and the drain end D are reversed.

  In such a pixel circuit P, regardless of whether or not the light emission control transistor is provided, when driving the organic EL element 127, the drain end D side of the drive transistor 121 is connected to the first power supply potential Vc1, and the source end S is By being connected to the anode end A side of the organic EL element 127, a source follower circuit is formed as a whole.

  As a simpler configuration, the configuration of the pixel circuit P shown in FIG. 3 can also employ a 2Tr drive configuration in which the light emission control transistor 122 is removed as the simplest circuit. In this case, the organic EL display device 1 has a configuration in which the drive scanning unit 105 is removed.

  Next, the operation of the pixel circuit P of the second comparative example shown in FIG. 3 will be described. Here, the operation of the light emission control transistor 122 will be omitted. First, an organic EL element which is an example of a light emitting element is sampled by sampling a potential (referred to as a signal potential) in an effective period within a potential (hereinafter also referred to as a video signal line potential) of a video signal Vsig supplied from a signal line HS. 127 is turned on.

  Specifically, when the video signal line 106HS is at a signal potential that is the effective period of the video signal Vsig, the potential of the write scanning line WS transitions to a high level, whereby the n-channel sampling transistor 125 is The storage capacitor 120 is charged with the video signal line potential supplied from the signal line HS. As a result, the potential of the gate terminal G (gate potential Vg) of the drive transistor 121 starts to rise and starts to flow a drain current. Therefore, the anode potential of the organic EL element 127 rises and light emission starts.

  Thereafter, when the write drive pulse WS transitions to a low level, the holding capacitor 120 holds the video signal line potential at that time, that is, the potential (signal potential) in the effective period within the potential of the video signal Vsig. As a result, the gate potential Vg of the drive transistor 121 becomes constant, and the light emission luminance is kept constant until the next frame (or field). A period during which the potential of the write scanning line WS is at a high level is a sampling period of the video signal Vsig, and a period after the write drive pulse WS is transitioned to a low level is a holding period.

<Iel-Vel Characteristics of Light-Emitting Element and IV Characteristics of Driving Transistor>
In general, as shown in FIG. 4, the drive transistor 121 is driven in a saturation region where the drive current Ids is constant regardless of the drain-source voltage. Therefore, the current flowing between the drain end and the source of the transistor operating in the saturation region is Ids, the mobility is μ, the channel width (gate width) is W, the channel length (gate length) is L, and the gate capacitance (per unit area). When the gate oxide film capacitance) is Cox and the threshold voltage of the transistor is Vth, the driving transistor 121 is a constant current source having a value shown in the following equation (1). “^” Indicates a power. As apparent from the equation (1), in the saturation region, the drain current Ids of the transistor is controlled by the gate-source voltage Vgs and operates as a constant current source.

  However, in general, the IV characteristics of current-driven light-emitting elements such as organic EL elements deteriorate as time passes, as shown in FIG. 4A (1). In the current-voltage (Iel-Vel) characteristics of a current-driven light-emitting element typified by the organic EL element shown in FIG. 4A (1), the curve indicated by the solid line indicates the characteristic in the initial state, and the curve indicated by the broken line indicates The characteristic after change with time is shown.

  For example, when the light emission current Iel flows through the organic EL element 127 which is an example of the light emitting element, the anode-cathode voltage Vel is uniquely determined. However, as shown in FIG. 4A (1), during the light emission period, the anode A of the organic EL element 127 has a light emission current Iel determined by the drain-source current Ids (= drive current Ids) of the drive transistor 121. As a result, the anode-cathode voltage Vel of the organic EL element 127 rises.

  In the pixel circuit P of the first comparative example shown in FIG. 2, the increase in the anode-cathode voltage Vel of the organic EL element 127 appears on the drain terminal D side of the drive transistor 121, but the drive transistor 121 is saturated. Since constant current driving operates in a region, the constant current Ids continues to flow through the organic EL element 127, and even if the Iel-Vel characteristic of the organic EL element 127 deteriorates, the emission luminance does not deteriorate over time.

  The organic EL element 127, which is an example of an electro-optical element, has the configuration of the pixel circuit P that includes the drive transistor 121, the light emission control transistor 122, the storage capacitor 120, and the sampling transistor 125 and has the connection mode illustrated in FIG. A drive signal stabilization circuit that corrects changes in current-voltage characteristics and maintains the drive current constant is configured.

  That is, when the pixel circuit P is driven by the video signal Vsig, the source terminal S of the p-channel type driving transistor 121 is connected to the first power supply potential Vc1, and is designed to always operate in the saturation region. The constant current source has the value shown in the equation (1).

  In the pixel circuit P of the first comparative example, the voltage at the drain terminal D of the drive transistor 121 changes with the time-dependent change of the Iel-Vel characteristic of the organic EL element 127 (FIG. 4A (1)). Since the gate-source voltage Vgs is held constant in principle by the bootstrap function of the storage capacitor 120, the drive transistor 121 operates as a constant current source. , A constant amount of current flows, and the organic EL element 127 can emit light with constant luminance, and the light emission luminance does not change.

  Also in the pixel circuit P of the second comparative example, the potential of the source terminal S (source potential Vs) of the drive transistor 121 is determined by the operating point of the drive transistor 121 and the organic EL element 127, and the drive transistor 121 is driven in the saturation region. Therefore, with respect to the gate-source voltage Vgs corresponding to the source voltage at the operating point, the drive current Ids having the current value defined in the above equation (1) is passed.

  However, in a simple circuit (pixel circuit P of the second comparative example) in which the p-channel driving transistor 121 of the pixel circuit P of the first comparative example is changed to an n-channel type, the source end S is on the organic EL element 127 side. It will be connected. As a result, the anode-cathode voltage Vel for the same emission current Iel changes from Vel1 to Vel2 due to the Iel-Vel characteristic of the organic EL element 127 that deteriorates with time as shown in FIG. 4A (1). The operating point of the driving transistor 121 changes, and the source potential Vs of the driving transistor 121 changes even when the same gate potential Vg is applied. As a result, the gate-source voltage Vgs of the drive transistor 121 changes.

  As is clear from the characteristic equation (1), when the gate-source voltage Vgs varies, the drive current Ids varies even if the gate potential Vg is constant, and the current value (light emission current) flowing through the organic EL element 127 at the same time. Iel) changes, and the light emission luminance changes.

  As described above, in the pixel circuit P of the second comparative example, the anode potential variation of the organic EL element 127 due to the temporal variation of the Iel-Vel characteristic of the organic EL element 127 which is an example of the light emitting element is caused between the gate and the source of the driving transistor 121. It appears as a fluctuation in the voltage Vgs and causes a fluctuation in the drain current (drive current Ids). Variations in the drive current Ids due to this cause appear as variations in light emission luminance and temporal variations for each pixel circuit P, resulting in degradation of image quality.

  On the other hand, as will be described in detail later, even when the n-channel type driving transistor 121 is used, the potential Vg of the gate terminal G is interlocked with the fluctuation of the potential Vs of the source terminal S of the driving transistor 121. By adopting a circuit configuration and driving timing for realizing the bootstrap function, even if there is an anode potential fluctuation of the organic EL element 127 (that is, a source potential fluctuation of the driving transistor 121) due to a change in characteristics of the organic EL element 127 over time, The gate potential Vg is varied so as to cancel the variation. Thereby, the uniformity (uniformity) of screen luminance can be secured. With the bootstrap function, it is possible to improve the temporal variation correction capability of a current-driven light-emitting element typified by an organic EL element.

  Of course, in the bootstrap function, the light emission current Iel begins to flow through the organic EL element 127 at the start of light emission, and as a result, the anode-cathode voltage Vel rises until it becomes stable. It also functions when the source potential Vs of the drive transistor 121 varies with the variation of the voltage Vel.

<Vgs-Ids characteristics of drive transistor>
In the first and second comparative examples, the characteristics of the drive transistor 121 are not particularly problematic. However, if the characteristics of the drive transistor 121 are different for each pixel, the influence of the drive current Ids flowing in the drive transistor 121 is affected. Affects. As an example, as can be seen from the equation (1), when the mobility μ and the threshold voltage Vth vary from pixel to pixel or change with time, the drive transistor 121 can be used even if the gate-source voltage Vgs is the same. The drive current Ids flowing through the output varies and changes with time, and the light emission luminance of the organic EL element 127 changes for each pixel.

  For example, due to variations in the manufacturing process of the drive transistor 121, there are variations in characteristics such as threshold voltage Vth and mobility μ for each pixel circuit P. Even when the driving transistor 121 is driven in the saturation region, even if the same gate potential is applied to the driving transistor 121 due to this characteristic variation, the drain current (driving current Ids) varies for each pixel circuit P, and the emission luminance is reduced. Appears as variations.

  For example, FIG. 4A (2) is a diagram showing voltage-current (Vgs-Ids) characteristics focusing on threshold variation of the drive transistor 121. FIG. A characteristic curve is given for each of the two drive transistors 121 having different threshold voltages of Vth1 and Vth2.

  As described above, the drain current Ids when the driving transistor 121 operates in the saturation region is expressed by the characteristic formula (1). As apparent from the characteristic equation (1), when the threshold voltage Vth varies, the drain current Ids varies even if the gate-source voltage Vgs is constant. That is, if no countermeasure is taken against the variation of the threshold voltage Vth, the drive current corresponding to Vgs becomes Ids1 when the threshold voltage is Vth1, as shown in FIG. The drive current Ids2 corresponding to the same gate voltage Vgs when is Vth2 is different from Ids1.

  FIG. 4A (3) is a diagram showing voltage-current (Vgs-Ids) characteristics focusing on the mobility variation of the drive transistor 121. FIG. Characteristic curves are given for two drive transistors 121 having different mobility in μ1 and μ2.

  As apparent from the characteristic equation (1), when the mobility μ varies, the drain current Ids varies even when the gate-source voltage Vgs is constant. In other words, if no countermeasure is taken against the variation in mobility μ, the drive current corresponding to Vgs becomes Ids1 when the mobility is μ1, as shown in FIG. When I is μ2, the drive current corresponding to the same gate voltage Vgs becomes Ids2, which is different from Ids1.

  As shown in FIGS. 4A (2) and 4A (3), if a large difference occurs in the Vin-Ids characteristic due to a difference in threshold voltage Vth or mobility μ, even if the same signal amplitude Vin is given, the drive current Ids, that is, the light emission luminance differs, and the uniformity of screen luminance cannot be obtained.

<Concept of threshold correction and mobility correction>
On the other hand, by setting the drive timing (details will be described later) to realize the threshold value correction function and the mobility correction function, the influence of these fluctuations can be suppressed, and the uniformity of the screen luminance (uniformity) can be ensured. .

  Although details will be described later in the threshold value correcting operation and the mobility correcting operation of this embodiment, when it is assumed that the writing gain is 1 (ideal value), the gate-source voltage Vgs at the time of light emission is “Vin + Vth−ΔV”. Thus, the drain-source current Ids is not dependent on the variation or variation of the threshold voltage Vth, and is not dependent on the variation or variation of the mobility μ. As a result, even if the threshold voltage Vth and the mobility μ fluctuate due to the manufacturing process and time, the driving current Ids does not fluctuate and the light emission luminance of the organic EL element 127 does not fluctuate.

  At the time of mobility correction, the mobility correction parameter ΔV1 is increased for a large mobility μ1, while negative feedback is applied so that the mobility correction parameter ΔV2 is also decreased for a small mobility μ2. Become. In this sense, the mobility correction parameter ΔV is also referred to as a negative feedback amount ΔV.

<Pixel Circuit of this Embodiment>
In the pixel circuit P of the second comparative example shown in FIG. 3, a circuit (bootstrap circuit) for preventing fluctuations in the drive current due to deterioration with time of the organic EL element 127 is mounted, and characteristic fluctuations in the drive transistor 121 (threshold voltage fluctuations and mobility). The pixel circuit P of this embodiment shown in FIG. 5 employs a driving method that prevents fluctuations in the driving current due to variations. The organic EL display device 1 including the pixel circuit P of the present embodiment in the pixel array unit 102 is referred to as the organic EL display device 1 of the present embodiment.

  Similar to the pixel circuit P of the second comparative example, the pixel circuit P of the present embodiment uses an n-channel driving transistor 121. In addition, the circuit for suppressing the fluctuation of the drive current Ids to the organic EL element due to the deterioration of the organic EL element with time, that is, the change of the current-voltage characteristic of the organic EL element which is an example of the electro-optical element is corrected. The present invention is characterized in that a drive signal stabilizing circuit for maintaining the drive current Ids constant is provided. Further, the organic EL element is characterized in that it has a function of keeping the driving current constant even when the current-voltage characteristic of the organic EL element changes with time.

  That is, a 2TR drive configuration using one switching transistor (sampling transistor 125) for scanning in addition to the drive transistor 121 is adopted, and the power supply drive pulse DSL and the write drive pulse WS for controlling each switching transistor are turned on / off. This is characterized in that setting the off timing prevents influence on the drive current Ids due to deterioration with time of the organic EL element 127 and fluctuations in characteristics of the drive transistor 121 (for example, variations and fluctuations in threshold voltage, mobility, etc.).

  Since it has a 2TR drive configuration and the number of elements and wirings is small, high definition can be achieved, and in addition, sampling can be performed without deterioration of the video signal Vsig, so that good image quality can be obtained.

  A major difference in configuration with respect to the second comparative example shown in FIG. 3 is that the connection mode of the storage capacitor 120 is modified to prevent the drive current from changing due to the deterioration of the organic EL element 127 over time. This is in the configuration of a bootstrap circuit which is an example of a circuit. As a method of suppressing the influence on the drive current Ids due to the characteristic variation of the drive transistor 121 (for example, variation or fluctuation in threshold voltage, mobility, etc.), this is dealt with by devising the drive timing of each of the transistors 121 and 125.

  Specifically, the pixel circuit P of the present embodiment includes a storage capacitor 120, an n-channel driving transistor 121, and an n-channel sampling transistor 125 to which an active H (high) write driving pulse WS is supplied. An organic EL element 127 which is an example of an electro-optical element (light emitting element) that emits light when a current flows is included.

  The storage capacitor 120 is connected between the gate terminal G (node ND122) of the driving transistor 121 and the source terminal S, and the source terminal S of the driving transistor 121 is directly connected to the anode terminal A of the organic EL element 127. The storage capacitor 120 functions also as a bootstrap capacitor. The cathode terminal K of the organic EL element 127 is set to a cathode potential Vcath as a reference potential. Preferably, the cathode potential Vcath is connected to a common wiring Vcath (preferably GND) for supplying a reference potential as in the second comparative example shown in FIG.

  The drain terminal D of the drive transistor 121 is connected to a power supply line 105DSL from the drive scanning unit 105 that functions as a power scanner. The power supply line 105DSL is characterized in that the power supply line 105DSL itself has a power supply capability to the drive transistor 121.

  Specifically, the drive scanning unit 105 supplies the first voltage Vcc on the high voltage side and the second voltage Vss on the low voltage side by switching to the drain terminal D of the drive transistor 121, respectively. A power supply voltage switching circuit is provided.

  The second potential Vss is set to a potential sufficiently lower than the reference potential Vo (also referred to as offset potential Vofs) of the video signal Vsig in the video signal line 106HS. Specifically, the gate-source voltage Vgs of the drive transistor 121 (the difference between the gate potential Vg and the source potential Vs) is larger than the threshold voltage Vth of the drive transistor 121. Two potential Vss is set. The offset potential Vofs is used for an initialization operation prior to the threshold correction operation and also used for precharging the video signal line 106HS in advance.

  The sampling transistor 125 has a gate terminal G connected to the writing scanning line 104WS from the writing scanning unit 104, a drain terminal D connected to the video signal line 106HS, and a source terminal S connected to the gate terminal G (node) of the driving transistor 121. ND122). The gate terminal G is supplied with an active H write drive pulse WS from the write scanning unit 104.

  The sampling transistor 125 may have a connection mode in which the source terminal S and the drain terminal D are reversed. As the sampling transistor 125, either a depletion type or an enhancement type can be used.

<Operation of Pixel Circuit of this Embodiment>
FIG. 6 is a timing chart for explaining a basic example of the drive timing of the present embodiment relating to the pixel circuit P of the present embodiment shown in FIG. 6B to 6L are diagrams illustrating an equivalent circuit and an operation state in each period of the timing chart illustrated in FIG. FIG. 7 is a diagram showing a change in the source potential Vs of the drive transistor 121 during the threshold correction operation. FIG. 7A is a diagram showing a change in the source potential Vs of the drive transistor 121 during the mobility correction operation.

  In the following, for ease of explanation and understanding, unless otherwise specified, it is assumed that the write gain is 1 (ideal value), and information on the signal amplitude Vin is written and held in the holding capacitor 120. Or it will be described briefly as sampling. When the write gain is less than 1, not the magnitude of the signal amplitude Vin itself but the gain multiplied information corresponding to the magnitude of the signal amplitude Vin is held in the holding capacitor 120.

  Incidentally, the ratio of the size of information written in the storage capacitor 120 corresponding to the signal amplitude Vin is referred to as a write gain Ginput. Here, the write gain Ginput is specifically the total capacitance C1 including the parasitic capacitance arranged in parallel with the holding capacitor 120 in terms of electrical circuit, and the total capacitance C1 arranged in series with the holding capacitor 120 in terms of electrical circuit. This is related to the amount of charge distributed to the capacitor C1 when the signal amplitude Vin is supplied to the capacitor series circuit in the capacitor series circuit with the capacitor C2. In terms of an expression, when g = C1 / (C1 + C2), the write gain Ginput = C2 / (C1 + C2) = 1−C1 / (C1 + C2) = 1−g. In the following description, “g” appears in consideration of the write gain.

  For ease of explanation and understanding, unless otherwise noted, the bootstrap gain is assumed to be 1 (ideal value) and will be described briefly. Incidentally, when the storage capacitor 120 is provided between the gate and the source of the driving transistor 121, the rate of increase of the gate potential Vg with respect to the increase of the source potential Vs is referred to as bootstrap gain (bootstrap operation capability) Gbst. Here, the bootstrap gain Gbst is specifically formed between the capacitance value Cs of the storage capacitor 120, the capacitance value Cgs of the parasitic capacitance C121gs formed between the gate and source of the drive transistor 121, and between the gate and drain. This is related to the capacitance value Cgd of the parasitic capacitance C121gd and the capacitance value Cws of the parasitic capacitance C125gs formed between the gate and the source of the sampling transistor 125. Expressed by the equation, the bootstrap gain Gbst = (Cs + Cgs) / (Cs + Cgs + Cgd + Cws).

  In FIG. 6, the change in the potential of the write scanning line 104WS, the change in the potential of the power supply line 105DSL, and the change in the potential of the video signal line 106HS are shown with a common time axis. In parallel with these potential changes, changes in the gate potential Vg and source potential Vs of the drive transistor 121 are also shown for one row (the first row in the figure).

  Basically, the same driving is performed for each row of the write scanning line 104WS and the power supply line 105DSL with a delay of one horizontal scanning period. Each timing and signal in FIG. 6 are indicated by the same timing and signal as the timing and signal of the first row regardless of the processing target row. When distinction is required in the description, the processing target row is indicated by a reference with “_” in the timing and signal.

  In the drive timing of the present embodiment, the period in which the video signal Vsig is at the offset potential Vofs, which is the ineffective period, is the first half of one horizontal period, and the period in which the signal potential is in the effective period (Vofs + Vin) is one horizontal. The second half of the period. Further, the threshold value correcting operation is repeated three times for each horizontal period including the effective period and the ineffective period of the video signal Vsig. The switching timing (t13V, t15V) between the effective period and the ineffective period of the video signal Vsig and the switching timing (t13W, t15W) of the write drive pulse WS active and inactive are set at the respective times. Distinguish by indicating with a reference without "_".

  In the present embodiment, the threshold correction operation is repeated three times with one horizontal period as a processing cycle. However, this repeated operation is not essential, and the threshold value is only once with one horizontal period as a processing cycle. You may make it perform correction | amendment operation | movement.

  One horizontal period becomes a processing cycle of the threshold correction operation, for each row, before the threshold correction operation, the sampling transistor 125 samples the information of the signal amplitude Vin into the storage capacitor 120. After the initialization operation of setting the potential to the second potential Vss, setting the gate of the driving transistor 121 to the offset potential Vofs, and further setting the source potential to the second potential Vss, the potential of the power supply line 105DSL is changed to the first potential Vss. A threshold value for causing the holding capacitor 120 to hold a voltage corresponding to the threshold voltage Vth of the drive transistor 121 by turning on the sampling transistor 125 in a time zone in which the video signal line 106HS is at the offset potential Vofs in a state where it is at one potential Vcc. This is because a correction operation is performed.

  Inevitably, the threshold correction period is shorter than one horizontal period. Accordingly, due to the magnitude relationship between the capacitance Cs and the second potential Vss of the storage capacitor 120 and other factors, the storage capacitor 120 holds an accurate voltage corresponding to the threshold voltage Vth in this short threshold correction operation period. There may be no cases. In the present embodiment, the threshold correction operation is executed a plurality of times for this purpose. That is, the voltage corresponding to the threshold voltage Vth of the drive transistor 121 is reliably obtained by repeatedly executing the threshold correction operation in a plurality of horizontal periods preceding the sampling (signal writing) of the information of the signal amplitude Vin to the storage capacitor 120. Is held in the holding capacitor 120.

  For a certain row (here, the first row), in the light emission period B of the previous field before timing t11, the write drive pulse WS is inactive L and the sampling transistor 125 is in a non-conducting state, while power supply drive The pulse DSL is at the first potential Vcc which is the high potential power supply voltage side.

  Therefore, as shown in FIG. 6B, regardless of the potential of the video signal line 106HS, the organic state depends on the voltage state (the gate-source voltage Vgs of the driving transistor 121) held in the holding capacitor 120 by the operation of the previous field. The drive current Ids is supplied from the drive transistor 121 to the EL element 127 and flows into the wiring Vcath (preferably GND) common to all pixels, whereby the organic EL element 127 is in a light emitting state. At this time, since the driving transistor 121 is set to operate in the saturation region, the driving current Ids flowing through the organic EL element 127 depends on the gate-source voltage Vgs of the driving transistor 121 held in the holding capacitor 120. The value shown in equation (1) is taken.

  Thereafter, a new field of line sequential scanning is entered. First, the drive scanning unit 105 supplies a power drive pulse DSL_1 to be supplied to the power supply line 105DSL_1 in the first row in a state where the write drive pulse WS is inactive L. The first potential Vcc on the high / low potential side is switched to the second potential Vss on the low potential side (t11_1: see FIG. 6C). As shown in FIG. 6, this timing (t11_1) is within a period in which the video signal Vsig is in the signal potential (Vofs + Vin) of the effective period. However, it is not always necessary to make transition at t11_1 at this timing.

  Next, the write scanning unit 104 switches the write drive pulse WS to active H while the power supply line 105DSL_1 is at the second potential Vss (t13W0). This timing (t13W0) is a timing (t13V0) at which the video signal Vsig in the immediately preceding horizontal period is switched from the offset potential Vofs, which is the ineffective period, to the signal potential (Vofs + Vin) in the effective period and then switched to the offset potential Vofs. Use the same timing or a little later than that. Thereafter, the timing (t15W0) at which the write drive pulse WS is switched to inactive L is the same timing as or slightly before the timing (t15V0) at which the offset potential Vofs is switched to the signal potential (Vofs + Vin).

  That is, preferably, the period (t13W to t15W) in which the write drive pulse WS is active H is within the time period (t13V to t15V) in which the video signal Vsig is at the offset potential Vofs which is the ineffective period. This is because when the power supply line 105DSL is at the first potential Vcc and the video signal Vsig is at the signal potential (Vofs + Vin), if the write drive pulse WS is set to active H, the information holding capacity of the signal amplitude Vin. This is because a sampling operation (signal potential writing operation) to 120 is performed, which causes inconvenience as a threshold correction operation.

  At timings t11_1 to t13W0 (referred to as a discharge period C), the potential of the power supply line 105DSL is discharged to the second potential Vss, and the source potential Vs of the driving transistor 121 further changes to a potential close to the second potential Vss. Further, a storage capacitor 120 is connected between the gate terminal G and the source terminal S of the drive transistor 121, and the gate potential Vg is linked to the variation of the source potential Vs of the drive transistor 121 due to the effect of the storage capacitor 120. To do.

  When the write drive pulse WS is switched to active H while the power supply drive pulse DSL is kept at the second potential Vss on the low potential side (t13W0), the sampling transistor 125 becomes conductive as shown in FIG. 6D.

  At this time, the video signal line 106HS is at the offset potential Vofs. Therefore, the gate potential Vg of the drive transistor 121 becomes the offset potential Vofs of the video signal line 106HS through the conducting sampling transistor 125. At the same time, when the drive transistor 121 is turned on, the source potential Vs of the drive transistor 121 is fixed to the second potential Vss on the low potential side.

  That is, since the potential of the power supply line 105DSL is from the first potential Vcc on the high potential side to the second potential Vss that is sufficiently lower than the offset potential Vofs of the video signal line 106HS, the source potential Vs of the drive transistor 121 is changed to the video signal line 106HS. Is initialized (reset) to a second potential Vss sufficiently lower than the offset potential Vofs. In this way, by initializing the gate potential Vg and the source potential Vs of the drive transistor 121, the preparation for the threshold correction operation is completed. Next, a period (t13W0 to t14_1) until the power supply driving pulse DSL is set to the first potential Vcc on the high potential side is an initialization period D. Note that the discharge period C and the initialization period D are also collectively referred to as a threshold correction preparation period in which the gate potential Vg and the source potential Vs of the drive transistor 121 are initialized.

  When the wiring capacity of the power supply line 105DSL is large, the power supply line 105DSL may be switched from the high potential Vcc to the low potential Vss at a relatively early timing. By sufficiently securing the discharge period C and the initialization period D (t11_1 to t14_1), it is prevented from being affected by wiring capacitance and other pixel parasitic capacitances. For this reason, in this embodiment, the initialization process is performed twice. That is, while the power supply line 105DSL_1 remains at the second potential Vss, the write drive pulse WS is switched to inactive L (t15W0), and then the video signal Vsig is switched to the signal potential (Vofs + Vin) (t15V0). . Further, after the video signal Vsig is switched to the offset potential Vofs (t13V1), the write drive pulse WS is switched to active H (t13W1).

  In the discharge period C, when the second potential Vss is smaller than the sum of the threshold voltage VthEL and the cathode potential Vcath of the organic EL element 127, that is, "Vss <VthEL + Vcath", the organic EL element 127 is extinguished. Further, the source end and the drain end of the drive transistor 121 are practically reversed so that the power supply line 105DSL becomes the source side of the drive transistor 121, and the anode end A of the organic EL element 127 is charged to the second potential Vss (FIG. 6C). See).

  Further, in the initialization period D, the gate-source voltage Vgs of the drive transistor 121 takes a value of “Vofs−Vss” (see FIG. 6D). Since “Vofs−Vss” is not greater than the threshold voltage Vth of the drive transistor 121, the threshold value correction operation cannot be performed, so that “Vofs−Vss> Vth”.

  Next, the power drive pulse DSL applied to the power supply line 105DSL is switched to the first potential Vcc while the write drive pulse WS remains active H (t14_1). Thereafter, the drive scanning unit 105 keeps the potential of the power supply line 105DSL at the first potential Vcc until the processing of the next frame (or field).

  When the power supply line 105DSL is switched to the first potential Vcc (t14_1), the source end and the drain end of the drive transistor 121 are reversed again, and the power supply line 105DSL becomes the drain side of the drive transistor 121 (see FIG. 6E). As a result, the drive current Ids flows into the storage capacitor 120 and enters a first threshold correction period (referred to as a first threshold correction period E) in which the threshold voltage Vth of the drive transistor 121 is corrected (cancelled). This first threshold value correction period E continues until the timing (t15W1) when the write drive pulse WS is made inactive L.

  Here, the drive scanning unit 105 according to the present embodiment uses the timing (t14_1) for changing the potential of the power supply line 105DSL from the second potential Vss on the low potential side to the first potential Vcc on the high potential side. A time zone (t13V1 to t15V1) in which the signal line 106HS is at the offset potential Vofs which is an ineffective period of the video signal Vsig, more preferably a time zone in which the write drive pulse WS is active (t13W1 to t15W1).

  Incidentally, in the first threshold correction period E after the timing (t14_1), as shown in FIG. 6E, the potential of the power supply line 105DSL transits from the second potential Vss on the low potential side to the first potential Vcc on the high potential side. As a result, the source potential Vs of the drive transistor 121 starts to rise.

  That is, the gate terminal G of the drive transistor 121 is held at the offset potential Vofs of the video signal Vsig, and the drive current Ids flows until the potential Vs of the source terminal S of the drive transistor 121 rises and the drive transistor 121 is cut off. Try to. When cut off, the source potential Vs of the drive transistor 121 becomes “Vofs−Vth”.

  That is, since the equivalent circuit of the organic EL element 127 is represented by a parallel circuit of a diode and a parasitic capacitance Cel, as long as “Vel ≦ Vcath + VthEL”, that is, the leakage current of the organic EL element 127 is greater than the current flowing through the drive transistor 121. Is considerably small, the drive current Ids of the drive transistor 121 is used to charge the storage capacitor 120 and the parasitic capacitor Cel.

  As a result, when the drive current Ids flows through the drive transistor 121, the voltage Vel at the anode end A of the organic EL element 127, that is, the potential of the node ND121 increases with time as shown in FIG. Then, the threshold value correction period is terminated when the potential difference between the potential of the node ND121 (source potential Vs) and the voltage of the node ND122 (gate potential Vg) is exactly the threshold voltage Vth. That is, after a certain time has elapsed, the gate-source voltage Vgs of the drive transistor 121 takes a value called the threshold voltage Vth.

  Until the gate-source voltage Vgs reaches the threshold voltage Vth, the gate-source voltage Vgs of the drive transistor 121 is larger than the threshold voltage Vth, and therefore, the drive current Ids flows as shown in FIG. 6E. At this time, since the organic EL element 127 is reverse-biased, the organic EL element 127 does not emit light.

  Here, actually, a voltage corresponding to the threshold voltage Vth is written in the storage capacitor 120 connected between the gate terminal G and the source terminal S of the driving transistor 121. However, the first threshold correction period E is returned to inactive L from the timing (t13W1) when the write drive pulse WS is set to active H (specifically, the time t14 when the power supply drive pulse DSL is returned to the first potential Vcc). Until the timing (t15W1), if this period is not sufficiently secured, the process ends before that.

  Specifically, when the gate-source voltage Vgs becomes Vx1 (> Vth), that is, when the source potential Vs of the drive transistor 121 becomes “Vofs−Vx1” from the second potential Vss on the low potential side. It ends in. For this reason, Vx1 is written to the storage capacitor 120 at the time (t15W1) when the first threshold correction period E is completed.

  Next, in the second half of one horizontal period, the drive scanning unit 105 switches the write drive pulse WS to inactive L (t15W1), and the horizontal drive unit 106 further changes the video signal line 106HS from the offset potential Vofs to the signal potential. Switch to (Vofs + Vin) (t15V1). As a result, as shown in FIG. 6F, the video signal line 106HS changes to the signal potential (Vofs + Vin), while the potential of the write scanning line 104WS (write drive pulse WS) becomes low level.

  At this time, the sampling transistor 125 is in a non-conductive (off) state, and a drain current corresponding to Vx1 previously held in the holding capacitor 120 flows to the organic EL element 127, so that the source potential Vs slightly increases. . When this increase is Va1, the source potential Vs becomes “Vofs−Vx1 + Va1”. Further, a storage capacitor 120 is connected between the gate terminal G and the source terminal S of the drive transistor 121, and the gate potential Vg is linked to the variation of the source potential Vs of the drive transistor 121 due to the effect of the storage capacitor 120. As a result, the gate potential Vg becomes “Vofs + Va1”.

  After the first threshold correction period E, the horizontal drive unit 106 switches the video signal line 106HS from the signal potential (Vofs + Vin) to the offset potential Vofs (t13V2), and the drive scanning unit 105 switches the write drive pulse WS to active H. A period up to (t13W2) (referred to as another row writing period) F is a sampling period for information on the signal amplitude Vin for pixels in other rows, and the sampling transistor 125 in this processing target row needs to be turned off. This completes the first one horizontal period process.

  In the first half of the next one horizontal period (1H), the horizontal drive unit 106 switches the video signal line 106HS from the signal potential (Vofs + Vin) to the offset potential Vofs (t13V2), and the drive scanning unit 105 outputs the write drive pulse WS. Switch to active H (t13W2). As a result, the drain current flows into the storage capacitor 120 and enters a second threshold correction period (referred to as a second threshold correction period G) in which the threshold voltage Vth of the drive transistor 121 is corrected (cancelled). This second threshold value correction period G continues until the timing (t15W2) when the write drive pulse WS is made inactive L.

  In the second threshold correction period G, the same operation as the first threshold correction period E is performed. Specifically, as shown in FIG. 6G, the gate terminal G of the driving transistor 121 is held at the offset potential Vofs of the video signal Vsig, and the gate potential is offset from the previous “Vg = offset potential Vofs + Va1”. Switch to Vofs. Information on the potential fluctuation amount Va1 at the gate end G of the drive transistor at this time is input to the source end S of the drive transistor via the storage capacitor 120 and the parasitic capacitance Cgs between the gate and source of the drive transistor. The amount of input to the source terminal S at this time is expressed as gVa1, and the source potential Vs is decreased by gVa1 from the previous “Vofs−Vx1 + Va1”, and thus becomes “Vofs−Vx1 + (1−g) Va1”.

  Here, if the gate-source voltage Vx1- (1-g) Va1 of the driving transistor 121 is larger than the threshold voltage Vth of the driving transistor 121, then the potential Vs of the source terminal S of the driving transistor 121 increases. Thus, the drain current tends to flow until the drive transistor 121 is cut off. When cut off, the source potential Vs of the drive transistor 121 becomes “Vofs−Vth”.

  However, the second threshold correction period G is from the timing (t13W2) when the write drive pulse WS is set to active H to the timing (t15W2) when the write drive pulse WS is returned to inactive L. When this period is not sufficiently secured, It will end before. This is the same as the first threshold value correction period E, and when the gate-source voltage Vgs becomes Vx2 (<Vx1, and> Vth), that is, the source potential Vs of the drive transistor 121 is “Vofs−Vx1”. When “Vofs−Vx2” is reached from “”, the process ends. Therefore, Vx2 is written to the storage capacitor 120 at the time (t15W2) when the second threshold correction period G is completed.

  Next, in the second half of one horizontal period, the drive scanning unit 105 switches the write drive pulse WS to inactive L (t15W2) in order to perform sampling of the signal potentials for the pixels in the other row, and further, the horizontal drive unit. 106 switches the video signal line 106HS from the offset potential Vofs to the signal potential (Vofs + Vin) (t15V2). As a result, as shown in FIG. 6H, the video signal line 106HS changes to the signal potential (Vofs + Vin), while the potential of the write scanning line 104WS (write drive pulse WS) becomes low level.

  At this time, the sampling transistor 125 is in a non-conduction (off) state, and a drain current corresponding to Vx2 previously held in the holding capacitor 120 flows to the organic EL element 127, so that the source potential Vs slightly increases. . When this increase is Va2, the source potential Vs becomes “Vofs−Vx2 + Va2”. Further, a storage capacitor 120 is connected between the gate terminal G and the source terminal S of the drive transistor 121, and the gate potential Vg is linked to the variation of the source potential Vs of the drive transistor 121 due to the effect of the storage capacitor 120. As a result, the gate potential Vg becomes “Vofs + Va2”.

  After the second threshold correction period G, the horizontal drive unit 106 switches the video signal line 106HS from the signal potential (Vofs + Vin) to the offset potential Vofs (t13V3), and the drive scanning unit 105 switches the write drive pulse WS to active H. A period (referred to as another row writing period) H up to (t13W3) is a sampling period of signal amplitude Vin information for pixels in other rows, and the sampling transistor 125 in this processing target row needs to be turned off. This completes the second process of one horizontal period.

  Further, in the first half of the next one horizontal cycle (1H), the horizontal drive unit 106 switches the video signal line 106HS from the signal potential (Vofs + Vin) to the offset potential Vofs (t13V3), and the drive scanning unit 105 writes the write drive pulse. WS is switched to active H (t13W3). As a result, the drain current flows into the storage capacitor 120 and enters a third threshold correction period (referred to as a third threshold correction period I) in which the threshold voltage Vth of the drive transistor 121 is corrected (cancelled). This third threshold value correction period I continues until the timing (t15W3) when the write drive pulse WS is made inactive L.

  In the third threshold correction period I, an operation similar to that of the first threshold correction period E and the second threshold correction period G is performed. Specifically, as shown in FIG. 6I, the gate terminal G of the driving transistor 121 is held at the offset potential Vofs of the video signal Vsig, and the gate potential is offset from the previous “Vg = offset potential Vofs + Va2”. Switch to Vofs. Information on the potential fluctuation amount Va2 at the gate end G of the drive transistor at this time is input to the source end S of the drive transistor via the storage capacitor 120 and the parasitic capacitance Cgs between the gate and source of the drive transistor. The amount of input to the source terminal S at this time is expressed as gVa2, and the source potential Vs is decreased by gVa2 from the previous “Vofs−Vx2 + Va2”, and thus becomes “Vofs−Vx1 + (1−g) Va2”.

  Thereafter, the drain current tends to flow until the potential Vs of the source terminal S of the driving transistor 121 rises and the driving transistor 121 is cut off. The drain current is cut off when the gate-source voltage Vgs is just equal to the threshold voltage Vth. When cut off, the source potential Vs of the drive transistor 121 becomes “Vofs−Vth”.

  That is, the gate-source voltage Vgs of the drive transistor 121 takes the value of the threshold voltage Vth by the processing in the threshold correction period that is performed a plurality of times (three times in this example). Here, actually, a voltage corresponding to the threshold voltage Vth is written in the storage capacitor 120 connected between the gate terminal G and the source terminal S of the driving transistor 121.

  Note that in the threshold correction periods E, G, and I for three times, all of the drain current does not flow to the holding capacitor 120 side or the parasitic capacitance Cel side of the organic EL element 127 but to the cathode potential Vcath side. Therefore, the potential Vcath of the common ground wiring cath is set so that the organic EL element 127 is cut off.

  Thereafter, the signal potential (Vofs + Vin) is actually supplied to the signal line 106HS by the horizontal driving unit 106, and writing of the information of the signal amplitude Vin to the storage capacitor 120 is performed during a period in which the write driving pulse WS is set to active H. A period (also referred to as a sampling period). Information on the signal amplitude Vin is held in a form that is added to the threshold voltage Vth of the drive transistor 121. Specifically, when the write gain Ginput is considered, the above-described ratio g is involved.

  As a result, fluctuations in the threshold voltage Vth of the drive transistor 121 are always canceled, and threshold correction is performed. By this threshold correction, the gate-source voltage Vgs held in the holding capacitor 120 becomes “Vin + Vth”. When the write gain Ginput is considered, (1−g) Vin + Vth = Ginput · Vin + Vth. At the same time, mobility correction is executed during this sampling period. That is, at the drive timing of the present embodiment, the sampling period also serves as the mobility correction period. The signal amplitude Vin is a voltage corresponding to the gradation.

  Specifically, first, the write drive pulse WS is switched to inactive L (t15W3), and the horizontal drive unit 106 further switches the video signal line 106HS from the offset potential Vofs to the signal potential (Vofs + Vin) (t15V3). Thus, the last (third time in this example) threshold correction period is completed. As a result, as shown in FIG. 6J, the sampling transistor 125 is turned off (off), and the preparation for the next sampling operation and mobility correction operation is completed. Next, a period until the timing (t16_1) when the write drive pulse WS is set to active H is referred to as a write & mobility correction preparation period J.

  Next, with the video signal line 106HS held at the signal potential (Vofs + Vin), the write scanning unit 104 switches the write drive pulse WS to active H (t16_1), and the horizontal drive unit 106 moves to the video signal line 106HS. At an appropriate timing from the signal potential (Vofs + Vin) to the timing (t18_1) for switching from the signal potential (Vofs + Vin) to the offset potential Vofs, that is, at an appropriate time zone in which the video signal line 106HS is at the signal potential (Vofs + Vin). Switch to inactive L (t17_1). A period (t16_1 to t17_1) in which the write drive pulse WS is active H is referred to as a sampling period & mobility correction period K.

  As a result, as shown in FIG. 6K, the sampling transistor 125 becomes conductive (ON), and the gate potential Vg of the drive transistor 121 becomes the signal potential (Vofs + Vin). Therefore, in the sampling period & mobility correction period K, the drive current Ids flows through the drive transistor 121 while the gate terminal G of the drive transistor 121 is fixed to the signal potential (Vofs + Vin).

  The gate potential Vg of the drive transistor 121 becomes the signal potential (Vofs + Vin) because the sampling transistor 125 is turned on, but the current flows from the power supply line 105DSL, so that the source potential Vs increases with time.

  As will be described later, when the threshold voltage of the organic EL element 127 is VthEL, when considering the write gain, the organic EL element 127 is set in a reverse bias state by setting “Vofs−Vth + gVin + ΔV <VthEL + Vcath”. In addition, since it is in a cut-off state (high impedance state), it does not emit light, and it exhibits simple capacitance characteristics instead of diode characteristics. If the source potential Vs at this time does not exceed the sum of the threshold voltage VthEL and the cathode potential Vcath of the organic EL element 127, the drain current (drive current Ids) flowing through the drive transistor 121 is equal to the capacitance value Cs of the storage capacitor 120 and the organic EL element. The capacitance value Cel of the 127 parasitic capacitance (equivalent capacitance) Cel is combined and written into the capacitance “C = Cs + Cel”. As a result, the source potential Vs of the drive transistor 121 increases. At this time, since the threshold value correcting operation of the driving transistor 121 is completed, the driving current Ids flowing through the driving transistor 121 reflects the mobility μ.

  In the timing chart of FIG. 6, this increase is represented by ΔV. When the write gain is taken into account, this increase, that is, the negative feedback amount ΔV, which is the mobility correction parameter, is the gate-source voltage “Vgs = (1−g) Vin + Vth” held in the holding capacitor 120 by the threshold correction. Since “Vgs = (1−g) Vin + Vth−ΔV”, negative feedback is applied. At this time, the source potential Vs of the driving transistor 121 is obtained by subtracting the voltage “Vgs = (1−g) Vin + Vth−ΔV” held in the storage capacitor from the gate potential Vg (= Vofs + Vin) “(1−g)”. Vofs + g (Vofs + Vin) −Vth + ΔV ”=“ Vofs + gVin−Vth + ΔV ”.

  In this way, at the drive timing of this embodiment, in the sampling period & mobility correction period K (t16 to t17), the negative feedback amount (for sampling the information of the signal amplitude Vin and the mobility μ in the video signal Vsig) The mobility correction parameter) ΔV is adjusted. The negative feedback amount ΔV is ΔV = Ids · (Cel + Cgs + Cs) / t.

  The writing scanning unit 104 can adjust the time width of the sampling period & mobility correction period K, and thereby can optimize the negative feedback amount of the drive current Ids for the storage capacitor 120. Here, “optimizing the negative feedback amount” means that the mobility correction can be appropriately performed at any level in the range from the black level to the white level of the video signal potential.

  Since the negative feedback amount ΔV is ΔV = Ids · (Cel + Cgs + Cs) / t, the negative feedback amount ΔV applied to the gate-source voltage Vgs depends on the drain current Ids extraction time, that is, the sampling period & mobility correction period K. The longer this period, the greater the negative feedback amount. At that time, the mobility correction period t is not necessarily constant, and conversely, it may be preferable to adjust the mobility correction period t according to the drive current Ids. For example, when the drive current Ids is large, the mobility correction period t is preferably set short, and conversely, when the drive current Ids is small, the mobility correction period t is preferably set long.

  Further, since the negative feedback amount ΔV is ΔV = Ids · (Cel + Cgs + Cs) / t, the negative feedback amount ΔV increases as the drive current Ids which is the drain-source current of the drive transistor 121 increases. Conversely, when the drive current Ids of the drive transistor 121 is small, the negative feedback amount ΔV is small. Thus, the negative feedback amount ΔV is determined according to the drive current Ids.

  Further, as the signal amplitude Vin increases, the drive current Ids increases and the absolute value of the negative feedback amount ΔV also increases. Therefore, mobility correction according to the light emission luminance level can be realized. At this time, the sampling period & mobility correction period K is not necessarily constant, and conversely, it may be preferable to adjust according to the drive current Ids. For example, when the drive current Ids is large, the mobility correction period t should be shortened. Conversely, when the drive current Ids is small, the sampling period & mobility correction period K should be set longer.

  For example, the mobility correction period is automatically set to the video line signal potential by tilting the rising characteristic of the video signal line potential (the potential of the signal line 106HS) or the transition characteristic of the write drive pulse WS of the write scanning line 104WS. Follow and optimize it. When the potential of the signal line 106HS is high (when the driving current Ids is large), the correction period is shortened, and when the potential of the signal line 106HS is low (when the driving current Ids is small), the correction period is automatically adjusted. To do. In this way, an appropriate correction period can be automatically set following the video signal potential (video signal Vsig), so that the optimum mobility correction can be performed regardless of the brightness and the pattern of the image.

  Further, the negative feedback amount ΔV is Ids · (Cel + Cgs + Cs) / t, and even when the drive current Ids varies due to the variation in mobility μ for each pixel circuit P, the negative feedback amount ΔV corresponds to each. Therefore, variation in mobility μ for each pixel circuit P can be corrected. That is, when the signal amplitude Vin is constant, as shown in FIG. 7A, as the mobility μ of the drive transistor 121 increases, the drive current Ids increases, the source potential Vs increases rapidly, and the absolute value of the negative feedback amount ΔV increases. growing. On the contrary, when the mobility μ is small, the drive current Ids is small, the rise of the source potential Vs is slow, and the absolute value of the negative feedback amount ΔV is small. In other words, since the negative feedback amount ΔV increases as the mobility μ increases, the gate-source voltage Vgs of the drive transistor 121 decreases to reflect the mobility μ, and the mobility μ is completely corrected after a certain period of time. Therefore, the variation in mobility μ for each pixel circuit P can be removed.

  In this way, at the drive timing of the present embodiment, the sampling of the information of the signal amplitude Vin and the adjustment of the negative feedback amount ΔV for correcting the variation of the mobility μ are simultaneously performed in the sampling period & mobility correction period K. Done. Of course, the negative feedback amount ΔV can be optimized by adjusting the time width of the sampling period & mobility correction period K.

  Next, the write scanning unit 104 switches the write drive pulse WS to inactive L while the video signal line 106HS is at the signal potential (Vofs + Vin) (t17_1). As a result, as shown in FIG. 6L, the sampling transistor 125 enters a non-conductive (off) state and proceeds to the light emission period L. The horizontal driving unit 106 stops supplying the signal potential (Vofs + Vin) to the video signal line 106HS at an appropriate time thereafter, and returns it to the offset potential Vofs (t18_1). Thereafter, the process proceeds to the next frame (or field), and the threshold correction preparation operation, the threshold correction operation, the mobility correction operation, and the light emission operation are repeated again.

  As a result, the gate terminal G of the drive transistor 121 is disconnected from the video signal line 106HS. Since the application of the signal potential (Vofs + Vin) to the gate terminal G of the drive transistor 121 is released, the gate potential Vg of the drive transistor 121 can be increased.

  At this time, the drive current Ids flowing through the drive transistor 121 flows through the organic EL element 127, and the anode potential of the organic EL element 127 rises according to the drive current Ids. Let this increase be Vel. Eventually, as the source potential Vs rises, the reverse bias state of the organic EL element 127 is canceled, so that the organic EL element 127 actually starts to emit light by the inflow of the drive current Ids. The rise (Vel) of the anode potential of the organic EL element 127 at this time is nothing but the rise of the source potential Vs of the drive transistor 121, and the source potential Vs of the drive transistor 121 is “(1-g) Vofs + g (Vofs). + Vin) −Vth + ΔV + Vel ”=“ Vofs + gVin−Vth + ΔV + Vel ”.

  The relationship between the drive current Ids and the gate voltage Vgs can be expressed as in Expression (2-1) by substituting “Vin−ΔV + Vth” into Vgs in Expression (1) representing the previous transistor characteristics. When the write gain is taken into consideration, it can be expressed as equation (2-2) by substituting “(1−g) Vin−ΔV + Vth” into Vgs of equation (1). In Expression (2-1) and Expression (2-2) (collectively referred to as Expression (2)), k = (1/2) (W / L) Cox.

  From this equation (2), it can be seen that the term of the threshold voltage Vth is canceled and the drive current Ids supplied to the organic EL element 127 does not depend on the threshold voltage Vth of the drive transistor 121. Basically, the drive current Ids is determined by the signal amplitude Vin. In other words, the organic EL element 127 emits light with a luminance corresponding to the signal amplitude Vin.

  At this time, the information held in the holding capacitor 120 is corrected by the feedback amount ΔV. This correction amount ΔV works so as to cancel the effect of the mobility μ located in the coefficient part of the equation (2). Therefore, the drive current Ids substantially depends only on the signal amplitude Vin. Since the drive current Ids does not depend on the threshold voltage Vth, even if the threshold voltage Vth varies depending on the manufacturing process, the drain-source drive current Ids does not vary, and the light emission luminance of the organic EL element 127 does not vary.

  In addition, a storage capacitor 120 is connected between the gate terminal G and the source terminal S of the drive transistor 121. Due to the effect of the storage capacitor 120, a bootstrap operation is performed at the beginning of the light emission period. The gate potential Vg and the source potential Vs of the drive transistor 121 rise while the gate-source voltage Vgs of the drive transistor 121 is kept constant. When the source potential Vs of the driving transistor 121 becomes “Vofs + gVin−Vth + ΔV + Vel”, the gate potential Vg becomes “Vofs + Vin + Vel”.

  At this time, since the gate-source voltage Vgs of the drive transistor 121 is constant, the drive transistor 121 passes a constant current (drive current Ids) to the organic EL element 127. As a result, the potential at the anode end A of the organic EL element 127 (= potential at the node ND121) rises to a voltage at which a current called a drive current Ids in a saturated state can flow through the organic EL element 127.

  Here, the organic EL element 127 has its IV characteristic changed as the light emission time becomes longer. Therefore, the potential of the node ND121 also changes with time. However, even if the anode potential fluctuates due to such deterioration of the organic EL element 127 with time, the gate-source voltage Vgs held in the holding capacitor 120 is always kept constant.

  Since the drive transistor 121 operates as a constant current source, the IV characteristic of the organic EL element 127 changes with time, and even if the source potential Vs of the drive transistor 121 changes accordingly, the drive transistor 121 drives the drive transistor 121. Since the gate-source potential Vgs 121 is kept constant (≈Vin−ΔV + Vth or ≈ (1−g) Vin−ΔV + Vth), the current flowing through the organic EL element 127 does not change. The light emission brightness is also kept constant.

  Regardless of the characteristic variation of the organic EL element 127, an operation for correction (operation based on the effect of the storage capacitor 120) for maintaining the gate-source voltage of the driving transistor 121 constant and maintaining the luminance constant is performed. This is called a bootstrap operation. By this bootstrap operation, even if the IV characteristic of the organic EL element 127 changes with time, it is possible to display an image without luminance deterioration associated therewith.

  That is, in the pixel circuit P of the present embodiment and the drive timing of the present embodiment for driving the pixel circuit P, the change in the current-voltage characteristic of the organic EL element 127 which is an example of the electro-optic element is corrected to keep the drive current constant. A bootstrap circuit, which is an example of a drive signal stabilizing circuit, is configured so that the bootstrap operation functions. Therefore, even if the IV characteristic of the organic EL element 127 deteriorates, the constant current Ids always flows, so that the organic EL element 127 continues to emit light with the luminance according to the pixel signal Vsig, and the luminance changes. Absent.

  The pixel circuit P of the present embodiment and the drive timing of the present embodiment for driving the pixel circuit P are threshold values that are an example of a drive signal stabilization circuit that corrects the threshold voltage Vth of the drive transistor 121 and maintains the drive current constant. A correction circuit is configured so that the threshold correction operation functions. As the gate-source potential Vgs reflecting the threshold voltage Vth of the drive transistor 121, a constant current Ids that is not affected by variations in the threshold voltage Vth can be passed.

  In particular, at the drive timing of the present embodiment, one threshold correction operation processing cycle is set as one horizontal period, and the threshold correction operation is repeated a plurality of times, so that the threshold voltage Vth is reliably applied to the storage capacitor 120. I try to keep it. For this reason, the inter-pixel difference of the threshold voltage Vth is reliably removed, and the luminance unevenness caused by the variation of the threshold voltage Vth can be suppressed regardless of the gradation.

  On the other hand, when the threshold voltage Vth is not sufficiently corrected, for example, when the threshold correction operation is performed once, that is, when the threshold voltage Vth is not held in the holding capacitor 120, the pixel circuits P are different. In the low gradation region, there is a difference in luminance (driving current Ids). Therefore, when the correction of the threshold voltage is insufficient, luminance unevenness appears at a low gradation and the image quality is impaired.

  In addition, at the drive timing of the present embodiment, the mobility μ of the drive transistor 121 is corrected in conjunction with the operation of writing the information of the signal amplitude Vin to the storage capacitor 120 by the sampling transistor 125 to keep the drive current constant. A mobility correction circuit, which is an example of a drive signal stabilization circuit, is configured so that the mobility correction operation functions. As the gate-source potential Vgs reflecting the carrier mobility μ of the driving transistor 121, a constant current Ids that is not affected by variations in the carrier mobility μ can be passed.

  That is, the pixel circuit P of the present embodiment automatically configures the threshold correction circuit and the mobility correction circuit by devising the drive timing, and the characteristic variation of the drive transistor 121 (in this example, the threshold voltage Vth and the carrier movement). In order to prevent the influence on the drive current Ids due to the variation in the degree μ), the influence of the threshold voltage Vth and the carrier mobility μ is corrected to function as a drive signal stabilization circuit that maintains the drive current constant. It is.

  Since not only the bootstrap operation but also the threshold correction operation and the mobility correction operation are performed, the gate-source voltage Vgs maintained in the bootstrap operation is a voltage corresponding to the threshold voltage Vth and for mobility correction. Therefore, the light emission luminance of the organic EL element 127 is not affected by variations in the threshold voltage Vth and mobility μ of the driving transistor 121, and is also affected by deterioration with time of the organic EL element 127. I do not receive it. A stable gradation corresponding to the input signal amplitude Vin can be displayed, and a high-quality image can be obtained.

  In addition, since the pixel circuit P of the present embodiment can be configured by a source follower circuit using an n-channel type drive transistor 121, an organic EL element of the current anode / cathode electrode can be used as it is. The EL element 127 can be driven.

  In addition, the pixel circuit P can be configured using only n-channel transistors including the driving transistor 121 and the sampling transistor 125 in the periphery thereof, and an amorphous silicon (a-Si) process is also used in TFT fabrication. Therefore, the cost of the TFT substrate can be reduced.

<< About vertical wiring and horizontal wiring >>
8 and 8A are diagrams for explaining a comparative example of the wiring form (layout) of the vertical wiring and the horizontal wiring of the pixel array unit 102. FIG. FIG. 8 shows a layout of scanning wiring for one pixel, and FIG. 8A shows a layout of scanning wiring of pixel circuits P for two rows adjacent in the vertical direction.

  In the case of the pixel circuit P shown in FIG. 5, in the pixel array unit 102, at least the writing scanning line 104WS and the power supply line 105DSL related to the vertical scanning system become one of the vertical / horizontal wirings (for example, horizontal wiring). On the other hand, the video signal line 106HS related to the horizontal scanning system is the other vertical / horizontal wiring (for example, vertical wiring). If the cathode potential Vcath of the organic EL element 127 is a normal wiring instead of a solid wiring, the wiring for the cathode potential Vcath (hereinafter referred to as the cathode wiring Wcath) is a horizontal wiring or a vertical wiring.

  Here, each of the above-mentioned wirings (the write scanning line 104WS, the power supply line 105DSL, and the video signal line 106HS) extends in the horizontal direction or the vertical direction, and the corresponding scanning unit (write) provided around the pixel array unit 102. , The scanning unit 104, the driving scanning unit 105, and the horizontal driving unit 106).

  When the horizontal direction of the screen is considered, a detailed explanatory diagram is omitted, but the write drive pulse WS is commonly supplied from the write scanning unit 104 to all the pixel circuits P in one row. The pixel circuit P (referred to as a far-side pixel) farther from the writing scanning unit 104 is closer to the writing scanning unit 104 (referred to as a near-side pixel) because the waveform of the pulse WS is affected by the wiring capacitance or wiring resistance. ), The waveform becomes dull. For this reason, the distribution characteristics of the wiring capacitance and the wiring resistance may affect the operations of threshold correction and mobility correction.

  The same applies to the power supply line 105DSL and the video signal line 106HS (or the cathode wiring Wcath), and the distribution characteristics of the wiring capacity and wiring resistance affect the threshold correction and mobility correction operations. There is.

  In consideration of these points, each wiring is generally wired using a metal wiring that does not have optical transparency such as aluminum Al or molybdenum Mo in order to reduce resistance. As described above, since vertical wiring and horizontal wiring are necessary, basically, at least two layers of metal wiring are required for the overlap at the intersection of the vertical wiring and the horizontal wiring.

  For example, in the first comparative example shown in FIG. 8A, the write scanning line 104WS for driving the gate terminal of the sampling transistor 125 and the power supply voltage at the drain terminal of the driving transistor 121 are set to the first potential Vcc and the second potential. The power supply line 105DSL for switching with the potential Vss is a metal wiring on one of the upper layer side and the lower layer side (here, the upper layer side).

  The video signal line 106HS for supplying the video signal Vsig to the source end of the sampling transistor 125 is a metal wiring on one of the upper layer side and the lower layer side (here, the upper layer side) in the pixel circuit P portion. On the other hand, since the portion intersecting the write scanning line 104WS and the power supply line 105DSL in the same layer (which is the metal wiring on the upper layer side) needs to overlap, the other of the upper layer side and the lower layer side (here, It is a metal wiring of the lower layer side).

  In the second comparative example shown in FIG. 8B, the power supply voltage at the write scanning line 104WS for driving the gate terminal of the sampling transistor 125 and the drain terminal of the driving transistor 121 is set to the first potential Vcc and the second voltage. The power supply line 105DSL for switching with the potential Vss is a metal wiring on one of the upper layer side and the lower layer side (here, the lower layer side).

  Further, the video signal line 106HS for supplying the video signal Vsig to the source end of the sampling transistor 125 is entirely made of metal wiring on the other of the upper layer side and the lower layer side (here, the upper layer side). By doing so, a bridge (connecting metal wirings of different layers) with the metal wiring on the lower layer side as in the first comparative example shown in FIG. 8A is avoided.

  In both the first comparative example shown in FIG. 8A and the second comparative example shown in FIG. 8B, the write scanning line 104WS and the power supply line 105DSL are laid out with the same layer of metal wiring, Even if they are separated within one pixel (at the upper and lower ends of the pixel circuit P), as shown in FIG. 8A, in the relationship with the adjacent pixel circuit P, they are very close in the same layer (same layer). Will run parallel (adjacent). Further, as described above, the write scanning line 104WS and the power supply line 105DSL are very long because they are laid out up to the corresponding writing scanning unit 104 and driving scanning unit 105 around the pixel array unit 102 (panel end). . Therefore, if the space between the wirings is narrow, there is a high possibility that the wirings in the same layer are connected (short-circuited) by foreign matters such as conductive dust, resulting in a decrease in yield.

  Therefore, the present embodiment employs a mechanism that can reduce the possibility that metal wirings running in parallel in the same layer are connected (shorted) by dust or the like. This will be specifically described below.

<Vertical Wiring and Horizontal Wiring Improvement Method: First Example>
FIG. 9 is a diagram for explaining a first example of the wiring form (layout) of the vertical wiring and horizontal wiring of the pixel array unit 102 employed in the present embodiment. FIG. 9A shows the layout of the scanning wiring for one pixel, and FIG. 9B shows the layout of the scanning wiring of the pixel circuits P for two rows adjacent in the vertical direction.

  In the layout of the first example, when the parallel wiring in each pixel (each scanning line parallel in the same direction) is an even number, in the pixel circuit P, the entire parallel wiring is composed of the upper layer wiring and the lower layer wiring. By alternately laying out, adjacent wiring is laid out with metal wirings of different layers. The portion intersecting the vertical wiring is overlapped by connecting the vertical wiring, which is the cross wiring with respect to the horizontal wiring, by the upper layer wiring and the lower layer wiring. Needless to say, the overlap portion is laminated with an insulating layer interposed therebetween so that the upper layer wiring and the lower layer wiring are not in electrical contact (the same applies hereinafter). By doing so, the entire adjacent wiring can be laid out with metal wirings of different layers both inside and outside the pixel circuit P, and the number of shorts between wirings due to dust or the like can be reduced.

  Specifically, in the layout of the first example, the case where there are two horizontal wirings in one pixel is shown. A power supply line 105DSL for switching the power supply voltage at the drain end of the drive transistor 121 between the first potential Vcc and the second potential Vss, and a video signal line 106HS for supplying the video signal Vsig to the source end of the sampling transistor 125. The inner side of the pixel circuit P (meaning the central portion in the vertical direction within the pixel pitch in which the pixel circuit P is arranged; the same applies hereinafter) is one of the upper layer side and the lower layer side (herein referred to as the upper layer side). Wiring. Further, the write scanning line 104WS for driving the gate end of the sampling transistor 125 is the other metal wiring on the upper layer side and the lower layer side (here, the lower layer side).

  Since the video signal line 106HS needs to overlap with the power supply line 105DSL in the same layer (which is a metal wiring on the upper layer side), it is made a metal wiring on the lower layer side. In addition, the metal wiring on the upper layer side of the video signal line 106HS extends to the boundary of the pixel circuit P in the next row adjacent thereto, and intersects with the power supply line 105DSL in the same layer (which is the metal wiring on the upper layer side) in the next row. It is made to overlap in the part to do.

  As shown in FIG. 9A, the write scanning line 104WS and the power supply line 105DSL are separated from each other (at the upper and lower ends of the pixel circuit P) within one pixel. At this time, as shown in FIG. 9B, in the relationship with the adjacent pixel circuit P, the layers run in close proximity (adjacent) in different layers.

  In this way, if the horizontal metal wirings that run in close proximity (adjacent) are laid out in different wiring layers, the upper layer and the lower layer can be used even if there is foreign matter such as conductive dust on the upper layer side. Are not connected (short-circuited), so it is possible to realize a countermeasure against a short-circuit between adjacent wirings and realize a high yield. A layout in which the same-layer short circuit between adjacent wirings due to dust or the like is unlikely to occur can be achieved, and a high yield can be realized.

  By laying out adjacent wirings with metal wirings of different layers within the pixel circuit P and between two adjacent pixel circuits P, the number of shorts between wirings due to conductive foreign substances can be reduced, and high yield can be achieved. It can be realized.

  Further, in contrast with the first comparative example shown in FIG. 8A, the video signal line 106HS which is a vertical wiring and the metal wiring on the lower layer side of the horizontal wiring (connecting metal wirings of different layers). Since the distance between them can be reduced, the load on the video signal line 106HS can be reduced.

<Method for improving vertical and horizontal wiring: second example>
FIG. 9A is a diagram illustrating a second example of the wiring form (layout) of the vertical wiring and horizontal wiring of the pixel array unit 102 employed in the present embodiment, and the pixel circuits P for two rows adjacent in the vertical direction. The layout of the scanning wiring is shown.

  The layout of the second example employs the layout method of the first example, and one wiring on the upper layer side and lower layer side of the lowermost end of a row and the other wiring on the upper layer side and lower layer side of the uppermost end of the next row Is characterized in that the pixel pitch in the vertical direction is reduced. Needless to say, the laminated portion is laminated with an insulating layer interposed therebetween so that the upper-layer wiring and the lower-layer wiring are not electrically contacted as in the overlap portion.

  In the illustrated example, the pixel pitch in the vertical direction is obtained by laminating the write scanning line 104WS on the lower layer side of a row and the power supply line 105DSL on the upper layer side of the next row on the basis of the layout shown in FIG. Narrowing down.

  Here, for the portion where the write scan line 104WS and the video signal line 106HS intersect, the write scan line 104WS is used so as to avoid the lower layer metal wiring that intersects the power supply line 105DSL and the video signal line 106HS. The metal wiring on the lower layer side is detoured to the pixel circuit P side of the own column and overlapped with the video signal line 106HS.

  In the layout of the first example, the pixel width of each row matches the pixel pitch, whereas in the layout of the second example, the pixel width of each row (the Nth row and the N + 1th row in the figure) matches the pixel pit. First, the vertical pixel pitch is reduced by ½ of the pixel stack by laminating the write scan line 104WS on the lower layer side of the Nth row and the power supply line 105DSL on the upper layer side of the (N + 1) th row. be able to.

  Even in the layout of the second example in which the pixel pitch in the vertical direction is narrowed as described above, the horizontal metal wirings that run in parallel (adjacent) are arranged in different wiring layers. Therefore, with respect to the metal wirings in the horizontal direction, even if there is a conductive foreign substance on the upper layer side, the upper layer and the lower layer are not connected (short-circuited), so that a high yield can be realized. That is, since the adjacent wiring is a metal wiring of a different layer except for the portion where the video signal line 106HS which is the vertical wiring and the writing scanning line 104WS which is the horizontal wiring overlap, there is an effect of a countermeasure against short-circuiting between the adjacent wirings. .

  In addition, as in the first example, in comparison with the first comparative example shown in FIG. 8A, the inter-bridge distance between the video signal line 106HS which is a vertical wiring and the metal wiring on the lower layer side of the horizontal wiring. Thus, the load on the video signal line 106HS can be reduced.

<Vertical Wiring and Horizontal Wiring Improvement Method: Third Example>
FIG. 9B is a diagram illustrating a third example of the wiring form (layout) of the vertical wiring and horizontal wiring of the pixel array unit 102 employed in the present embodiment. FIG. 9B (A) shows the layout of the scanning wiring for one pixel, and FIG. 9B (B) shows the layout of the scanning wiring of the pixel circuits P for two rows adjacent in the vertical direction.

  In the layout of the third example, when the parallel wiring in each pixel (each scanning line parallel in the same direction) is an odd number, one of the scanning lines is within the pixel pitch where the pixel circuit P is disposed. One of the uppermost wiring and the lower wiring is formed at one end of the other, and the other scanning line is arranged on the other (opposite side to the other) within the pixel pitch where the pixel circuit P is arranged. It is characterized in that it is formed at the other end of the upper layer wiring and the lower layer wiring at the extreme end. For the remaining even number, the upper layer wiring and the lower layer wiring are preferably laid out alternately by applying the layout of the first example. Still, the last one remaining is laid out on either the upper layer side or the lower layer side.

  In other words, on the inside of the pixel circuit P, either the upper layer wiring or the lower layer wiring is laid out at the extreme end on both sides, and the upper layer wiring and the lower layer wiring are alternately applied by applying the layout of the first example for the remaining even number. And the last one is laid out on either the upper layer side or the lower layer side, so that the entire adjacent wiring between pixels is laid out with metal wirings of different layers. Of course, the portion intersecting with the vertical wiring is overlapped by connecting the vertical wiring which is the cross wiring with respect to the horizontal wiring by the upper layer wiring and the lower layer wiring. In this way, at least between two adjacent pixel circuits P, the entire adjacent wiring can be laid out with metal wirings of different layers, and the number of shorts between wirings due to dust or the like can be reduced.

  Specifically, in the layout of the third example, the cathode wiring Wcath is handled as a horizontal scanning line, and the cathode wiring Wcath is close to the writing scanning line 104WS which is a horizontal scanning line in the pixel circuit P. This is an example of running in parallel. As shown in the figure, the power supply line 105DSL for switching the power supply voltage at the drain end of the drive transistor 121 between the first potential Vcc and the second potential Vss, and the write scan for driving the gate end of the sampling transistor 125. The line 104WS and the pixel circuit P portion of the video signal line 106HS for supplying the video signal Vsig to the source end of the sampling transistor 125 and the portion intersecting with the cathode wiring Wcath are respectively one of the upper layer side and the lower layer side (here, the upper layer side) Metal wiring). Further, the cathode wiring Wcath of the organic EL element 127 is a metal wiring on the other of the upper layer side and the lower layer side (here, the lower layer side).

  The video signal line 106HS is formed as a lower layer metal wiring because it is necessary to overlap a portion intersecting with the power supply line 105DSL and the write scanning line 104WS in the same layer (which is an upper layer metal wiring). In addition, the metal wiring on the upper layer side of the video signal line 106HS intersecting with the cathode wiring Wcath is extended to the pixel circuit P on the next row adjacent thereto, and the power supply for the same layer on the next row (which is the metal wiring on the upper layer side) is supplied. The line 105DSL is overlapped at the intersection.

  As shown in FIG. 9B (A), in one pixel, the power supply line 105DSL is laid out at the upper end and the write scanning line 104WS and the cathode wiring Wcath are laid out at the lower end. And the cathode wiring Wcath are separated and run in parallel. At this time, the cathode wiring Wcath and the write scanning line 104WS run in parallel (adjacent) in close proximity in different layers.

  Further, as shown in FIG. 9B (B), in the relationship with the adjacent pixel circuit P, the cathode wiring Wcath in the previous row and the power supply line 105DSL in the next row run in parallel (adjacently) in different layers. ).

  In this way, if horizontal metal wirings that run parallel (adjacent) in close proximity are laid out in different wiring layers, the upper and lower layers are connected even if there is dust on the upper layer, which is the upper layer. Since it is not short-circuited, a countermeasure against a short circuit between adjacent wirings can be realized, and a high yield can be realized.

  In the pixel circuit P, adjacent wirings are laid out as much as possible with metal wirings of different layers, and between adjacent two pixel circuits P, adjacent wirings are laid out with metal wirings of different layers, thereby shorting between wirings due to dust or the like. The number can be reduced and a high yield can be realized.

  In addition, since the same-layer wiring can be widened at the pixel boundary, that is, the write scanning line 104WS in the previous row and the next row that are laid out in the same layer with the pixel boundary (also the cathode wiring Wcath) in between. In the relationship of the power supply line 105DSL, the wiring interval can be increased, and therefore, if the diameter of the conductive foreign material is not larger than the large wiring interval, it is not connected (short-circuited). realizable.

  Although the detailed description is omitted, while adopting the layout of the third example, the cathode wiring Wcath on the lower layer side of a certain row, the power supply line 105DSL on the upper layer side of the next row, as in the layout method of the second example, By stacking layers, the pixel pitch in the vertical direction can be narrowed.

<Vertical Wiring and Horizontal Wiring Improvement Method: Fourth Example>
FIG. 9C is a diagram illustrating a fourth example of the wiring form (layout) of the vertical wiring and the horizontal wiring of the pixel array unit 102 employed in the present embodiment. FIG. 9C (A) shows the layout of the scanning wiring for one pixel, and FIG. 9C (B) shows the layout of the scanning wiring of the pixel circuits P for two rows adjacent in the vertical direction.

  The layout of the fourth example is characterized in that not all of the adjacent wirings are laid out in different wiring layers, but a part of each wiring is laid out in the same layer as the adjacent wiring. The portion intersecting with the vertical wiring is overlapped by connecting the vertical wiring with the upper layer wiring and the lower layer wiring. In this way, there is a possibility that a short circuit between adjacent wirings will occur when a part of the wiring is in the same layer as the adjacent wiring, but the number of bridges (connecting metal wirings of different layers) to the horizontal wiring due to vertical wiring. And the load on the vertical wiring can be reduced. Of course, since the adjacent wiring is laid out in a different wiring layer except for a part of which is in the same layer as the adjacent wiring, an effect of a countermeasure against a short circuit between the adjacent wirings can be obtained.

  In the illustrated example, the method of the fourth example is applied to the cathode wiring Wcath based on the layout method of the third example shown in FIG. 9B. As shown in the figure, the power supply line 105DSL for switching the power supply voltage at the drain end of the drive transistor 121 between the first potential Vcc and the second potential Vss, and the write scan for driving the gate end of the sampling transistor 125. The inner side of the pixel circuit P of the line 104WS and the video signal line 106HS for supplying the video signal Vsig to the source end of the sampling transistor 125 is one of the upper layer side and the lower layer side (here, the upper layer side) metal wiring I have to.

  The cathode wiring Wcath of the organic EL element 127 is a metal wiring on one of the upper layer side and the lower layer side (here, the upper layer side) at the portion intersecting with the video signal line 106HS, and the upper layer other than the portion intersecting with the video signal line 106HS. This is a metal wiring on the other side (here, the lower layer side) of the lower layer side and the lower layer side.

  The video signal line 106HS needs to overlap the power supply line 105DSL, the write scanning line 104WS, and the cathode wiring Wcath in the same layer (which is a metal wiring on the upper layer side). ing. In addition, the metal wiring on the lower layer side of the video signal line 106HS intersecting with the write scanning line 104WS and the cathode wiring Wcath is extended to the adjacent pixel circuit P in the next row, and the same layer (upper layer metal in the next row) It is the same layer as the power supply line 105DSL.

  As shown in FIG. 9C (A), in one pixel, the power supply line 105DSL is laid out at the upper end and the write scanning line 104WS and the cathode wiring Wcath are laid out at the lower end, so that the power supply line 105DSL and the write scanning line 104WS are laid out. And the cathode wiring Wcath are separated and run in parallel. At this time, the cathode wiring Wcath and the writing scanning line 104WS run in parallel (adjacent) in different layers except for a portion that intersects with the video signal line 106HS. The adjacent write scanning line 104WS and the cathode wiring Wcath are not wirings of different layers as a whole, and a portion overlapping the video signal line 106HS is wiring of the same layer.

  Further, as shown in FIG. 9C (B), in the relationship with the adjacent pixel circuit P, the cathode wiring Wcath of the previous row and the power supply line 105DSL of the next row are other than the portion intersecting with the video signal line 106HS. It will run parallel (adjacent) in close proximity in different layers. The adjacent cathode wiring Wcath and the next power supply line 105DSL are not wirings of different layers as a whole, and the portion overlapping the video signal line 106HS is wiring of the same layer.

  As described above, in the layout of the fourth example, the layout is the same as the layout method of the third example except for the portion where the cathode wiring Wcath and the video signal line 106HS intersect. You can enjoy the effect. That is, except for the portion where the video signal line 106HS and the cathode wiring Wcath overlap, the adjacent wirings adjacent to each other are laid out in different wiring layers, so that there is an effect of measures against short-circuiting between the adjacent wirings.

  In addition, in the portion where the cathode wiring Wcath which is the horizontal wiring and the video signal line 106HS which is the vertical wiring which intersects the horizontal wiring intersect with each other, the video signal lines are laid out in different wiring layers. A process of overlapping the line 106HS by connecting the upper layer wiring and the lower layer wiring becomes unnecessary. Since the number of bridges of the video signal line 106HS can be reduced, the load on the video signal line 106HS can be reduced.

  The adjacent horizontal adjacent wiring is laid out in the same layer only in the portion overlapping with the video signal line 106HS (vertical wiring), and the other portions are laid out in different wiring layers, thereby reducing the load on the video signal line 106HS. However, a high yield can be realized.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above-described embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

<Modification of drive timing>
In terms of drive timing, various modifications are possible while the timing of the transition of the potential of the power supply line 105DSL from the second potential Vss to the first potential Vcc is the period of the offset potential Vofs which is the ineffective period of the video signal Vsig. is there.

  For example, as a first modification, although not shown, the setting method of the sampling period & mobility correction period K can be modified with respect to the drive timing shown in FIG. Specifically, the timing t15V at which the video signal Vsig transitions from the offset potential Vofs to the signal potential (Vofs + Vin) is first shifted to the second half of one horizontal period from the driving timing shown in FIG. + Vin) period is narrowed.

  When the threshold correction operation is completed (when the threshold correction period I is completed), the signal potential (Vofs + Vin) is first applied to the video signal line 106HS by the horizontal drive unit 106 while the write drive pulse WS remains active H. ) Is supplied (t15), and the period until the write drive pulse WS is made inactive L (t17) is a period for writing information of the signal amplitude Vin to the storage capacitor 120. Information on the signal amplitude Vin is held in a form that is added to the threshold voltage Vth of the drive transistor 121. As a result, fluctuations in the threshold voltage Vth of the drive transistor 121 are always canceled, and threshold correction is performed. By this threshold value correction operation, the gate-source voltage Vgs held in the holding capacitor 120 becomes “(1−g) Vin + Vth”. At the same time, the mobility correction is executed in the signal writing period t15 to t17. That is, the timings t15 to t17 serve as both a signal writing period and a mobility correction period.

  In the period from t15 to t17 in which the mobility correction is performed, the organic EL element 127 does not emit light because it is actually in the reverse bias state. In the mobility correction period t15 to t17, the drive current Ids flows through the drive transistor 121 while the gate terminal G of the drive transistor 121 is fixed at the level of the video signal Vsig. The driving timing is the same as that shown in FIG.

  Each drive unit (104, 105, 106) adjusts the relative phase difference between the video signal Vsig supplied from the horizontal drive unit 106 to the video signal line 106HS and the write drive pulse WS supplied from the write scanning unit 104. Thus, the mobility correction period can be optimized.

  However, the writing & mobility correction preparation period J does not exist, and the timing t15V3 to t17 becomes the sampling period & mobility correction period K. For this reason, a difference in waveform characteristics due to the influence of the wiring resistance and wiring capacitance of the write scanning line 104WS and the video signal line 106HS may affect the sampling period & mobility correction period K. . Since the sampling potential and the mobility correction time are different between the side closer to the writing scanning unit 104 and the far side (that is, the left and right sides of the screen), a luminance difference occurs between the left and right sides of the screen, and there is a difficulty in being visually recognized as shading. Concerned.

  Further, as a second modification, it is possible to change the power supply off timing (transition timing to the second potential Vss side). Specifically, both the off timing and the on timing of the row can be set to the same horizontal period.

  At the drive timing of the second modification, both power supply switching operations are performed during the offset potential Vofs of the video signal Vsig. At this time, the sampling transistor 125 is turned on and the gate terminal G of the drive transistor 121 is set to the offset potential. It is fixed at Vofs and has a low impedance, and the resistance to coupling noise caused by the power pulse (power drive pulse DSL) is improved.

<Modification of Pixel Circuit>
On the pixel circuit side, as a configuration example of a bootstrap circuit and a threshold & mobility correction circuit which are examples of a drive signal stabilization circuit that maintains a drive current constant, a 2TR configuration using an n-channel type as the drive transistor 121 is adopted. Although an example in which the drive timing is devised is shown, this is merely an example of a drive signal stabilization circuit and a drive timing for maintaining a drive signal for driving the organic EL element 127 constant. As the drive signal stabilizing circuit for preventing the influence on the drive current Ids due to deterioration or characteristic variation of the n-channel type drive transistor 121 (for example, variation or fluctuation of threshold voltage or mobility), various other circuits are used. Can be applied.

  For example, since “dual theory” holds in circuit theory, the pixel circuit P can be modified from this point of view. In this case, although not shown in the figure, the pixel circuit P having the 2TR configuration shown in FIG. 5 is configured using the n-channel driving transistor 121, whereas the p-channel driving transistor (hereinafter referred to as p) is used. The pixel circuit P is configured using a type driving transistor 121p. In accordance with this, a change in accordance with the dual reason, such as reversing the polarity of the signal amplitude Vin (signal potential (Vofs + Vin)) of the video signal Vsig and the magnitude of the power supply voltage, is added.

  In addition, although the modification demonstrated here added the change according to "the dual reason" with respect to 2TR structure shown in FIG. 5, the method of a circuit change is not limited to this. In addition to the sampling transistor (an example of a switching transistor) and a driving transistor, other than the 2TR configuration in which another switching transistor for performing a control for keeping the driving current constant is provided. However, in order to realize a small display device that requires high-definition display, it is optimal to realize a drive signal stabilization function with a 2TR configuration.

  Here, also in various modified examples, by applying the mechanism of the present embodiment in which adjacent adjacent wirings are laid out in different wiring layers as much as possible, a short circuit between wirings due to conductive foreign matters can be reduced.

  At this time, when the number of wirings running in the vertical direction or the horizontal direction in the pixel circuit P is an even number, the layout method of the first example (or a second example which is a modified example thereof) is applied, In that case, the layout method of the third example (or the second example which is a modified example thereof) may be applied. In any case, the layout method of the fourth example can be applied.

1 is a block diagram showing an outline of a configuration of an active matrix display device which is an embodiment of a display device according to the present invention. It is a figure which shows the 1st comparative example with respect to the pixel circuit of this embodiment. It is a figure which shows the 2nd comparative example with respect to the pixel circuit of this embodiment. It is a figure explaining the operating point of an organic EL element and a drive transistor. It is a figure explaining the influence which the characteristic variation of an organic EL element or a drive transistor has on a drive current. It is a figure which shows the structural example of the pixel circuit of this embodiment. 6 is a timing chart for explaining a basic example of drive timing of the present embodiment relating to the pixel circuit of the present embodiment shown in FIG. 5. FIG. 7 is an equivalent circuit of the light emission period B at the drive timing shown in FIG. FIG. 7 is a diagram illustrating an equivalent circuit and an operation description of a discharge period C at the drive timing illustrated in FIG. 6. FIG. 7 is an equivalent circuit of an initialization period D at the drive timing shown in FIG. FIG. 7 is an equivalent circuit of the first threshold value correction period E at the drive timing shown in FIG. FIG. 7 is a diagram for explaining an equivalent circuit and operation of the other row write period F at the drive timing shown in FIG. 6. FIG. 7 is an equivalent circuit of the second threshold correction period G at the drive timing shown in FIG. FIG. 7 is a diagram illustrating an equivalent circuit and an operation description of the other row write period H at the drive timing shown in FIG. 6. FIG. 7 is an equivalent circuit of the third threshold value correction period I at the drive timing shown in FIG. FIG. 7 is an equivalent circuit of the write & mobility correction preparation period J at the drive timing shown in FIG. FIG. 7 is an equivalent circuit of the sampling period & mobility correction period K at the drive timing shown in FIG. FIG. 7 is an equivalent circuit of a light emission period L and an operation explanation diagram at the drive timing shown in FIG. 6. It is a figure which shows the change of the source potential of the drive transistor at the time of threshold value correction | amendment operation | movement. It is a figure which shows the change of the source potential Vs of a drive transistor at the time of a mobility correction | amendment operation | movement. It is a figure (for 1 pixel) explaining the comparative example of the wiring form of a pixel array part. It is a figure (for 2 rows) explaining the comparative example of the wiring form of a pixel array part. It is a figure explaining the 1st example of the wiring form of the pixel array part employ | adopted by this embodiment. It is a figure explaining the 2nd example of the wiring form of the pixel array part employ | adopted by this embodiment. It is a figure explaining the 3rd example of the wiring form of the pixel array part employ | adopted by this embodiment. It is a figure explaining the 4th example of the wiring form of the pixel array part employ | adopted by this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Organic EL display device, 100 ... Display panel part, 101 ... Substrate, 102 ... Pixel array part, 103 ... Vertical drive part, 104 ... Write scanning part, 105 ... Drive scanning part, 106 ... Horizontal drive part, 109 ... Control unit, 120 ... holding capacitor, 121 ... drive transistor, 122 ... light emission control transistor, 125 ... sampling transistor, 127 ... organic EL element (an example of an electro-optical element), 200 ... drive signal generation part, 300 ... video signal processing part , Cel ... parasitic capacitance, P ... pixel circuit

Claims (11)

A driving transistor that generates a driving current, a holding capacitor that holds information according to the signal amplitude of the video signal, an electro-optic element connected to the output terminal side of the driving transistor, and information corresponding to the signal amplitude in the holding capacitor And a pixel circuit that emits light from the electro-optic element when the drive transistor generates a drive current based on the information held in the storage capacitor and flows it through the electro-optic element. A pixel array unit,
A drive signal stabilization circuit comprising a transistor and controlling the transistor to maintain the drive current constant;
Two adjacent scanning lines for controlling the transistors constituting the pixel circuit and the drive signal stabilizing circuit are formed in different wiring layers in the pixel circuit and at the boundary between adjacent pixel circuits. A display device. The display device according to claim 1, wherein each of the adjacent two scanning lines is formed in the different wiring layer. 2. The display device according to claim 1, wherein one of the two adjacent scanning lines and most of the other excluding a part of the other scanning line are formed in the different wiring layers. A cross wiring crossing the two adjacent scanning lines;
4. The display device according to claim 3, wherein the other of the two adjacent scanning lines is formed in the same layer as the intersection wiring. 5. The pixel circuit has an even number of scanning lines running in parallel in the same direction for controlling the transistors constituting the pixel circuit and the drive signal stabilization circuit,
The display device according to claim 1, wherein the even number of scanning lines are alternately formed by upper layer wirings and lower layer wirings within a pixel pitch in which the pixel circuits are arranged. The pixel circuit has an odd number of scanning lines running in parallel in the same direction for controlling the transistors constituting the pixel circuit and the drive signal stabilization circuit,
One of the odd number of scanning lines is formed in one of the upper layer wiring and the lower layer wiring at one end in the pixel pitch in which the pixel circuit is arranged,
The other one of the odd number of scanning lines is formed on the other of the upper layer wiring and the lower layer wiring at the other end in the pixel pitch in which the pixel circuit is arranged. The display device according to claim 1. 7. The display device according to claim 6, wherein even-numbered scanning lines among the odd-numbered lines are alternately formed by upper layer wirings and lower layer wirings within a pixel pitch in which the pixel circuits are arranged. . In two adjacent pixel circuits,
One of the upper layer wiring and the lower layer wiring formed at the end adjacent to the other pixel circuit in one pixel circuit, and the end adjacent to the one pixel circuit in the other pixel circuit 7. The display device according to claim 5, wherein the other of the formed upper layer wiring and lower layer wiring is laminated with an insulating layer interposed therebetween. The drive signal stabilization circuit supplies a video signal switched between a reference potential and a signal potential to the sampling transistor, and a voltage corresponding to a first potential used to flow a drive current to the electro-optic element is the drive transistor. The voltage corresponding to the threshold voltage of the driving transistor is held in the holding capacitor by conducting the sampling transistor in a time zone in which the reference potential in the video signal is supplied to the sampling transistor. The display device according to claim 1, wherein the display device is configured to realize a threshold correction function. The drive signal stabilization circuit has a threshold correction function for holding a voltage corresponding to the threshold voltage of the drive transistor in the holding capacitor, and a signal potential in the holding capacitor by conducting the sampling transistor after the threshold correction operation. And a mobility correction function for adding a correction amount for the mobility of the driving transistor to a signal written to the storage capacitor when writing information according to the characteristics. The display device according to 1. The drive signal stabilization circuit is configured to realize a bootstrap function by connecting the storage capacitor between a control input terminal and an output terminal side of the drive transistor. The display device according to claim 1.

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