JP2009129480A - Threshold control method for nonvolatile semiconductor memory device - Google Patents

Abstract

A threshold value control method for a nonvolatile semiconductor memory device capable of shortening a writing time is provided.
The memory includes a memory cell capable of holding a multi-valued state by adjusting a threshold voltage, and a word line commonly connected to the plurality of memory cells, and is adjusted to a state other than an erased state. A threshold control method for a nonvolatile semiconductor memory device, wherein verify reading is performed on a cell and writing is performed by increasing a write voltage applied to the word line for the memory cell that has not reached a target threshold value. The write voltage applied to the word line at the time of writing the first memory cell adjusted to the first target threshold is adjusted to the second target threshold having the second highest threshold voltage after the first target threshold. The second memory connected to the first memory cell and the word line common to the first memory cell when the voltage exceeds the write start voltage of the second memory cell. It provided against and Le, a step of writing the same time.
[Selection] Figure 9

Description

  The present invention relates to a threshold control method for a nonvolatile semiconductor memory device, for example, a method for adjusting multi-value data stored in a memory cell.

  Along with the increase in capacity and cost of nonvolatile semiconductor memory devices such as flash memories, multi-value storage for holding a plurality of bits of data in one memory cell has been advanced. In a multi-level memory, if the threshold voltage corresponding to each data state has a wide distribution, the interval between adjacent states becomes narrow, and it becomes difficult to read data reliably. A very narrow distribution is required for each threshold. For example, Patent Document 1 discloses a writing method for obtaining a narrow threshold voltage distribution.

  In such a multilevel memory, with the miniaturization of a memory cell, a variation in the threshold value of a memory cell adjacent to a certain memory cell has caused the adjacent effect that the threshold value of the certain memory cell varies. Yes.

In addition, even though a very narrow threshold distribution is required, the adjustment time (writing time) is required to be shortened. For example, Patent Document 2 discloses a writing method for improving the writing speed.
JP 2004-94987 A JP 2007-141447 A

  The present invention provides a threshold control method for a nonvolatile semiconductor memory device capable of shortening the writing time.

  A threshold control method for a nonvolatile semiconductor memory device according to one embodiment of the present invention includes a memory cell that can hold a multi-valued state by adjusting a threshold voltage, and a word line that is commonly connected to the plurality of memory cells. Then, verify reading is performed on the memory cell adjusted to a state other than the erased state, and writing is performed on the memory cell that has not reached the target threshold by increasing the write voltage applied to the word line. A method for controlling a threshold value of a nonvolatile semiconductor memory device, wherein a write voltage applied to the word line at the time of writing to a first memory cell adjusted to a first target threshold is next to the first target threshold. The first memory cell and the first memory cell when the threshold voltage is equal to or higher than the write start voltage of the second memory cell that is adjusted to the second target threshold value Against said second memory cells connected to a common said word lines, characterized in that it comprises a step of writing the same time.

  According to the present invention, it is possible to provide a threshold value control method for a nonvolatile semiconductor memory device that can shorten the writing time.

  Before describing the embodiment of the present invention, the adjacency effect will be described by taking the case where the nonvolatile semiconductor memory device is a NOR flash memory as an example.

  In general, the NOR flash memory has a plurality of memory cells MC arranged in a matrix as shown in FIG. In FIG. 13, only memory cells MC in the same column are shown. Each memory cell MC includes a source region S and a drain region D formed on the semiconductor substrate, and a gate insulating film (not shown) formed on the semiconductor substrate that becomes a channel region between the source region S and the drain region D. ), A floating gate FG formed on the gate insulating film, an interelectrode insulating film (not shown) formed on the floating gate FG, and a control gate CG formed on the interelectrode insulating film And.

  The memory cells MC in the same column share the source region S or the drain region D with the adjacent memory cells MC in the same column. The drain regions D of the memory cells MC in the same column are connected in parallel to a common bit line BL via a bit line contact BC (not shown). The control gates CG of the memory cells MC in the same row are connected to a common word line WL.

  FIG. 13 shows a NOR flash memory having a structure in which a ground potential is supplied via the source region S of each memory cell MC. However, as shown in FIG. 14, the source region of the memory cells MC in the same row is shown. A structure in which S is connected by a source line SL below the bit line BL and a ground potential is supplied via the source line SL may be employed.

  In the NOR type flash memory configured as described above, threshold adjustment (writing) of each memory cell MC applies a predetermined voltage to the control gate CG and the drain region D, and grounds the source region S and the semiconductor substrate. This is done by injecting channel hot electrons generated by setting the potential into the floating gate FG.

  When electrons are injected into the floating gate FG of a certain memory cell MC, as shown in FIG. 15, capacitive coupling C occurs between the floating gate FG of the memory cell MC adjacent to the memory cell MC, and the adjacent memory cell MC. The adjacent effect that the threshold voltage of the memory cell MC changes occurs.

  In the NOR flash memory, as shown in FIG. 16, the drain region D of the memory cells MC in the same column is connected to the bit line BL via the bit line contact BC. For this reason, the adjacent memory cells sharing the drain region D in the bit line direction (same column direction) are shielded by the bit line contact BC, and the adjacent effect does not occur.

  However, adjacent effects occur between adjacent memory cells in the word line direction (same row direction) and between adjacent memory cells sharing the source region S in the bit line direction (same column direction). However, in the NOR flash memory shown in FIG. 14 in which the source region S in the word line direction (same row direction) is connected to the common source line SL, the potential is shielded by the source line SL and the word line direction (same row) The adjacent effect occurs only between the memory cells MC in the direction). Since the NAND flash memory has a structure in which memory cells in the same column are connected in series, the adjacent effect occurs between all adjacent memory cells.

  Therefore, in the NOR type flash memory shown in FIG. 13, write data to the memory cell group connected to at least two word lines WL, and in the NOR type flash memory shown in FIG. 14, connected to at least one word line WL. If the data to be written to the memory cell group to be written is not determined before writing, it is impossible to adjust the threshold value for all the memory cell groups in which the adjacent effects are generated almost simultaneously.

  In the following embodiments, it is assumed that a NOR flash memory having the structure shown in FIG. 14 is assumed, and that write data of a memory cell group connected to at least one word line is determined. In the following embodiment, the multilevel distribution of each memory cell MC is set to (11) for the erased state, and the remaining three states are set to (10), (00), (01 ).

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
A multilevel data adjustment method for a nonvolatile semiconductor memory device according to a first embodiment of the present invention will be described. FIG. 1 is a block diagram schematically showing an example of the entire configuration of a NOR type flash memory 100 to which the multi-value data adjustment method of the nonvolatile semiconductor memory device according to the first embodiment can be applied. Note that the substantially same configuration as the above-described general NOR flash memory is denoted by the same reference numeral, and description thereof is omitted.

  The NOR flash memory 100 of the present embodiment includes, for example, an address latch 101, an address counter 102, an address buffer 103, an I / O buffer 104, a data latch 105, a memory cell array 106, a read sense amplifier circuit 107, and a column gate circuit 108. A page buffer 109, a multi-value compression circuit 110, a write circuit 111, a verify sense amplifier circuit 112, a command register 113, an internal controller 114, a row decoder 115, a column decoder 116, a charge pump circuit 117, and a regulator circuit 118.

  In FIG. 1, an address latch 101 receives and latches an address from an external address bus. The address counter 102 receives and counts the latch address of the address latch 101. The address buffer 103 receives the count output of the address counter 102 and outputs an internal address corresponding to the memory cell MC to be written, read or erased.

  The I / O buffer 104 exchanges read data / write data between the external data bus and the internal data latch 105. The memory cell array 106 has a structure in which a plurality of nonvolatile memory cells MC are arranged in a matrix, like the above-described general NOR flash memory, and includes a word line WL and a bit connected to each memory cell. A line BL and a source line SL are provided. The memory cell array 106 may be divided into units called banks that can be written and read simultaneously in parallel.

  The read sense amplifier (S / A) circuit 107 senses the data of the memory cell MC in the memory cell array 106 through the column gate circuit 108 at the time of reading, and outputs it to the data latch 105. For example, by applying a predetermined read voltage to the word line WL and comparing a cell current flowing through the bit line BL with a reference current flowing through a reference cell (not shown), data in the memory cell MC is read.

  As in the comparative example, the memory cell MC can store quaternary data by subdividing and controlling the amount of electrons injected into the floating gate FG. That is, in the multi-value distribution of each memory cell MC, the erased state is (11), and the remaining three states are defined as (10), (00), and (01) from the lowest threshold voltage. Note that the assignment of data to the multi-value distribution is not limited to this. The data that can be stored in the memory cell MC is not limited to four values. For example, n-value data (n is a positive integer of 4 or more) can be stored.

  The page buffer 109 latches write data supplied from the data latch 105. The number of page buffers necessary for determining the write data of the memory cell group connected to at least one word line WL is prepared.

  The multi-value compression circuit 110 compresses multi-value write data supplied from the page buffer 109 at the time of writing and outputs the compressed data to the write circuit 111. The write circuit 111 receives write data supplied from the multi-value compression circuit 110 at the time of writing, and supplies a write voltage to the corresponding bit line BL in the memory cell array 106 via the column gate circuit 108.

  The verify sense amplifier circuit 112 senses the data of the memory cell MC in the memory cell array 106 via the column gate circuit 108 at the time of verify read for verifying whether or not writing has been performed to a desired threshold voltage or higher. , Output to the page buffer 109. For example, the data of the memory cell MC is read by applying a predetermined verify voltage to the word line WL and comparing a cell current flowing through the bit line BL with a reference current flowing through a reference cell (not shown).

  By performing the verify read, the internal controller 114 compares the write data with the output data of the verify sense amplifier 112, and if they match, the write data latched in the page buffer 109 is updated to the write non-target data. If not, the data latched in the page buffer 109 is maintained without being updated. By repeatedly performing the writing and the verify reading, it is possible to continue writing only to the memory cell MC that is insufficiently written without writing to the memory cell MC that has already been sufficiently written.

  The command register 113 holds a command (write command, read command, erase command, etc.) input from an external control bus. The internal controller 114 receives a command held in the command register 113 and generates a control signal for controlling each circuit in the NOR flash memory 100.

  The row decoder 115 receives the internal address output from the address buffer 103 and selects the corresponding word line WL in the memory cell array 106. A write voltage, a read voltage, an erase voltage, and the like are applied to the word line WL selected by the row decoder 115 in accordance with each operation such as write, read, and erase.

  The column decoder 116 receives the internal address output from the address buffer 103 and selectively drives the column gate in the column gate circuit 108 according to the internal address. As a result, the data of the memory cell MC connected to the selected bit line BL in the memory cell array 106 can be read out to the read sense amplifier circuit 107 or the verify sense amplifier circuit 112.

  The charge pump circuit 117, which is a booster circuit, boosts the external power supply voltage to generate a high voltage (write voltage, erase voltage, etc.) corresponding to each operation such as write, read, and erase. This is supplied to the circuit 111, the row decoder 115, and the like.

  The regulator circuit 118 generates and outputs a voltage supplied to the word line, that is, the control gate CG of the memory cell MC, from the voltage obtained by the charge pump circuit 117 when the memory cell MC is written or read. The voltage generated by the regulator circuit 118 is supplied to the word line WL in the memory cell array 106 via the row decoder 115.

  Hereinafter, the multi-value data adjustment method according to the present embodiment will be described using the NOR flash memory 100 having the above configuration as an example.

  In the flash memory, in order to reduce the above-described adjacent effect, it is necessary to suppress the threshold value fluctuation of the adjacent memory cell as much as possible after the adjustment of the threshold value of the memory cell MC to be written. For this purpose, first, it is necessary to adjust the threshold values almost simultaneously for the memory cell groups in which the adjacent effects are generated.

  In general, the NOR flash memory has a larger erase unit (for example, 128 Kbyte block unit) than a write unit (for example, 16-bit word unit). Since only the data cannot be erased, it is necessary to pay attention to overwriting when adjusting the multi-value data of the memory cell MC (when writing to the memory cell).

FIG. 2 schematically shows a threshold distribution in each state of the memory cell MC controlled by the multi-value data adjustment method according to the present embodiment. In the multi-value data adjustment method according to the present embodiment, as shown in FIG. 2, the target threshold values (verify voltages) V _th of the states (10), (00), and (01) are set to V _th1 and V _{th2, respectively.} , V _th3, and the target widths W _th of the respective threshold distributions are W _th1 , W _th2 , W _th3 .

That is, the adjusted threshold value of the memory cell MC in the state (10) needs to be between V _{th1 and} V _th1 + W _th1 , and the adjusted threshold value of the memory cell MC in the state (00) Needs to exist between V _{th2 and} V _th2 + W _th2 , and the threshold value after adjustment of the memory cell MC in the state (01) exists between V _{th3 and} V _th3 + W _th3 There is a need. In addition, when the data is read, the read sense amplifier circuit 107 satisfies the relations V _th2 > V _th1 + W _th1 and V _th3 > V _th2 + W _th2 in order to determine each state.

It is assumed that all memory cells in the memory cell group to be subjected to multilevel adjustment are in the erased state (11) before the multilevel adjustment. That is, the upper limit of the threshold value of the memory cell MC is V _th0 (<V _th1 ) or less, and the lower limit is 0 V or more. This is because when the threshold value of the memory cell MC is lower than 0V (over-erased state), the current leaks from the bit line BL when the word line WL voltage is 0V. By repeating weak writing and verify reading after erasing data, the threshold value of the memory cell MC in the erased state (11) is set between 0 and _Vth0 .

  The multi-value data adjustment method of this embodiment is shown in FIG. In the multi-value data adjustment method of the present embodiment, two types of write methods (first write method and second write method) for the states (10), (00), and (01) that require threshold adjustment. Define

  First, writing to the memory cell MC is performed by the first writing method. The first writing method is characterized in that writing to the memory cell MC is performed without performing verify reading (see step S1 in FIG. 3). In this first write method, the row decoder 115 selects a write voltage at which “overwrite” does not occur for the memory cell MC in any of the states (10), (00), and (01) after adjustment. This is performed by applying to the control gate CG of the memory cell MC through the word line WL.

The threshold adjustment by the first write method may be performed by applying a predetermined write voltage _Vprg corresponding to each state to the word line WL only once, or increases with a predetermined step-up width _Vstep . The writing voltage may be applied by applying it in a plurality of times. In any case, the write voltage does not cause overwriting. The step-up width V _step may be set to a different value in each of the states (10), (00), and (01), and the rate of increase may or may not be constant.

Here, “overwriting” does not occur when, for example, the state of the adjusted memory cell is in the state (01), the upper limit of the threshold value of the memory cell MC by this first writing is V _th3 + W _th3 It means the following.

  All the memory cells that should be in the states (10), (00), and (01) after adjustment in the memory cell group connected to the selected word line WL to be written are adjusted by the first write method. Perform for MC. Note that when threshold adjustment in a certain state is performed (writing is performed), the memory cell MC to be in another state connected to the same word line WL is not selected (0 V is supplied to the drain region D from the bit line BL. It is said that.

  At this time, first, the first write method is performed on the memory cell MC having the highest threshold value (01) after adjustment, and then the adjusted state is any one of (00) and (10). It is preferable that the first write method is performed on all the memory cells MC that are one, and then the first write method is performed on all the memory cells MC that are the other (FIG. 4A). reference).

  This is because in the NOR flash memory 100, there is no problem even if overwriting due to the adjacent effect occurs in the memory cell MC that has the highest threshold value (01) after adjustment. Even if the distribution of the state with the highest threshold (01) is shifted to the high voltage side due to the adjacent effect, there is no problem of erroneous data reading because there is no state with a higher threshold, and in the NOR flash memory, Since the memory cell MC is connected in parallel to the bit line BL, it is not necessary to guarantee the on state of the non-selected memory cell unlike the NAND flash memory, and the cell current of the non-selected memory cell MC is ensured. This is because it is not necessary to consider the margin.

  The numbers in parentheses in FIG. 4A indicate a preferable order in which threshold adjustment is performed by the first writing method. In this first writing method, writing is performed without performing verify reading, so that electrons are injected without distinguishing between memory cells MC having relatively good writing characteristics and memory cells MC having relatively poor writing characteristics. Thus, the width of the threshold distribution corresponding to each state is considerably widened (see FIG. 4A).

  The threshold adjustment by the first writing method can shorten the time required for the subsequent threshold adjustment by the second writing method by making the upper limit of the threshold voltage of the memory cell MC after writing as high as possible. Further, by performing the first writing in a plurality of times, the write current can be suppressed and the number of memory cells to be collectively written can be increased. Further, the write time can be shortened by omitting the verify read.

In the first writing method, it is possible to increase the threshold value up to the vicinity of the target threshold value in a range where overwriting does not occur, but in what range the threshold value of each state at the time when the first writing method is completed. The setting may be appropriately set in consideration of the write characteristics of the memory cell MC, the required write time, and the like. For example, as shown in FIG. 4A, the threshold distribution in each state may be set so as not to exceed the target threshold (verify voltage) _Vth when the threshold adjustment by the first writing method is completed.

Next, threshold adjustment by the second writing method is performed on each memory cell MC that should be in the states (10), (00), and (01) after adjustment. In the second write method, after writing to the memory cell MC, verify read with respect to the target threshold value (verify voltage) _Vth of the memory cell MC is performed using the verify sense amplifier circuit 112, and the memory cell MC that is insufficiently written is written. That is, for the memory cells MC whose threshold value does not exceed the target threshold value, additional writing is performed while increasing the write voltage V _prg applied to the word line WL selected by the row decoder 115 with a predetermined step-up width V _step. This is performed (see steps S2 to S5 in FIG. 3).

The step-up width V _step may be set to a different value in each of the states (10), (00), and (01), and the rate of increase may or may not be constant. Also, a value different from the first writing method may be set.

  This additional writing and verify reading are repeated until the writing shortage is resolved. In this case, the write voltage first applied to the word line WL is set to a voltage that does not cause “overwriting” even for the memory cell MC having good write characteristics.

  In addition, after the transition from the first writing method to the second writing method, before the first writing, verify reading is performed using the verifying sense amplifier circuit 112 (see step S2 in FIG. 3). As a result, it is possible to prevent further writing from being performed on the memory cell MC that has already been sufficiently written.

When all the memory cells MC pass the verify read and the threshold value adjustment by the second write method is completed, the threshold value of each memory cell MC is positioned in the range of the target threshold value V _th to the target threshold value V _th + the target width W _th. Will do. For example, if the state after the multi-value adjustment of the memory cell MC is (01), it is in the range of V _{th3 to} V _th3 + W _th3 , and if it is (00), the range of V _{th2 to} V _th2 + W _th2 . If it is (10), it is located in the range of V _{th1 to} V _th1 + W _th1 (see FIG. 4B).

  FIG. 4B is a schematic diagram showing the threshold distribution of the memory cells MC in each state after the threshold adjustment by the second write method is completed. In the second write method, as in the first write method, first, the second write method is performed on the memory cell 10 having the highest threshold value (01) after adjustment, The second write is performed on all the memory cells MC in which the adjusted state is any one of (00) and (10), and then the second write is performed on all the other memory cells MC. It is preferable to perform writing.

  The numbers in parentheses in FIG. 4B indicate a preferable order in which threshold adjustment is performed by the second writing method. This is because, as described above, in the NOR flash memory, there is no problem even if overwriting due to the adjacent effect occurs in the memory cell MC that has the highest threshold value (01) after adjustment.

  As described above, according to the present embodiment, the first write method for performing writing so that overwriting does not occur without verifying the memory cell groups in which the adjacent effects are generated. Then, the threshold adjustment is performed by using the second write method in which the verify read is performed first, and the additional write and the verify read are performed on the insufficiently written memory cell MC so that overwriting does not occur. I do.

  That is, the threshold value distribution of the memory cells MC connected to one word line WL is shifted to a position that is somewhat close to the target threshold value in each state to some extent by the first write method. It is possible to reduce the adjacency effect received during threshold adjustment by the second writing method for determining a typical threshold distribution. Therefore, the distribution of each threshold value of the memory cell MC can be narrowed and the adjacent effect can be suppressed.

  In the present embodiment, the first write method is performed for all the memory cells MC in the states (10), (00), and (01), and then the states (10) and (00). , (2) is applied to all the memory cells MC that become (01), but the present invention is not limited to this. For example, the first write method may be performed only for a specific state among the memory cells MC in the states (10), (00), and (01). Further, the second write method may be performed only for a specific state among the memory cells MC in the states (10), (00), and (01). Further, for example, a plurality of modifications shown below can be considered.

(Modification 1)
First, the first write method is performed on the memory cell MC in the state (01) to form a threshold distribution that is somewhat close to the target threshold value. Subsequently, before the first write method is performed on the state (10) or the state (00), the second write method is performed on the memory cell MC in the state (01). Thereby, the threshold voltage of the memory cell MC in the state (10) is located in the range of V _{th1 to} V _th1 + W _th1 .

  Next, the first writing is performed on the memory cell MC in one of the state (10) and the state (00), and then the second writing method is performed. Thereafter, the first write method is performed on the memory cell MC in the other state, and then the second write method is performed.

  Since the distribution of the state (01) allows a change in the threshold voltage due to the adjacent effect to some extent as described above, the distribution of each threshold value of the memory cell MC can be narrowed and the adjacent effect can be obtained also by such a method. Can be suppressed.

(Modification 2)
First, for the memory cell MC that is in the state (01), the first write method is performed to form a threshold distribution that is somewhat close to the target threshold value. Subsequently, the second write method is performed on the memory cell MC in the state (01). Thereby, the threshold voltage of the memory cell MC in the state (10) is located in the range of V _{th1 to} V _th1 + W _th1 .

  Next, with respect to the memory cell MC in one of the state (10) and the state (00), the writing method is performed by the second writing method without performing the first writing method, and the other For the memory cells MC in this state, the write method is performed by the second write method without performing the first write method.

  Since the distribution of the state (01) allows a change in the threshold voltage due to the adjacent effect to some extent as described above, the distribution of each threshold value of the memory cell MC can be narrowed and the adjacent effect can be obtained also by such a method. Can be suppressed.

(Second Embodiment)
Next, a multilevel data adjustment method for a nonvolatile semiconductor memory device according to a second embodiment of the present invention will be described. This embodiment can be applied to, for example, the NOR flash memory 100 shown in the first embodiment.

  Since the first write method according to the first embodiment does not perform verify read, the threshold distribution of the memory cells MC corresponding to the states (10), (00), and (01) after the write is performed is wide. When the threshold value distribution is narrowed by performing the second writing method on the wide threshold distribution, the memory cell MC whose threshold after the writing by the first writing method is far from the target threshold is written in the second writing method. The threshold fluctuation amount in the process of threshold adjustment by the method is large.

  As a result, the memory cell MC whose threshold after the end of writing by the first writing method is close to the target threshold value immediately ends the threshold adjustment by the second writing method, while the writing by the first writing method is completed. In the memory cell MC with the far threshold after the completion, additional writing and verify reading are repeated. Therefore, the threshold value after the end of writing by the first writing method is close to the target threshold value, and the adjacent effect on the memory cell MC in which the threshold adjustment by the second writing method has ended immediately becomes very large. .

Therefore, the present embodiment is characterized in that threshold adjustment in the second writing method is performed in two stages. That is, in the threshold adjustment in the second writing method, each state (10), (00), (01) is first performed using a threshold voltage (low verify voltage) _VLth lower than the target threshold (verify voltage) _{Vth .} Are adjusted to form a first multi-value distribution. Thereafter, using the final target threshold value _Vth , the threshold values of the states (10), (00), and (01) are adjusted again to form a second multi-value distribution.

  In the present embodiment, in the second writing method, the threshold adjustment performed when forming the first multi-value distribution is performed when performing the low verify step, and then forming the second multi-value distribution. The threshold adjustment is referred to as a verify step. Hereinafter, the threshold adjustment method according to the present embodiment will be described with reference to FIGS. 5 to 6C.

  FIG. 5 is a flowchart showing multi-value data threshold adjustment according to the present embodiment. FIGS. 6A, 6B, and 6C schematically show threshold distributions in the respective states of the memory cell MC when the write sequence of FIG. 5 is applied.

  First, in the multi-value data adjustment method of this embodiment, as shown in FIG. 6A, as in the first embodiment, writing by the first writing method is performed after the adjustment in the states (10), (00). , (01) for all the memory cells MC. As in the first embodiment, the threshold adjustment by the first write method may be performed by applying a predetermined write voltage to the word line WL only once, or a write voltage that increases with a predetermined step-up width. May be performed by applying in multiple steps. (See step S1 in FIG. 5).

  In the threshold adjustment by the first writing method, as in the first embodiment, writing is performed on the memory cell MC that is in the state (01) having the highest threshold after the adjustment, and then the state after the adjustment is ( (00) and (10), it is preferable to write to all memory cells, and then write to all other memory cells. The numbers in parentheses in FIG. 6A indicate a preferable order in which threshold adjustment is performed by the first writing method.

Thereafter, as shown in FIG. 6B, threshold adjustment is performed by the second writing method (low verify step) to form a first multi-value distribution (see steps S2 to S5 in FIG. 5). Unlike the first embodiment, the write performed in this row verify step is applied with a voltage applied to the word line WL lower than the target threshold _values V _th1 , V _th2 , and V _th3 in each state. First values (low verify voltages) V _Lth1 , V _Lth2 and V _Lth3 are set, respectively.

By repeating the adding and verify reading writing using the first value _{V Lth1, V Lth2, V Lth3} , threshold adjustment of each state is carried out. Note that the verify read performed by setting a value lower than the final target voltage (verify voltage) is hereinafter referred to as row verify read.

In the first multi-value distribution, second values W _Lth1 , W _Lth1 , and W _Lth1 that are target widths are set for the respective first values. Memory cell threshold of MC after forming a first multi-level distribution, for each state, each present in the range of the first value _{V Lth} ~ first value _{V Lth} + second value _{W Lth} It will be.

  In the row verify step, the row verify read is performed on each memory cell MC with respect to the target threshold value of the memory cell MC, and the memory cell MC whose write is insufficient, that is, the memory cell MC whose threshold voltage does not exceed the target threshold value. Thus, additional writing and row verify reading are performed while increasing the voltage applied to the word line WL with a predetermined step-up width. This additional writing and row verify reading are repeated until the writing shortage is resolved.

  In the present embodiment, after shifting from the first writing method to the row verifying step of the second writing method, before performing the first writing, row verify reading is performed (see step S2 in FIG. 5). As a result, it is possible to prevent further writing from being performed on the memory cell MC that has already been sufficiently written. However, since the first multi-value distribution has a lower threshold voltage than the final second multi-value distribution, if the possibility of overwriting is sufficiently low, the first verify read is omitted. May be.

In the first multi-level distribution formed by performing the low verify step, the threshold voltage of each state, state (10) is _V Lth1 _~V Lth1 _{+ W Lth} 1 range, condition (00) is _{V Lth2} range of ~V _Lth2 + _{W Lth2,} state (10) is controlled to be in the range of _{V Lth2 ~V} Lth2 _{+ W} Lth2.

Here, the threshold voltages of the respective states in the first multi-value distribution are set so as to satisfy the conditions of, for example, V _Lth1 + W _Lth1 <V _th1 , V _Lth2 + W _Lth2 <V _th2 , V _Lth3 + W _Lth3 <V _th3 be able to. If the threshold voltage difference between the first multi-value distribution and the second multi-value distribution is small, it is possible to shorten the writing time in the subsequent verify step. If the threshold voltage difference between the first multi-value distribution and the second multi-value distribution is large to some extent, the possibility of overwriting can be reduced.

  In the threshold adjustment by the low verify step, as in the first embodiment, writing is performed on the memory cell MC that has the highest threshold value (01) after the adjustment, and then the adjusted state is (00 ) And (10), it is preferable to write to all the memory cells that are one of them, and then write to all the memory cells that are the other. The numbers in parentheses in FIG. 6B indicate a preferable order in which threshold adjustment is performed by the first writing method.

Thereafter, as shown in FIG. 6C, threshold adjustment is performed by the second writing method (verify step) to form a second multi-value distribution (final multi-value distribution) (steps S6 to S6 in FIG. 5). (See S9). That is, for each memory cell MC, verify reading is performed with respect to the target threshold value of the memory cell MC, and a word line is applied to a memory cell MC that is insufficiently written, ie, a memory cell MC whose threshold voltage does not exceed the target threshold value the write voltage _{V prg} to be applied to WL perform additional writing and verify reading while increasing by a predetermined step-up width _{V step.}

This additional writing and verify reading are repeated until the writing shortage is resolved. In the second multi-value distribution formed by performing this verify step, the threshold value of the memory cell MC in each state is the target threshold value as in the threshold distribution finally formed in the first embodiment. It exists in the range of _Vth -target threshold value _Vth + target width _Wth .

That is, if the state after the multi-value adjustment of the memory cell 10 is (01), it is in the range of V _{th3 to} V _th3 + W _th3 , and if it is (00), the range of V _{th2 to} V _th2 + W _th2 . If it is (10), it is located in the range of V _{th1 to} V _th1 + W _th1 (see FIG. 6C).

  In addition, after the transition from the row verify step of the second write method to the verify step of the second write method, verify read is performed before the first write (see step S6 in FIG. 5). As a result, it is possible to prevent further writing from being performed on the memory cell MC that has already been sufficiently written.

  In the threshold adjustment by the verify step, as in the first embodiment, writing is performed on the memory cell 10 having the highest threshold value (01) after the adjustment, and then the adjusted state is (00 ) And (10), it is preferable to write to all the memory cells that are one of them, and then write to all the memory cells that are the other. The numbers in parentheses in FIG. 6C indicate a preferable order in which threshold adjustment is performed by the first writing method.

  As described above, according to the present embodiment, since the first multi-value distribution is formed and then the second multi-value distribution (final multi-value distribution) is formed, the second multi-value distribution is formed. It is possible to reduce the threshold fluctuation amount of the memory cell MC when forming the distribution, and to suppress the adjacent effect.

  In the present embodiment, the adjacent effect that occurs when the first multi-value distribution is formed sets the threshold value for forming the first multi-value distribution lower than the target threshold value. The difference can be absorbed, and the formation of the second multi-value distribution is not affected.

Further, the write voltage _Vprg applied to the word line WL at the start of writing at the time of forming the second multi-value distribution is the end of the first multi-value distribution formation so that the memory cell MC having good write characteristics will not be overwritten. It is preferable to execute from a voltage lower than the voltage applied to the current word line WL.

  In the present embodiment, the first write method is performed for all the memory cells MC in the states (10), (00), and (01) after adjustment, and then the state (10) after adjustment. , (00) and (01) are all subjected to the row verify step of the second writing method for all the memory cells MC, and then, after adjustment, the states (10), (00) and (01) are obtained. Although the verify step of the second write method is performed on all the memory cells MC, the present invention is not limited to this.

  For example, the first write method may be performed only for a specific state among the memory cells MC in the states (10), (00), and (01). In addition, the row verify step of the second write method may be performed only for a specific state among the memory cells MC in the states (10), (00), and (01). In addition, the verify step of the second write method may be performed only for a specific state among the memory cells MC in the states (10), (00), and (01).

  Furthermore, as described in the first embodiment, since the distribution of the state (01) allows a change in threshold voltage due to the adjacent effect to some extent, for example, the threshold voltage of the state (01) is adjusted first (state ( 10), the first write method, the second write method row verify step, and the second write method verify step are performed on the memory cell MC that becomes 10), and then the state (10) or (00) The threshold voltage may be adjusted. In this case, the threshold value adjustment of the memory cell MC in the state (01) may omit the row verify step.

  In accordance with each state, whether to execute the first write method, whether to perform the row verify step of the second write method, or whether to perform the verify step of the second write method is set. By doing so, various modifications as described in the modification of the first embodiment can be realized.

(Third embodiment)
Next, a multi-value data adjustment method for a nonvolatile semiconductor memory device according to a third embodiment of the present invention will be described with reference to FIGS. 7 and 8 are flowcharts showing the procedure of the multi-value data adjustment method of the present embodiment. FIG. 9 is a waveform diagram of a voltage applied to the word line WL in the multi-value data adjustment method of this embodiment. This embodiment can be applied to, for example, the NOR flash memory 100 shown in the first embodiment.

Hereinafter, the write voltage _{V prg} to be applied to the selected word line WL at the time of writing, the state (10) of the write start voltage _{V prg1,} state (00) of the write start voltage _{V prg2,} the write start voltage state (01) The description will be made _assuming that V _prg3 is set. Here, it is _{assumed that} the relationship of V _prg1 <V _prg2 <V _prg3 is established.

In the multi-value data adjustment method of the present embodiment, first, the write voltage V _prg is set to the write start voltage V _prg1 (step S10 in FIG. 7). Then, verify read (time t1 to t2) is performed on all of the memory cells MC that are in the state (10) having the lowest threshold value after adjustment in the memory cell group connected to the selected word line WL to be written. This is performed (step S11 in FIG. 7).

As a result of the verify read, the memory cell MC determined to have passed the verify in step S12, that is, the memory cell MC written up to the threshold voltage equal to or higher than the verify voltage V _th1 is the target of writing in the next write operation (step S13). Excluded. On the other hand, as a result of the verify read, the memory cell MC that is determined not to pass verify, that is, the memory cell MC that has not reached the threshold voltage to the verify voltage _Vth1 , is written (time t2 to t3) in step S13. If it is determined in step S12 that all the memory cells MC in the state (10) have passed the verify, the process proceeds to step S28 shown in FIG.

Thereafter, or after the write voltage _{V prg} is increased (step-up) (step S14), and in step S15, the write voltage _{V prg} is, the next lower state threshold after adjustment is (00) write start voltage _{V prg2} more If the write start voltage _Vprg2 is not exceeded, the process returns to step S11, and verify read (time t3 to t4) is performed again.

That is, all states (10) and a memory cell MC is determined to pass the verification, or, until the write voltage V _prg exceeds or first matches the write start voltage V _prg2, verify read operation (time t1 To t2, times t3 to t4) and the writing operation (times t2 to t3) are repeated (see steps S11 to S15 in FIG. 7).

In addition, the write voltage V _prg applied to the word line WL in each write operation is a value that is increased by V _step (step-up width) than the voltage applied to the word line WL in the immediately previous write operation. The increasing voltage V _step may be a constant value or may not be a constant value. For example, the write voltage V _prg applied to the word line WL at time t2 to t3 is V _prg1 + V _step . In the following description, V _step is assumed to be a constant value.

Then, while the verify read operation and the write operation to the memory cell MC in the state (10) are repeated, the write voltage V _prg applied to the word line WL matches the write start voltage V _prg2 , or When it exceeds for the first time (time t5), the verify read in the state (10) and the verify read in the state (00) are sequentially performed (steps S16 and S17 in FIG. 7, times t5 to t6 and t6 to t7 in FIG. 9). . Thereafter, in step S18, it is determined whether or not verification has been passed.

As a result of the verify read, if it is determined in step S18 that all the memory cells MC in the states (10) and (00) have passed the verify, the process proceeds to step S39 shown in FIG. On the other hand, the memory cell MC determined not to pass the verify, that is, the memory cell MC in the state (10) in which the threshold voltage has not reached the verify voltage V _th1 and the threshold voltage reaches the verify voltage V _th2. The memory cells MC that have not reached the state (00) are simultaneously written in step S19 (step S19 in FIG. 7, times t7 to t8 in FIG. 9).

Thereafter, the write voltage _{V prg} is increased (step S20) after the write voltage _{V prg} In step S21, the threshold after adjustment is determined whether the state (01) write start voltage _{V prg3} above, the write start voltage If V _prg3 is not exceeded, the process returns to step S16, and verify read (time t8 to t9, t9 to t10) is performed again.

That is, it is determined that all the memory cells MC in the states (10) and (00) have passed the verify, or the verify read is performed until the write voltage V _prg matches the write start voltage V _prg3 or exceeds for the first time. The operation (time t5 to t6, time t6 to t7, time t8 to t9, time t9 to t10) and the write operation (time t7 to t8, time t10 to t11) are repeated (see steps S16 to S21 in FIG. 7). ).

The write voltage V _prg applied to the word line WL coincides with the write start voltage V _prg3 while the verify read operation and the write operation to the memory cell MC in the states (10) and (00) are repeated. Or when it exceeds for the first time (time t11), the verify read in the state (10), the verify read in the state (00), and the verify read in the state (01) are sequentially performed (step S22 in FIG. 7, S23, S24, times t11 to t12, t12 to t13, t13 to t14 in FIG. 9). Thereafter, in step S25, it is determined whether or not verification has been passed.

As a result of the verify read, if it is determined in step S25 that all of the memory cells MC in the states (10), (00), and (01) have passed the verify, they are connected to the selected word line WL to be written. The threshold adjustment of the memory cell group thus completed is completed. On the other hand, the threshold voltage reaches the memory cell MC determined to not pass verification, that is, the memory cell MC in the state (10) in which the threshold voltage has not reached the verification voltage V _th1 and the verification voltage V _th2. The memory cell MC that is not in the state (00) and the memory cell MC that is in the state (01) in which the threshold voltage has not reached the verify voltage V _th3 are simultaneously written in step S26 (step in FIG. 7). S26, times t14 to t15 in FIG. 9).

Thereafter, after the write voltage _Vprg is increased (step S27), the process returns to step S22, and verify read is performed again (time t15 to t16, t16 to t17, t17 to t18).

  That is, the verify read operation (time t11 to t12, time t12 to t13, time t13 to t14) is performed until it is determined that all the memory cells MC in the states (10), (00), and (01) have passed the verify. , Times t15 to t16, t16 to t17, t17 to t18) and the write operation (times t14 to t15) are repeated (see steps S22 to S27 in FIG. 7).

In step S12 shown in FIG. 7, if all the memory cells MC in the state (10) passes the verification, the process proceeds to step S28 shown in FIG. 8, the write voltage _{V prg} is set to the write start voltage _{V prg2} . Then, verify read is performed on all the memory cells MC in the state (00) after adjustment in the memory cell group connected to the selected word line WL to be written (step S29 in FIG. 8).

As a result of the verify read, the memory cell MC determined to have passed the verify in step S30, that is, the memory cell MC written up to the threshold voltage equal to or higher than the verify voltage _Vth2 is the target of writing in the next write step (step S31). Excluded. On the other hand, as a result of the verify read, the memory cell MC determined not to pass the verify, that is, the memory cell MC whose threshold voltage has not reached the verify voltage _Vth2, is written in step S31. If it is determined in step S30 that all the memory cells MC in the state (00) have passed the verify, the process proceeds to step S39 shown in FIG.

Thereafter, after the write voltage V _prg is increased (step S32), it is _determined in step S33 whether the write voltage V _prg is _{equal to} or higher than the write start voltage V _{prg3 in} the state (01), and does not exceed the write start voltage V _prg3 . In this case, the process returns to step S29, and verify read is performed again.

That is, it is determined that all the memory cells MC in the states (00) and (01) have passed the verify, or the verify read is performed until the write voltage V _prg matches the write start voltage V _prg3 or exceeds for the first time. The operation and the writing operation are repeated (see steps S29 to S33 in FIG. 8). Then, when the verify read operation and the write operation are repeated, when the write voltage V _prg matches or for the first time exceeds the write start voltage V _prg3 , the verify read of the state (00) and the state (01) The verify reading is sequentially performed (steps S34 and S35 in FIG. 8). Thereafter, in step S36, it is determined whether or not verification has been passed.

As a result of the verify read, if it is determined in step S36 that the verify has passed, the threshold adjustment of the memory cell group connected to the selected word line WL to be written is ended. On the other hand, the memory cell MC determined not to pass the verify, that is, the memory cell MC in the state (00) in which the threshold voltage has not reached the verify voltage _Vth2, and the threshold voltage reaches the verify voltage _Vth3. The memory cells MC that have not reached the state (01) are simultaneously written in step S37.

After that, after the write voltage V _prg is increased (step S38), the process returns to step S34, and verify read is performed again (time t15 to t16, t16 to t17, t17 to t18).

  That is, the verify read operation and the write operation are repeated until it is determined that all the memory cells MC in the states (00) and (01) have passed the verify (see steps S34 to S38 in FIG. 8).

Further, when it is determined in step S18 shown in FIG. 7 that all of the memory cells MC in the states (10) and (00) have passed the verification, or in step S30 shown in FIG. 8, the state (00) If it is determined that all the memory cells MC pass the verify, the process proceeds to step 39 in FIG. 8, and the write voltage V _prg is set to the write start voltage V _prg3 . Then, verify read is performed on all of the memory cells MC in the state (01) after adjustment in the memory cell group connected to the selected word line WL to be written (step S40 in FIG. 8).

As a result of the verify read, the memory cell MC determined to have passed the verify in step S41, that is, the memory cell MC written up to the threshold voltage equal to or higher than the verify voltage _Vth3 is the target of writing in the next write operation (step S42). The process is terminated. On the other hand, as a result of the verify read, the memory cell MC determined not to pass the verify, that is, the memory cell MC whose threshold voltage has not reached the verify voltage _Vth3 is written in step S42. After that, after the write voltage V _prg is increased (step S43), the process returns to step S40, and verify read is performed again.

  That is, in step S41, the verify read operation and the write operation are repeated until all the memory cells MC in the state (01) pass the verify (see steps S40 to S43 in FIG. 8).

  Although not explicitly shown in FIGS. 7 to 9, writing and verify reading are performed on the memory cell MC in the state (10), the memory cell MC in the state (00), and the memory cell MC in the state (01). In the repetition, for example, when the memory cell MC in the state (10) in which the write is determined to be insufficient as a result of the verify read or the memory cell MC in the state (00) disappears, the state (01) Writing is performed only to the memory cell MC and the memory cell MC that is in a state (10) where writing is insufficient, or the memory cell MC that is in the state (00). In this case, verify reading corresponding to the state (10) and the state (00) may be omitted.

  In addition, as a result of the verify read, for example, there is no memory cell MC in the state (01) in which the write is determined to be insufficient, and the memory cell MC in the state (10) in which the write is determined to be insufficient, or When the memory cell MC in the state (00) still remains, writing is performed only to the memory cell MC in the state (10) or the memory cell MC in the state (00). In this case, the verify reading corresponding to the state (10) or the state (00) may be omitted.

  That is, finally, all the memory cells MC that are to be in the state (10), the state (00), and the state (01) connected to the selected word line WL to be written are written as a result of the verify read. When it is determined that it is sufficient, the write operation is completed. Note that, for example, when a predetermined write time has elapsed from the start of writing, or when the write voltage is increased (step-up) a predetermined number of times, the write is interrupted on the way because the write has failed. Of course it is also possible.

  Thus, in the present embodiment, the write voltage is applied from the memory cell MC in the low adjustment threshold state (10) to the memory cell MC in the state (00) and from the memory cell MC in the state (01). Increase and write sequentially. Then, when the write voltage is increased and the write operation and the verify read operation are repeated, the write adjustment potential coincides with the write start potential for the memory cell MC in the next adjustment threshold state, for example, the state (00). Then, in addition to the memory cell MC in the state (10) in which the verify read does not pass, the memory cell in the state (00) can be simultaneously processed as a write target, thereby reducing the write time. Can do.

In addition, good writing characteristics of the memory cell MC, before reaching the write start voltage _{V prg2} the high write voltage _{V prg} is the next threshold state (00), when the write state (10) is completed, the write voltage V _The write may be started by setting _prg to the write start voltage _Vprg2 in the state (00). When the write voltage reaches the write start voltage _Vprg3 of the state (01) after the start of the write of the state (00), the write to the state (00) and the state (01) may be performed.

In addition, when the writing characteristics of the memory cell MC are good and the writing of the state (10) and the state (00) is finished before the writing voltage _Vprg reaches the writing start voltage of the state (01) having the next highest threshold value, the write voltage _{V prg} is set to write start voltage _{V prg3} of the state (01), may start writing.

  The multi-value data adjustment method according to this embodiment may be used in combination with the first embodiment and the second embodiment. That is, the multi-value data adjustment method according to this embodiment may be used in the second writing method in the first embodiment and the second writing method in the second embodiment. In the second embodiment, the present embodiment may be applied to both the row verify step and the verify step, or the present embodiment may be applied to any one of them.

  As described above, according to the present embodiment, writing is simultaneously performed on the memory cells MC connected to the selected word line WL to be written and adjusted to a plurality of threshold states, so that the writing time is shortened. Can be achieved.

  In this embodiment, the adjustment threshold is gradually increased from the state (10) where the adjustment threshold is low. However, as a modification of the present embodiment, the following multi-value data adjustment method may be used.

(Modification 1)
First, the threshold adjustment for the memory cell in the state (01) is completed by repeatedly performing the write step and the verify step for the memory cell MC in the state (01) having the highest adjustment threshold. Thereafter, as in the present embodiment, the write operation and the verify read operation are repeated from the state (10) with the lowest adjustment threshold.

When the write voltage V _prg coincides with the write start potential V _{prg2 in} the state (00) that is the next adjustment threshold, the state (in addition to the memory cell MC in the state (10) in which the verify read is not passed) The write operation and the verify read operation are repeated for the memory cell MC that becomes 00).

  This repetition is repeated until there are no more memory cells MC in the state (10) where the verify read is not passed. Thereafter, the write operation and the verify read operation are repeated for the memory cell MC in the state (00).

  The multi-value data adjustment method according to this modification can shorten the writing time as in the present embodiment. In this modification, first, a memory cell MC that is in a state (01) with a high adjustment threshold is subjected to threshold adjustment to form a desired distribution, and then a memory that is in another adjustment threshold state. Since the threshold adjustment is performed on the cell MC, the adjacent effect received by the memory cell MC in the states (10) and (00) can be suppressed.

(Fourth embodiment)
Next, a multi-value data adjustment method of the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 10 is a flowchart showing the procedure of the multi-value data adjustment method of this embodiment. This embodiment can be applied to, for example, the NOR flash memory 100 shown in the first embodiment.

  The multi-value data adjustment method according to the present embodiment is a multi-value data adjustment method when an interruption operation (suspend operation) occurs during a write operation in the first embodiment and the second embodiment. In the present embodiment, for example, the suspend command is entered by the suspend command input from the external command bus, the write operation is interrupted, the read operation is executed, and the suspend command is input by the resume command input from the external command bus. A nonvolatile semiconductor memory device having a function of returning from a state is assumed.

  First, as shown in step S50 of FIG. 10, writing is performed on each memory cell MC that is in any of the states (10), (00), and (01) after adjustment. When a suspend command is input during the writing (step S51), the writing operation is immediately stopped even before the threshold adjustment of the memory cell MC being written is completed.

  Then, it is determined whether the writing is performed by the first writing method or the second writing method (step S52). If the second writing method is accompanied by verify reading, the interruption is interrupted. After returning from (after resume), verify read is performed (step S53).

  Thereafter, referring to the verify read result, it is determined whether or not the threshold adjustment of the write target memory cell MC, which has been interrupted in accordance with the input of the suspend command, has been completed (step S54), and has not been completed. In this case, the process returns to step S50 to perform additional writing.

  In step S52, in the case of the first writing method that does not involve verify reading, after returning from the interruption (after resume), the write address is incremented (step S56), and then the process returns to step S50 to perform the write operation. Do. As described above, in the case of the first writing method without verify reading, in order to prevent overwriting after resuming, rewriting to the memory cell MC at the same address is not performed, and writing to the memory cell MC at the next address is started. To do.

  If no suspend command is input during writing, the process proceeds to step S55 after writing, and it is determined whether or not the writing is based on the second writing method (step S55). In the case of the first writing method that does not involve verify reading, the write address is incremented and the process returns to step S50 to execute writing.

  In step 55, in the case of the second writing method with verify read, the process proceeds to step S53, and verify read is performed. As described above, in the case of the second write method with verify read, in order to prevent overwriting after resuming, the verify read for the memory cell MC at the same address is started, and then the write is executed.

  As described above, in the present embodiment, in order to prevent overwriting, even before the threshold adjustment of the memory cell MC being written is completed, the write operation is immediately stopped and the second write accompanied by verification is performed. In the case of the method, overwriting is prevented by performing the verify reading after returning from the interruption (after resume), and the subsequent threshold distribution is guaranteed. Further, in the case of the first writing method not accompanied with verify reading, overwriting is prevented by starting from writing to the memory cell MC at the next address without performing rewriting to the memory cell MC at the same address after resume. And guarantees the subsequent threshold distribution.

  It should be noted that the present embodiment can be similarly applied to the case where the first embodiment, the second embodiment, and the third embodiment are combined.

(Fifth embodiment)
Next, a multi-value data adjustment method for a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention will be described with reference to FIGS. 11 to 12B. FIG. 11 is a flowchart showing the procedure of the multi-value data adjustment method of the present embodiment, and FIGS. 12A and 12B are schematic diagrams for explaining the multi-value data adjustment method of the present embodiment. This embodiment can be applied to, for example, the NOR flash memory 100 shown in the first embodiment.

  Hereinafter, a memory cell MC to be written (electron injection) is referred to as a selected memory cell, a word line WL to which the selected memory cell is connected is referred to as a selected word line, and a bit line BL to which the selected memory cell is connected is referred to as a selected bit line. The memory cells MC other than the selected memory cell may be referred to as non-selected memory cells, the word lines WL other than the selected word line may be referred to as non-selected word lines, and the bit lines BL other than the selected bit line may be referred to as non-selected bit lines BL.

  In the case of a NOR flash memory, the write characteristics of the memory cell MC to be written to deteriorate due to a leak current flowing through unselected memory cells on the same bit line BL during writing, and the writing time increases.

Therefore, as shown in FIG. 12A, a method is adopted in which the voltage of the word line WL of the unselected memory cell is lowered to the negative side (for example, −1 V) to suppress the leakage current. However, when the write voltage V _prg (for example, + 9V) applied to the word line WL connected to the selected memory cell is high, the memory cell MC or the peripheral element is determined by the difference between the negative potential and the positive potential (for example, 10V). There is a possibility that an event exceeding the pressure resistance of the The above-described negative voltage applied to the unselected word line at the time of writing is hereinafter referred to as a control voltage V _reg .

In the present embodiment, as shown in FIG. 12B, while the multi-value distribution is being formed as in the third embodiment, the write voltage V _prg of the word line WL does not exceed the specified value. Decreases the control voltage V _reg to a lower value (for example, −3 V), and increases the number of batch write memory cells from, for example, 16 bits (1 word) to 64 bits (4 words).

In the middle of performing writing by increasing the write voltage _Vprg , the control voltage _Vreg is returned when the write voltage _Vprg becomes equal to or higher than a specified value (for example, -1V as shown in FIG. 12A). The write time can be shortened by returning the number of batch write memory cells from, for example, 64 bits (4 words) to 16 bits (1 word). Here, the specified value for changing (switching) the number of batch write memory cells may be appropriately determined in consideration of the breakdown voltage of the memory cell MC or the peripheral element, the allowable leakage current, and the like.

  In the multi-value data adjustment method of the present embodiment, first, as shown in step S60 of FIG. 11, for example, after 16-bit batch writing is performed, verify reading is performed (step S61). Then, as a result of the verify read, it is determined whether or not the writing of all the 16-bit memory cells MC has been completed (step S62). If it is determined that the writing has been completed, the adjustment operation is terminated.

As a result of the verify read, if there is a memory cell MC that does not reach the target threshold value _Vth and the write operation is not completed, the process proceeds to step S63 and the write voltage _Vprg (that is, the voltage applied to the word line WL) is set to _Vstep (step up). Width) increase.

Then, in step S64, it is determined whether or not the withstand voltage of the memory cell MC into which data is written with respect to the write voltage _Vprg has a margin (whether or not the write voltage _Vprg is equal to or higher than a specified value). If not, batch writing (that is, 16-bit batch writing) is performed on the 16 memory cells MC connected to the selected word line WL (step S65). The voltage of the word line WL of the memory cell MC is lowered, and batch writing (that is, 64-bit batch writing) is performed on the 64 memory cells MC connected to the selected word line WL (step S66).

  When the batch writing is completed, the process proceeds to step S67. If the current address is not the last address, the process returns to step S61 to perform verify reading. If it is the last address, 1 is added to the current address and the process returns to step S60 to repeat the above-described operation.

  As described above, according to the present embodiment, the voltage applied to the word line WL can be reduced by lowering the negative voltage and increasing the number of memory cells for batch writing in a range where no breakdown of the breakdown voltage occurs. Time can be shortened. Note that this embodiment can also be applied in combination with the first to fourth embodiments described above.

(Sixth embodiment)
Next, a multi-value data adjustment method for a nonvolatile semiconductor memory device according to a sixth embodiment of the present invention will be described. This embodiment can be applied to, for example, the NOR flash memory 100 shown in the first embodiment.

In the multi-value data adjustment method of this embodiment, when a multi-value distribution is formed as in the first embodiment or the second embodiment, the write voltage V _prg applied to the selected word line WL is _made relatively high. When adjusting the multi-value data of the memory cell MC that is in the low threshold state (10), (00), the control voltage V _reg applied to the word line WL of the non-selected memory cell is further lowered, This is done by increasing the number of batch write memory cells and returning the negative voltage to reduce the number of batch write memory cells when adjusting the memory cells MC that are in the high threshold state (01). Thereby, the writing time can be shortened. Note that this embodiment can also be applied in combination with the first to fourth embodiments described above.

(Application example)
Hereinafter, an example in which the NOR flash memory 100 having the above configuration and function is mounted on a semiconductor chip will be described. Note that the control methods described in the first to sixth embodiments can be applied to the NOR flash memory 100 according to the application example.

  FIG. 17 is a cross-sectional view showing an example of a semiconductor chip (multi-chip package: MCP) 1000 including the NOR type flash memory 100 according to the first embodiment which is an aspect of the present invention. .

  As shown in FIG. 17, a semiconductor chip 1000 includes a NAND flash memory 1002, a spacer 1003, a NOR flash memory 100, a spacer 1004, a PSRAM (Pseudo Static Random Access Memory) 1005, and a controller, which are sequentially stacked on a substrate 1001. 1006 is mounted in the same package.

  The NAND flash memory 1002 has, for example, a plurality of memory cells that can store multi-value data. Further, the semiconductor chip 1000 may be configured to use SDRAM (Synchronous Dynamic Random Access Memory) instead of PSRAM.

  Among the above memories, the NAND flash memory 1002 is used as a data storage memory, for example, depending on the use by the memory system. The NOR flash memory 100 is used as a program storage memory, for example. The PSRAM 1005 is used as a work memory, for example.

  The controller 1006 mainly performs data input / output control and data management for the NAND flash memory 1002. The controller 1006 includes an ECC correction circuit (not shown), adds an error correction code (ECC) when writing data, and analyzes and processes the error correction code when reading data.

  The NAND flash memory 1002, the NOR flash memory 100, the PSRAM 1005, and the controller 1006 are bonded to the substrate 1001 with wires 1007.

  Each solder ball 1008 provided on the back surface of the substrate 1001 is electrically connected to a wire 1007. As the package shape, for example, a surface mount type BGA (Ball Grid Array) in which each solder ball 1008 is two-dimensionally arranged is adopted.

  Next, a case where the semiconductor chip 1000 is applied to a mobile phone which is an example of an electronic device will be described.

  FIG. 18 is a diagram showing a mobile phone in which the semiconductor chip 1000 is mounted. As shown in FIG. 18, the mobile phone 2000 includes a main body upper part 2002 having a main screen 2001 and a main body lower part 2004 having a keypad 2003. The mobile phone 2000 is equipped with a semiconductor chip 1000.

  A CPU (not shown) mounted on the mobile phone 2000 accesses the semiconductor chip 1000 via an interface (not shown) and transfers data and the like. The cellular phone 2000 uses, for example, the NAND flash memory 1002 as a user data storage area and the NOR flash memory 100 as a program storage area such as firmware.

  In such a memory system, the NOR flash memory 100 is required to perform a high-speed write operation. On the other hand, the amount of program data to be stored is increasing as the application software becomes more sophisticated.

  The NOR flash memory 100 according to the first embodiment, which is an aspect of the present invention, includes memory cells capable of holding multi-value data, and shortens the write time using the threshold adjustment method described above, thereby It is possible to solve the problem.

  The semiconductor chip 1000 can be applied to various electronic devices such as a personal computer, a digital still camera, and a PDA in addition to the mobile phone.

1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment. The schematic diagram which shows the threshold value distribution of the memory cell which can memorize | store multi-value data of 1st Embodiment. The flowchart which shows the procedure of the multi-value data adjustment method of 1st Embodiment. The schematic diagram which shows the threshold value distribution of the memory cell after each procedure of the multi-value data adjustment method of 1st Embodiment. The flowchart which shows the procedure of the multi-value data adjustment method of 2nd Embodiment. The schematic diagram which shows the threshold value distribution of the memory cell after each procedure of the multi-value data adjustment method of 2nd Embodiment. The flowchart which shows the procedure of the multi-value data adjustment method of 3rd Embodiment. The flowchart which shows the procedure of the multi-value data adjustment method of 3rd Embodiment. FIG. 10 is a voltage waveform diagram applied to a word line in the multi-value data adjustment method according to the third embodiment. The flowchart which shows the procedure of the multi-value data adjustment method of 4th Embodiment. The flowchart which shows the procedure of the multi-value data adjustment method of 5th Embodiment. The figure explaining the multi-value data adjustment method of 5th Embodiment. The figure which shows the structure of the 1st example of a general NOR type flash memory. The figure which shows the structure of the 2nd example of a general NOR type flash memory. The schematic diagram explaining the generation | occurrence | production factor of the adjacent effect of a general flash memory. The top view explaining the influence range of the adjacent effect of a general NOR type flash memory. Sectional drawing which shows the structure of the semiconductor chip provided with the non-volatile semiconductor memory device by 1st Embodiment. The schematic diagram which shows the mobile telephone which stores the semiconductor chip provided with the non-volatile semiconductor memory device by 1st Embodiment.

Explanation of symbols

MC memory cell S source region D drain region SL source line FG floating gate CG control gate BC bit line contact BL bit line WL word line 100 NOR type flash memory 101 address latch 102 address counter 103 address buffer 104 I / O buffer 105 data latch 106 memory cell array 107 read sense amplifier circuit 108 column gate circuit 109 page buffer 110 multi-value compression circuit 111 write circuit 112 verify sense amplifier circuit 113 command register 114 internal controller 115 row decoder 116 column decoder 118 regulator circuit 1000 semiconductor chip 1001 substrate 1002 NAND flash memory 1003, 1004 Spacer 1005 PSRAM
1006 Controller 1007 Wire 1008 Solder ball 2000 Mobile phone 2001 Main screen 2002 Main body upper part 2003 Keypad 2004 Lower main body

Claims (5)

For the memory cell having a memory cell capable of holding a multi-valued state by adjusting a threshold voltage and a word line commonly connected to the plurality of memory cells and adjusted to a state other than an erased state A threshold control method for a non-volatile semiconductor memory device that performs verify reading and performs writing by increasing a write voltage applied to the word line to the memory cell that has not reached a target threshold value,
The write voltage applied to the word line at the time of writing to the first memory cell adjusted to the first target threshold is adjusted to the second target threshold having the second highest threshold voltage after the first target threshold. When the voltage exceeds the write start voltage of the second memory cell, the first memory cell and the second memory cell connected to the word line in common with the first memory cell , Writing simultaneously,
A method for controlling a threshold value of a nonvolatile semiconductor memory device, comprising: After adjusting the threshold distribution of the third memory cell adjusted to the third target threshold value having the highest threshold voltage, the first memory cell connected to the word line in common with the third memory cell A write step of adjusting the threshold distribution of the second memory cell connected to the word line common to the third memory cell after adjusting the threshold distribution and adjusting the threshold distribution of the first memory cell. ,
The threshold value control method for a nonvolatile semiconductor memory device according to claim 1, further comprising: The first memory cell and the second memory cell when a write voltage applied to the word line at the time of writing to the first memory cell is equal to or higher than a write start voltage of the second memory cell. The first memory cell determined to have not reached the first target threshold and the second memory cell determined to have not reached the second target threshold In contrast, the step of performing writing by increasing the write voltage applied to the word line
The threshold value control method for a nonvolatile semiconductor memory device according to claim 1, further comprising: When the write voltage is lower than a specified value, a step of collectively writing to the first predetermined number of the memory cells in a state where a first negative voltage is applied to the unselected word lines; ,
When the write voltage is greater than or equal to the specified value, the second negative voltage higher than the first negative voltage is applied to the unselected word lines, and the write voltage is smaller than the first predetermined number. Performing batch writing on a second predetermined number of the memory cells;
The threshold value control method for a nonvolatile semiconductor memory device according to claim 1, further comprising: When adjusting the threshold distribution of the first memory cell and the second memory cell, a first negative voltage is applied to the non-selected word lines and a first predetermined number of the memory cells are applied. A step of writing in batches,
When adjusting the threshold distribution of the third memory cell, the second negative voltage higher than the first negative voltage is applied to the unselected word line, and the threshold value distribution is higher than the first predetermined number. Writing to the small second predetermined number of the memory cells at once;
The threshold value control method for a nonvolatile semiconductor memory device according to claim 3, further comprising:

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