JP2009118155A - Slave node, image forming apparatus, and method of setting slave address - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a slave node which can set and change the address or perform other address management easily even if a common node is used as the slave node. <P>SOLUTION: Slave nodes 90 (90a, 90b, ...) connected to a bus formed serial communication system equipped with at least one master node 9 are each equipped with: an address generating portion 92 (92a, 92b, ...) for setting the slave address of itself based on the value of analog voltage input into the external input terminal; a step-down circuit 93 (93a, 93b, ...) which steps down the analog voltage input into the external input terminal and outputs the stepped-down analog voltage to the external output terminal; and an address conversion table 94 (94a, 94b, ...) which is provided in the address generating section 92 and converts the analog voltage value into the slave address. The external output terminal can be connected to external input terminals of other slave nodes. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a slave node connected to a bus serial communication system including at least one master node, an image forming apparatus equipped with the slave node, and a slave node address setting method for the slave node.

  In order to control an image forming apparatus such as a copying machine, if a single control unit with a high-performance CPU is provided and each unit is controlled by the control unit, the operation program of the control unit is very In addition, the program development period becomes longer and the cost of the CPU increases because the CPU is expensive.

  Therefore, a plurality of control units equipped with inexpensive CPUs are connected via a serial communication line, and each control unit uses a distributed control system that controls controlled units such as an image reading unit and an image forming unit. There are many devices. In this case, the program executed by each control unit is simplified, the development period of the program can be shortened, and an increase in the manufacturing cost and component cost of the apparatus can be suppressed. The distributed control system is frequently used in many apparatuses other than the image forming apparatus.

  One of the communication systems employed in such a distributed control system is a bus type serial in which a master node and a plurality of slave nodes are connected via a serial bus, and the master node polls each slave node for communication. There is a communication system.

  In the bus type serial communication system, each slave node is given a unique slave address in advance, the master node specifies the slave address, selects a slave node that allows communication, communicates with the selected slave node, When communication is completed, the master node specifies the slave address of another slave node, permits communication to the other slave node, and communicates with the slave node. Based on such a communication protocol, the master node and each slave node execute control of the entire system while communicating with each other.

  As described in Patent Document 1, conventionally, the address of each slave node is pulled up to each slave node via a dip switch or a resistor through a plurality of address setting terminals for address setting corresponding to the number of digits of the address. Alternatively, it is set by pulling down or stored in advance in a ROM or the like provided in each slave node.

  In the former case, in addition to the input / output terminals for serial communication, a large number of address setting terminals are required, resulting in an increase in cost. In the latter case, there is a problem that the flexibility is insufficient. The following address setting methods have been proposed.

That is, the first to Nth main serial buses connected to the first to Nth slave nodes are separated by the first to (N-1) th node control circuits, and the bus type serial communication system is initially powered on. By doing so, the first to Nth slave nodes and the first to (N-1) th node control circuits are power-on reset, and only the first slave node and the first node control circuit are the first. The control master node is electrically connected to the control master node via the main serial bus, and the control master node sequentially stores the first to Nth address information for the first to Nth slave nodes on the first main serial bus. When the first to (N-1) th node control circuits receive the first to (N-1) th address information, respectively, the respective inputs and outputs are electrically connected. Connect The second to Nth slave nodes are sequentially connected to the control master node, and after the power-on reset, the first to Nth slave nodes set the address information received first as their own addresses. This is an address setting method in which the first to Nth address information is set as its own address in the first to Nth slave nodes, respectively.
Japanese Patent Laid-Open No. 5-292298

  In the conventional technique described in Patent Document 1, when it is necessary to change the address of the slave node once set, it is necessary to replace the corresponding address data with the ROM or to set the dip switch again. Management of address change settings and the like is very complicated. Furthermore, since it is necessary to individually set the slave address, there is a problem that it is difficult to configure a plurality of slave nodes using a device having a common hardware and software.

  On the other hand, in the address setting method proposed in Patent Document 1, it is necessary to provide a plurality of node control circuits, which may lead to an increase in cost and a decrease in reliability due to an increase in the size of a substrate, an increase in mounted components, and the like. There is also a problem that the time until all slave addresses are set after power-on is long.

  In view of the above problems, an object of the present invention is to provide a slave node that can easily manage address settings and changes while using a common device as a slave node, and an image forming apparatus equipped with the slave node, And it is in providing the address setting method of the slave node.

  In order to achieve the above object, a first characteristic configuration of a slave node according to the present invention is a bus type serial communication system including at least one master node as described in claim 1 of the claims. A slave node to be connected is provided with an address generation unit that sets its own slave address based on an analog voltage value input to the external input terminal.

  According to the above configuration, since the slave address is set by the address generator based on the analog voltage value input to the external input terminal, an individual circuit or ROM for address setting is provided on the slave node side. Even if it is not provided, it is very easy to set or change each slave node to a unique address by appropriately managing the analog voltage value input to the external input terminal. As a result, a plurality of slave nodes can be configured in common.

  In the second feature configuration, as described in claim 2, in addition to the first feature configuration described above, a step-down operation is performed to step down an analog voltage value input to the external input terminal and output the voltage to an external output terminal. A circuit is provided, and the external output terminal and an external input terminal of another slave node are configured to be connectable.

  According to the above configuration, since the analog voltage input to the external input terminal is stepped down by the step-down circuit and input to the external input terminal of the next slave node, the voltage for address setting of each slave node is individually set. A unique address is set by each address generation unit in each slave node to which different voltages are sequentially input without the need for adjustment.

  In addition to the first or second feature configuration described above, the third feature configuration includes an address conversion table for converting the analog voltage value into the slave address in the address generation unit. It is in the point to have.

  According to the above configuration, the address generation unit can set an address corresponding to the input analog voltage value with reference to the address conversion table.

  The characteristic configuration of the image forming apparatus according to the present invention is that, as described in claim 4, a plurality of slave nodes according to any one of claims 1 to 3 are connected to a bus type serial communication system including at least one master node. Each slave node is configured to control the controlled unit based on a command from the master node.

  According to the configuration described above, the control of the controlled part is executed in a distributed manner under the instruction of the master node by each slave node in which a unique address is set based on the analog voltage value input to the external input terminal. Is done.

  The characteristic configuration of the slave address setting method according to the present invention is a slave address setting method for a slave node connected to a bus type serial communication system having at least one master node, as described in claim 5, The slave address is set based on the analog voltage value input to the input terminal.

  According to the above-described configuration, the address of each slave node can be easily set or managed by appropriately setting the analog voltage value input to the external input terminal.

  As described above, according to the present invention, while using a common device as a slave node, a slave node that can easily manage address settings, changes, and the like, an image forming apparatus equipped with the slave node, and The slave node address setting method can be provided.

  A communication system using a slave node in the present invention will be described below.

  As shown in FIG. 1, a plurality of slave nodes 90 (90a, 90b,...) Are connected to a master node 9 via a serial bus 8 to constitute a bus type serial communication system.

  The serial bus 8 includes a bidirectional data line 80 for transmitting serial data transmitted and received between the master node 9 and each slave node 90 and a clock signal line 81 for transmitting a clock signal transmitted from the master node 9. Has been.

  Each slave node 90 (90a, 90b,...) Is composed of devices having common hardware and software. Hereinafter, the slave node 90a will be described as an example. The slave node 90a includes a serial communication unit 91a that performs serial communication with the master node 9 via the serial bus 8, and an address generation unit 92a that sets its own slave address based on the analog voltage value input to the external input terminal. I have.

  As shown in FIG. 2A, the address generation unit 92a includes an address conversion table 94a that converts a detected analog voltage value into a slave address, and is input to an external input terminal with reference to the address conversion table 94a. Set its own address based on the analog voltage value.

  The address generation unit 92a also includes a step-down circuit 93a that steps down the analog voltage value input to the external input terminal using a voltage dividing resistor and outputs the voltage to the external output terminal. The external output terminal and the external input terminal of another slave node Is configured to be connectable. In the present embodiment, an external output terminal of a certain slave node is configured to be connected to an external input terminal of an adjacent slave node, and an external output terminal of the slave node 90a is connected to an external input terminal of the slave node 90b. ing.

  Therefore, the analog voltage value Va1 input from the external output terminal of the master node 9 to the external input terminal of the slave node 90a is stepped down by the step-down circuit 93a, and the analog voltage value Va2 is input to the external input terminal of the slave node 90b. In this way, different analog voltage values are input to the external input terminals of each slave node 90, and each address generation unit 92 sets a unique address to each slave node.

  The master node 9 includes a slave attribute table 900 in which the address of each slave node 90 is set, designates an address with reference to the slave attribute table 900, and performs serial communication with each slave node 90 by a polling method.

  As shown in FIG. 2 (b), the slave attribute table 900 controls the role that each slave node 90 plays in the communication system (for example, when a slave node is a control device that controls a controlled unit, which control device is controlled). Table data in which an address corresponding to a slave attribute indicating whether or not to be set is set.

  As shown in FIG. 3A, a header is added to data transmitted / received between the master node 9 and each slave node 90 via the data line 80, and the address of the destination node is set in the header. The

  As shown in FIG. 3B, the data is transmitted / received via the data line 80 in synchronization with the clock signal transmitted through the clock signal line 81. The transmitting node transmits data in synchronization with the rising edge of the clock signal, and the receiving node receives data in synchronization with the falling edge of the clock signal.

  The data transmission / reception between the master node 9 and the slave node 90 will be described by taking the data transmission / reception between the master node 9 and the slave node 90a as an example. As shown in FIG. Referring to this, “transmission confirmation” data in which the address of the slave node 90 a is set in the header is transmitted to the serial bus 8. Each slave node 90 confirms the address set in the header of the “transmission confirmation data” received via the serial bus 8 and discards it if its own address is not set.

  The slave node 90a in which its own address is set in the header of “transmission confirmation data” transmits “response data” to the serial bus 8, and when there is data to be transmitted thereafter, within a predetermined time set in advance. The data is transmitted to the serial bus 8. When the predetermined time elapses, the master node 9 transmits “completion confirmation data” in which the address of the slave node 90 a is set in the header to the serial bus 8. Thereby, the data transmission / reception between the master node 9 and the slave node 90a is completed.

  When communication with the slave node 90a is completed, the master node 9 transmits “transmission confirmation data” in which the address of the slave node 90b is set in the header, starts communication with the slave node 90b, and repeats the above procedure. Thus, data transmission / reception between the master node 9 and the slave node 90 is performed.

  As shown in FIG. 4, the slave node 90a includes a microcomputer 95a in which a serial communication unit 91a is incorporated, and peripheral circuits such as a step-down circuit 93a, a reference voltage generation circuit 99a, and an input / output interface circuit.

  The microcomputer 95a includes a CPU 96a, a ROM storing an operation program for the CPU 96a, a RAM serving as a work area, a serial bus 8, and a communication control unit 97a that performs serial communication with the master node 9, and an external input terminal. An A / D port 98a and the like are provided which are obtained by A / D converting the analog voltage value input to, and input to the CPU 96a.

  The microcomputer 95a executes an operation program stored in the ROM, operates according to a prescribed algorithm, sets its own address, and executes serial communication with the master node 9.

  The A / D port 98a acquires the value of the analog voltage input to the external input terminal based on the reference voltage Vref supplied from the reference voltage generation circuit 99a.

  Here, each slave node 90 is provided with a common reference voltage generation circuit 98 so that the same reference voltage Vref is input, and A / D conversion by the A / D port 98 provided in each slave node 90 is performed. The value is configured so that there is no error.

  The CPU 96a refers to the address conversion table 94a stored in the ROM, and stores the address “r” corresponding to the analog voltage value Va1 input from the A / D port 98a in the RAM as its own address (node address). .

  That is, the address generator 92a of the slave node 90a is configured by the operation program stored in the ROM, the address conversion table 94a, the CPU 96a that executes the program, and the A / D port 98a.

  The communication control unit 97a sets the data input via the serial bus 8 in the reception buffer and interrupts the CPU 96a. The CPU 96a confirms the address set in the header of the data in the reception buffer by the interrupt, fetches the data if it matches the own address “r” stored in the RAM, and discards it if it does not match.

  The CPU 96a sets data to be transmitted in the transmission buffer, and outputs a transmission command to the communication control unit 97a. The communication control unit 97a transmits the data set in the transmission buffer by the command to the serial bus 8.

  That is, the serial communication unit 91a is configured by the operation program stored in the ROM, the CPU 96a that executes the program, the communication control unit 97a, the transmission buffer, and the reception buffer.

  Hereinafter, the address setting method of the slave node 90a will be described with reference to the flowchart shown in FIG.

  When the slave node 90a is powered on, the CPU 96a executes an operation program to execute initialization such as initialization of the RAM and port setting such as an input / output port (S1 to S3).

  The CPU 96a acquires the analog voltage value Va1 input to the external input terminal via the A / D port 98a, refers to the address conversion table 94a stored in the ROM, and addresses “ r ”is set as its own address and stored in the RAM (S4 to S6).

  Here, the address conversion table 94a is not provided in the ROM of the slave node 90a, but may be transmitted from the master node 9 to the slave node 90a via the serial bus 8 and stored in the RAM. .

  Specifically, for example, node addresses that can be received by all slave nodes 90 (90a, 90b,...) Are set in advance, and the master node 9 adds a header that sets the node addresses. The address translation table 94 is transmitted by broadcast, and the slave node 90a stores the address translation table 94 received via the serial bus 8 in the RAM as the address translation table 94a.

  In this case, since it is not necessary to previously provide the address conversion table 94a in the ROM at the slave node 90a, the degree of freedom of the address set by the address generation unit 92a is increased, and the versatility of the slave node 90a is increased.

  The master node 9 includes the slave attribute table 900 in which addresses corresponding to the slave attributes of each slave node 90 are set. However, the master node 9 does not include the slave attribute table 900 and is turned on when the communication system is turned on. The slave attribute table 900 may be inquired of each slave node 90 via the serial bus 8 to generate a table corresponding to the slave attribute table 900.

  Specifically, for example, when the slave node 90 is a control device that controls a controlled unit, the controlled unit includes a port that outputs a unique signal, and each slave node 90 is a controlled device that is a control target. By acquiring the slave attribute by receiving the signal from the control unit, the slave attribute can be acquired even when the slave node 90 is configured by a common device. Can do.

  In this case, for example, when there are four controlled units, a specific signal can be output from the controlled unit by using two ports. In addition, instead of a port that outputs a unique signal, a ROM that stores a unique code is provided in the controlled unit, and a slave node can acquire its own slave attribute by referring to the ROM. May be.

  Hereinafter, an embodiment of an image forming apparatus equipped with the above-described communication system will be described using a color digital copying machine as an example.

  As shown in FIG. 6, a tandem color digital copying machine 100 adopting an electrophotographic system has an operation unit 200 that is a man-machine interface with an operator, and an image that reads a document image from a document as image data by photoelectric conversion. A reading unit 300 and an image forming unit that forms a toner image based on the image data read by the image reading unit 300, transfers the toner image onto a sheet conveyed from the sheet cassette 430 (431 to 434), and performs a fixing process. 400 includes functional blocks such as 400, and the operation of each functional block is controlled by a corresponding control unit.

  A plurality of the slave nodes 90 described above are arranged in the image forming unit 400 as the development control unit 50 and are controlled by the engine controller 5 which is a master node. Each development control unit 50 (50a, 50b, 50c, 50d) is connected to the engine controller 5 via the serial bus 6 to constitute a bus type serial communication system. The engine controller 5 includes the development control unit 50 and the like. The image forming unit 400 is controlled in an integrated manner.

  As illustrated in FIG. 7, the image forming unit 400 includes four image forming units 4 (4 a to 4 d) that form toner images of four colors by forming toner images of any color of YMCK. Prepare. The hardware of the image forming unit 4 (4a to 4d) is the same. The hardware configuration of the image forming unit 4 will be described by taking the image forming unit 4a as an example.

  The image forming unit 4a is arranged in order around the image carrier 41a, a charging member 42a arranged in contact with the image carrier 41a to charge the image carrier 41a, and a charged image carrier. A print head 43a that exposes the body 41a to form an electrostatic latent image; a developing unit 44a that visualizes the toner image by electrostatically attaching toner to the electrostatic latent image formed on the image carrier 41a; A cleaner 45a that removes and collects toner remaining on the image carrier 41a, and a static elimination lamp 46a that lowers the residual potential of the image carrier 41a and makes it uniform.

  The developing unit 44a includes a developing roller that electrostatically attaches toner to the electrostatic latent image on the image carrier 41, and the developing roller is rotationally driven by a driving motor. The developing unit 44a includes a toner sensor that detects the toner concentration, and toner is supplied from a toner cartridge (not shown) to the developing unit 44a based on the toner concentration detected by the toner sensor.

  The rotational drive control of the drive motor and the toner detection of the toner sensor are controlled by the corresponding development control units 50 (50a, 50b, 50c, 50d). Since each control target is the same device and the control operation is common, each development control unit 50 is configured by a common device that operates based on a common operation program.

  The development control unit 50a will be described as an example. As shown in FIG. 8, the development control unit 50a is based on a microcomputer 53a, a step-down circuit 54a including a resistor R540a as a peripheral circuit, and a control signal from the microcomputer 53a. A motor drive circuit 71a for rotationally driving the drive motor, and a sensor signal input circuit 70a for inputting a toner concentration detection signal input from the toner sensor to the microcomputer 53a. That is, the development control unit 50a is a slave node of the present invention. The development control unit 50a includes a serial communication unit 55a and an address generation unit 56a.

  When the color digital copying machine 100 is turned on, the analog voltage value Va1 is input from the engine controller 5 through the resistor R51 to the external input terminal of the development controller 50a. As shown in FIG. 9A, the address generation unit 56a refers to an address conversion table 57a in which an analog voltage value and an address corresponding to the voltage value are set, based on the analog voltage value Va1. Set the address. The analog voltage value Va1 is stepped down by the step-down circuit 54a and output from the external output terminal, and the analog voltage value Va2 is input to the external input terminal of the development control unit 50b.

  Similarly, in the other development control units 50b, 50c, and 50d, the address generation conversion tables 57b, 57c, and 57d are referred to by the respective address generation units 56b, 56c, and 56d, and analog input to the respective external input terminals. A unique address is set based on the voltage values Va2, Va3, and Va4.

  As shown in FIG. 9B, the engine controller 5 selects an address set in each development control unit 50 and a color of toner included in the image forming unit 4 corresponding to the development control unit 50 in which the address is set. A slave attribute table 500 is provided as a slave attribute. Therefore, the engine controller 5 can communicate with each development control unit 50 by designating an address with reference to the slave attribute table 500.

  Another embodiment will be described below.

  In the above-described embodiment, the color digital copying machine 100 uses the four development control units that perform the rotational drive control of the driving motor of the developing unit 44 of each image forming unit 4 and the toner detection of the toner sensor as slave nodes of the present invention. Although described as being provided, as shown in FIG. 10, four image forming unit control units 40 (40a to 40d) that uniquely control the corresponding image forming unit 4 are provided as slave nodes of the present invention. Also good.

  In the above-described embodiment, the engine controller 5 that is a master node constitutes a bus type serial communication system with the development control unit 50 that is a slave node, but for example, the paper cassette 430 (431 of the color digital copying machine 100). 11 to 434) are provided with the paper feed control unit 70 (70a to 70d), and the paper feed control unit 70 is configured to manage the presence / absence of paper in each paper cassette 430 and the paper type, etc. As shown in a), the engine controller 5 includes functional blocks of an image formation control unit 5a that performs overall control of the image forming unit and a conveyance control unit 5b that performs overall control of paper conveyance from the paper cassette 430 (431 to 434). Each functional block functions as a master node, and the image formation control unit 5a communicates with the development control unit 50 by bus type serial communication. With constituting the stem, with the same serial bus, or may be transport control unit 5b constitute the bus-type serial communication system and the feed control unit 70.

  In this case, as shown in FIG. 12A, each development control unit 50 and each paper feed control unit 70 have an address conversion table 57 (in which an analog voltage value and an address corresponding to the voltage value are set). 77), as shown in FIG. 12B, the engine controller 5 has a unique address set in each development control unit 50 and each paper feed control unit 70, and development control in which the address is set. By providing the slave attribute table 500 in which the slave attribute of the unit 50 or the paper feed controller 70 is set, the engine controller 5, each development controller 50, and each paper feed controller 70 can communicate.

  Here, in FIG. 12B, regarding the development control unit 50, the toner color included in the image forming unit 4 corresponding to the development control unit 50 is set as a slave attribute, and regarding the paper feed control unit 70, the paper feed control unit. The number of steps from the top of the paper cassette 430 corresponding to 70 is the slave attribute.

  Further, as shown in FIG. 11B, the image forming control unit 5a and the conveyance control unit 5b included in the engine controller 5 may be configured by two control units that are physically separated.

  In these cases, each master node (the image formation control unit 5a and the conveyance control unit 5b) can perform serial communication with each slave node by changing the use of the serial bus every predetermined time. The slave node's own address can be set by the slave address setting method according to the present invention. Here, in FIG. 11B, the image formation control unit 5a and the conveyance control unit 5b are connected by a bus line different from the serial bus used for serial communication with the slave node, and each is used by using the bus line. May transmit and receive the change timing of the usage time of the serial bus used for serial communication.

  Furthermore, as shown in FIG. 11 (c), the slave nodes corresponding to the respective master nodes are connected to the respective master nodes via different serial buses to constitute individual bus type serial communication systems. Also good.

  In this case, since the address of each slave node can be set by the slave address setting method of the present invention in each system, the same address is set for each slave node in each system. The degree of freedom is improved and a large voltage width of the analog voltage value corresponding to the address can be secured.

  Therefore, even if the analog voltage value input to the slave node may fluctuate due to unexpected noise, etc., the voltage of the analog voltage value relative to the address in consideration of the assumed voltage fluctuation range By setting the width, it is possible to prevent an erroneous address from being set in the slave node.

  In the above-described embodiment, the development control unit 50 (50a to 50d) is the slave node of the present invention and the engine controller 5 is the master node. However, for example, the image reading unit 300 is also connected to the image forming unit 400. Similarly, a bus serial communication system may be configured, and the present invention may be applied to a slave node of the system.

  Specifically, as shown in FIG. 13, a mirror scanning control unit 30 a that controls a mirror scanning mechanism provided in the image reading unit 3, and a document transport mechanism that transports a document placed on a document feed tray 301. A bus type serial communication system is configured by a slave node including a document conveyance control unit 30b that controls the image and a scanner controller 3 that performs overall control of the slave node. The address setting according to the present invention is performed by each of the image reading unit 300 and the image formation control unit 400. The address of each slave node may be set by a method.

  Here, each development control unit 50 that is controlled by a controlled unit that can be controlled in common is configured by a device having a common hardware and software, but a controlled unit that is difficult to control in common is controlled. The mirror scanning control unit 30a and the document conveyance control unit 30b cannot be configured by a common device in hardware or software. However, the present invention can be applied to any system.

  The engine controller 5 and the scanner controller 3 are master nodes of the respective systems. Since these are controlled by a system control unit that performs overall control of the color digital copying machine 100, a slave having the system control unit as a master node. Also operates as a node.

  As described above, even if a plurality of bus serial communication systems are hierarchically configured in the color digital copying machine 100, the address of the slave node is set by the address setting method of the present invention in each system. can do.

  In the above-described embodiment, the color digital copying machine 100 has been described as an example of an image forming apparatus equipped with the slave node of the present invention. However, the master node and a controlled unit based on a command from the master node. The slave node of the present invention can be mounted on an image forming apparatus other than the color digital copying machine 100 as long as it adopts a bus type serial communication system configured by slave nodes that control the above.

  In the above-described embodiment, each slave node 90 includes the step-down circuit 93 that steps down the analog voltage value input to the external input terminal and outputs the voltage to the external output terminal. Although the terminals are configured to be connectable, each slave node 90 may not include the step-down circuit 93.

  In this case, as shown in FIG. 14, for example, a unique analog voltage value may be directly input from the master node 9 to the external input terminal of each slave node 90, and further input to the external input terminal of each slave node 90. The analog voltage value to be input may be input from the power supply unit or the like instead of from the master node 9.

  Each of the above-described embodiments is merely an example of the present invention, and the scope of the present invention is not limited by the description. The specific configuration of each part is appropriately selected within the scope of the effects of the present invention. It goes without saying that changes can be designed.

Illustration of a bus-type serial communication system with a slave node (A) is an explanatory diagram of an address conversion table, (b) is an explanatory diagram of a slave attribute table. (A) is explanatory drawing of the data transmitted / received by serial communication, (b) is explanatory drawing of the relationship between the data transmitted / received by serial communication, and a clock signal, (c) is explanatory drawing of the communication between a master node and a slave node. Slave node configuration diagram Flowchart explaining own address setting operation in slave node Functional block diagram of color digital copier Illustration of the image forming unit Explanatory drawing of development control unit (A) is explanatory drawing of the address conversion table with which a development control part is provided, (b) is explanatory drawing of the slave attribute table with which an engine controller is provided. Explanatory drawing of the image formation part of another embodiment (A) is an explanatory diagram of a bus type serial communication system installed in a color digital copying machine of another embodiment, (b) is an explanatory diagram of a bus type serial communication system installed in a color digital copying machine of another embodiment, (c) ) Is an explanatory diagram of a bus type serial communication system installed in a color digital copying machine of another embodiment. (A) is explanatory drawing of the address conversion table with which the development control part and paper feed control part of another embodiment are provided, (b) is explanatory drawing of the slave attribute table with which the engine controller of another embodiment is provided. Explanatory diagram of a bus type serial communication system installed in a color digital copying machine of another embodiment Explanatory drawing of the bus type serial communication system provided with the slave node of another embodiment

Explanation of symbols

8: Serial bus 9: Master node 80: Data line 81: Clock signal line 90 (90a, 90b,...): Slave node 91 (91a, 91b,...) Serial communication unit 92 (92a, 92b,. ..): Address generator 93 (93a, 93b,...): Step-down circuit 94 (94a, 94b...): Address conversion table 900: Slave attribute table

Claims (5)

A slave node connected to a bus-type serial communication system having at least one master node,
A slave node having an address generation unit that sets its own slave address based on an analog voltage value input to an external input terminal.   2. A step-down circuit that steps down an analog voltage value input to the external input terminal and outputs the voltage to an external output terminal, wherein the external output terminal and an external input terminal of another slave node are connectable. The described slave node.   The slave node according to claim 1, wherein the address generation unit includes an address conversion table for converting the analog voltage value into the slave address.   A plurality of slave nodes according to any one of claims 1 to 3 are connected to a bus type serial communication system including at least one master node, and each slave node controls a controlled unit based on a command from the master node. An image forming apparatus configured as described above. A slave address setting method of a slave node connected to a bus type serial communication system having at least one master node,
A slave address setting method that sets its own slave address based on the analog voltage value input to the external input terminal.

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