JP2009117709A - Semiconductor thin film, thin film transistor array substrate, manufacturing method thereof, and semiconductor thin film manufacturing apparatus - Google Patents

Abstract

A method of manufacturing a semiconductor thin film capable of improving reliability and yield and improving quality is provided.
A method of manufacturing a semiconductor thin film according to the present invention includes a step of forming an amorphous semiconductor thin film on a substrate (Step 1), a step of removing a natural oxide film (Step 2), and ultraviolet irradiation. A step of performing surface oxidation treatment with ozone or / and oxygen radicals (Step 3), and a laser annealing step of obtaining a polycrystalline semiconductor thin film having crystal lattice boundaries at substantially equal intervals and having a lattice-like periodic structure (Step 4) In the laser annealing process, laser annealing is performed in order to obtain a polycrystalline semiconductor thin film by performing laser annealing immediately after the process of removing the natural oxide film without performing the process of performing the surface oxidation treatment. Laser light irradiation is performed at an energy density lower than the optimum energy density by a predetermined energy density.
[Selection] Figure 8

Description

  The present invention relates to a semiconductor thin film, a thin film transistor array substrate, and a manufacturing method thereof. Moreover, it is related with the manufacturing apparatus for manufacturing a semiconductor thin film.

  A liquid crystal display device is one of thin panels, and is widely used in monitors of personal computers and portable information terminal devices, taking advantage of low power consumption and small size and light weight. It is also widely used for TV applications and is replacing the conventional cathode ray tube.

  The mainstream of recent liquid crystal display devices is that a plurality of signal lines and a plurality of scanning lines are arranged in a lattice pattern, and a thin film transistor (hereinafter referred to as “TFT” ( An active matrix type in which a thin film transistor is also formed. The active matrix type generally has better image quality than the passive matrix type, and is the mainstream in display devices such as organic EL display devices in addition to liquid crystal display devices.

  The structure and material of the TFT are appropriately selected according to the application and required performance of the display device. As the TFT structure, a MOS (Metal Oxide Semiconductor) structure such as a bottom gate type (reverse stagger type) or a top gate type (stagger type) is often employed. Examples of the semiconductor thin film constituting the TFT include an amorphous silicon thin film and a polycrystalline silicon (low temperature polysilicon) thin film.

  A TFT using a polycrystalline silicon thin film as the channel active layer has high electron mobility. By utilizing a polycrystalline silicon thin film, active matrix display devices have been dramatically improved in performance. By using a TFT using a polycrystalline silicon thin film for forming a circuit around a display device, the use of an IC and an IC mounting substrate can be reduced. As a result, it is possible to simplify the configuration of the display device, achieve downsizing, and improve reliability.

  In a liquid crystal display device, when a polycrystalline silicon thin film is used as a switching element for each pixel, not only can the capacitance be reduced, but also the area of a storage capacitor connected to the drain side can be reduced. Therefore, a liquid crystal display device with high resolution and high aperture ratio can be realized.

  An organic EL display device is a so-called self-luminous display device in which an EL layer emits light by passing a current between a pair of electrodes sandwiching the EL layer. A semiconductor thin film using an amorphous silicon thin film or a polycrystalline silicon thin film is applied to a pixel signal processing circuit disposed in a pixel of an active organic EL display device. A TFT using a polycrystalline silicon thin film has been widely applied because it has a high electron mobility and a threshold voltage shift of a transistor that occurs when a current is passed for a long time is small. A TFT using a polycrystalline silicon thin film can also be applied to a peripheral circuit portion that controls a pixel signal processing circuit.

  A TFT using polycrystalline silicon is manufactured as follows. First, an amorphous silicon thin film is formed on a glass substrate, and the amorphous silicon is melted by irradiating it with an excimer laser (XeCl (wavelength: 308 nm)). Next, it is crystallized by cooling to obtain polycrystalline silicon. Polycrystalline silicon is formed on the entire surface of the glass substrate by scanning with a laser beam. This is a so-called laser annealing method.

  A natural oxide film is always formed on an amorphous silicon thin film laminated on a glass substrate by exposure to the atmosphere. At this time, impurities in the atmosphere may be mixed into the natural oxide film. In order to prevent this impurity from diffusing into silicon, a natural oxide film formed on the surface of amorphous silicon is treated with hydrofluoric acid or the like immediately before excimer laser annealing (hereinafter simply referred to as “laser annealing”). The removal is performed using. Then, after removing the natural oxide film on the amorphous silicon surface, laser annealing is performed immediately to convert the amorphous silicon into polycrystalline silicon.

  However, the polycrystalline silicon produced by such a method has a non-uniform crystal size. For this reason, when a TFT is formed, the driving capability and threshold voltage of the transistor may vary due to the non-uniformity of the crystal size of the polycrystalline silicon. More specifically, crystal defects are localized in the crystal grain boundaries of polycrystalline silicon, which impedes carrier movement in TFTs, and fluctuations in transistor driving capability and threshold voltage due to non-uniformity of crystal grains. Will become bigger. Furthermore, the crystal size changes according to the fluctuation of the energy density of the laser beam. For this reason, when trying to obtain a desired crystal size, the energy density must be set within a very narrow range. Further, when the energy density is increased in order to obtain large crystal grains, microcrystals that cause a significant deterioration in transistor performance are generated.

  The optimum energy density varies depending on a slight film thickness change of amorphous silicon. For this reason, it is very difficult to manage the apparatus when forming the amorphous silicon thin film. In particular, in the case of an excimer laser using XeCl gas, it is inevitable that the pulse fluctuates during the operation of the laser emitting oscillator. As a result, it is necessary to monitor the fluctuation of the oscillator and change the energy density setting at any time.

  In addition, during laser irradiation, hydrogen gas contained in a large amount in amorphous silicon is released into the silicon film, and the silicon film in that portion may be depressed, so-called bumping (ablation). If this bumping is formed in the semiconductor active layer region, transistor operation failure and reliability decrease are caused. In addition, the breakdown voltage of the gate insulating film is reduced. Therefore, not only the yield but also the quality is deteriorated.

Patent Document 1 proposes a method in which after forming an extremely thin oxide film on the surface of amorphous silicon, the oxide film is removed with hydrofluoric acid and then laser annealing is performed. Further, in Patent Documents 2 to 4, after the natural oxide film formed on the amorphous silicon surface is removed with hydrofluoric acid, and before laser annealing treatment, ozone water or the like is sprayed on the oxidizing power. Discloses a method of forming a surface oxide film on an amorphous silicon surface. Patent Document 2 describes a technique of irradiating ultraviolet (UV) light as a method of forming an oxide film on the surface of amorphous silicon.
JP 2001-326359 A paragraph number 0014 JP 2002-141510 A paragraph number 0019-0023 [Patent Document 1] Japanese Patent Laid-Open No. 2002-1000056 Paragraph No. 0033-0043 FIG. JP, 2003-158135, A Paragraph Nos. 0011-0013

  The method of Patent Document 1 has a problem that bumping occurs. According to the methods of Patent Documents 2 to 4, bumping can be prevented. However, the method of spraying ozone water on the amorphous silicon surface has a problem that it is difficult to form a uniform surface oxide film on the entire amorphous silicon surface without unevenness. This is because the surface of the amorphous silicon treated with hydrofluoric acid to remove the natural oxide film exhibits water repellency. The hydrofluoric acid treatment and the ozone water treatment are generally performed continuously with a spin cleaning apparatus. When using a spin cleaning device, ozone water is sprayed by a nozzle attached above the amorphous silicon surface while rotating the glass substrate, so that the ozone water is spread over the entire amorphous silicon surface. Perform oxidation treatment. However, since the amorphous silicon surface is water-repellent, it is difficult to oxidize uniformly without unevenness. For example, spiral unevenness may occur radially. In addition, when ozone water is sprayed and becomes a mist that adheres to the amorphous silicon surface, if laser annealing is performed as it is, the crystalline state of the part becomes an abnormal state, which is the same as in the case of bumping In addition, the transistor malfunctions and the gate insulating film breakdown voltage decreases.

  Moreover, when manufactured by the method described in Patent Documents 1 to 4, the obtained polycrystalline silicon has crystal grains in a disk shape (polygonal shape close to a circle), and the crystals are not aligned. Further, when the energy density is increased in order to increase the crystal size, the crystal size is nonuniform. Crystal non-uniformity leads to variations in carrier movement. Further, it becomes a variation factor of the driving capability and threshold voltage of the transistor.

  The present invention has been made in view of the above-mentioned problems, and the object of the present invention is to provide a semiconductor thin film, a thin film transistor array substrate, and a manufacturing method thereof that can improve reliability, improve yield, and lead to quality improvement. And a semiconductor thin film manufacturing apparatus.

  The method of manufacturing a semiconductor thin film according to the present invention includes a step of forming an amorphous semiconductor thin film on a substrate, a step of removing a natural oxide film formed on a surface of the amorphous semiconductor thin film, and the natural thin film. After removing the oxide film, the surface of the amorphous semiconductor thin film is subjected to surface oxidation treatment with ozone or / and oxygen radicals generated by ultraviolet irradiation, and an inert gas atmosphere is applied to the amorphous semiconductor thin film. A laser annealing step of obtaining a polycrystalline semiconductor thin film having crystal grain boundaries at substantially equal intervals and having a lattice-like periodic structure by irradiating with laser light. In the laser annealing step, laser light for obtaining a polycrystalline semiconductor thin film by performing laser annealing immediately after the step of removing the natural oxide film without passing through the step of performing the surface oxidation treatment. The laser beam irradiation is performed at an energy density lower than the optimum energy density by a predetermined energy density.

  The semiconductor thin film according to the present invention is polycrystallized by the method for manufacturing a semiconductor thin film. The obtained polycrystalline semiconductor thin film has an interval between adjacent crystal grain boundaries of 300 nm or more and 400 nm or less, and the crystal grain boundaries are formed from flat portions of crystal grains partitioned by the crystal grain boundaries. It protrudes like a protrusion, the height of the protrusion is 60 nm or less, and the polycrystalline semiconductor thin film has a surface roughness Ra of 10 nm or less.

  An apparatus for manufacturing a semiconductor thin film according to the present invention is used in the method for manufacturing a semiconductor thin film, and includes a surface oxidation unit used in the step of performing the surface oxidation treatment. The surface oxidation unit includes an irradiation light source that emits ultraviolet rays that generate ozone and / or oxygen radicals in an oxygen gas atmosphere, and an irradiation unit that irradiates the amorphous semiconductor thin film with the ultraviolet rays.

  According to the present invention, it is possible to provide a semiconductor thin film, a thin film transistor array substrate, a manufacturing method thereof, and a semiconductor thin film manufacturing apparatus capable of improving reliability and yield and improving quality. Have

  Hereinafter, an example of an embodiment to which the present invention is applied will be described. It goes without saying that other embodiments may also belong to the category of the present invention as long as they match the gist of the present invention. Moreover, the size and ratio of each member in the following drawings are for convenience of explanation, and are not limited to this.

  The display device according to the present embodiment is a display device on which an active matrix TFT array substrate having a thin film transistor (TFT) provided with polycrystalline silicon is mounted. Here, a transmissive liquid crystal display device will be described as an example of the display device.

  FIG. 1 is a schematic plan view of a TFT array substrate 100 according to the present embodiment. As shown in FIG. 1, the TFT array substrate 100 includes a gate signal line 11, a scanning signal driving circuit 12, a first external wiring 13, a storage capacitor wiring 14, a source signal line 21, a display signal driving circuit 22, and a second external wiring. 23 etc.

  The gate signal lines (scanning signal lines) 11 extend in the horizontal direction in FIG. 1 and are arranged in parallel in the vertical direction. The source signal lines (display signal lines) 21 extend in the vertical direction in FIG. 1 and are arranged in parallel in the horizontal direction so as to intersect with the gate signal lines 11 via a gate insulating layer (not shown). Yes. The plurality of gate signal lines 11 and the plurality of source signal lines 21 form a matrix so as to be substantially orthogonal, and a region surrounded by the adjacent gate signal lines 11 and the source signal lines 21 is a pixel 30. Accordingly, the pixels 30 are arranged in a matrix. A region where the plurality of pixels 30 are formed is a display region 40. An area partitioned outside the display area 40 is a frame area 41.

  The scanning signal driving circuit 12 is formed in the frame area 41, and each gate signal line 11 extends from the display area 40 to the scanning signal driving circuit 12. Similarly, the display signal drive circuit 22 is also formed in the frame area 41, and each source signal line 21 extends from the display area 40 to the display signal drive circuit 22. A first external wiring 13 is connected in the vicinity of the scanning signal driving circuit 12, and a second external wiring 23 is connected in the vicinity of the display signal driving circuit 22. The first external wiring 13 and the second external wiring 23 are wiring boards such as FPC (Flexible Printed Circuit).

  Various external signals are supplied to the scanning signal driving circuit 12 via the first external wiring 13 and to the display signal driving circuit 22 via the second external wiring 23. The scanning signal drive circuit 12 supplies a gate signal (scanning signal) to the gate signal line 11 based on a control signal from the outside. The gate signal lines 11 are sequentially selected by this gate signal. The display signal drive circuit 22 supplies a display signal to the source signal line 21 based on an external control signal and display data. As a result, a display voltage corresponding to the display data can be supplied to each pixel 30.

  The scanning signal driving circuit 12 and the display signal driving circuit 22 are directly mounted on the TFT array substrate 100 using COG (Chip On Glass) technology, but the configuration is not limited to this. For example, the drive circuit may be connected on the TFT array substrate 100 by TCP (Tape Carrier Package).

  In the vicinity of the intersection of the gate signal line 11 and the source signal line 21 of each pixel, at least one signal transmission TFT 31 is provided. In each pixel, a storage capacitor element 32 connected to the TFT 31 is formed. The gate electrode of the TFT 31 formed in the pixel is connected to the gate signal line 11, and the source electrode of the TFT 31 is connected to the source signal line 21. When a voltage is applied to the gate electrode, a current flows from the source signal line 21. Thereby, a display voltage is applied from the source signal line 21 to the pixel electrode connected to the drain electrode of the TFT 31. An electric field corresponding to the display voltage is generated between the pixel electrode and the counter electrode.

  On the other hand, the storage capacitor element 32 is electrically connected to the counter electrode through the storage capacitor wiring 14 in addition to the TFT 31. Accordingly, the storage capacitor element 32 is connected in parallel with the capacitor between the pixel electrode and the counter electrode. An alignment film is formed on the surface of the TFT array substrate 100.

  Further, a counter substrate (not shown) is disposed opposite to the TFT array substrate 100. The counter substrate is, for example, a color filter substrate, and is disposed on the viewing side. On the counter substrate, a color filter, a black matrix (BM), a counter electrode, an alignment film, and the like are formed. The counter electrode may be arranged on the TFT array substrate 100 side.

  A liquid crystal layer is sandwiched between the TFT array substrate 100 and the counter substrate. In addition, a polarizing plate, a retardation plate, and the like are provided on the outer surfaces of the TFT array substrate 100 and the counter substrate. A backlight unit or the like is disposed on the non-viewing side of the liquid crystal display panel.

  The alignment direction of the liquid crystal molecules is changed by an electric field between the pixel electrode and the counter electrode. The polarization state of light passing through the liquid crystal layer changes according to the change in the orientation of the liquid crystal molecules. That is, the polarization state changes when linearly polarized light formed by passing through the polarizing plate from the backlight unit passes through the liquid crystal layer. Therefore, the amount of light passing through the polarizing plate on the counter substrate side changes depending on the polarization state. That is, among the transmitted light that passes through the liquid crystal display panel from the backlight unit, the amount of light that passes through the viewing-side polarizing plate changes. The alignment direction of the liquid crystal changes depending on the applied display voltage. Therefore, the amount of light passing through the viewing-side polarizing plate can be changed by controlling the display voltage. That is, a desired image can be displayed by changing the display voltage for each pixel. In the storage capacitor element 32, the display voltage can be held by forming an electric field in parallel with the electric field between the pixel electrode and the counter electrode.

  In the TFT array substrate 100 configured as described above, a semiconductor thin film is used to form the TFT 31 and the storage capacitor element 32. A method for manufacturing a semiconductor thin film according to this embodiment will be described with reference to FIGS.

FIG. 2 is a flowchart for explaining a method for manufacturing a semiconductor thin film according to the present embodiment. 3A to 3C show manufacturing process diagrams of the semiconductor thin film according to this embodiment. First, the base film 2 is formed on the insulating substrate 1. The insulating substrate 1 can be configured by a transmissive substrate such as a glass substrate or a quartz substrate. In the present embodiment, a SiN film is formed on the insulating substrate 1 by a CVD (CVD: Chemical Vapor Deposition) method, and a SiO ₂ film is formed thereon. The film thickness of the SiN film is, for example, 50 nm, and the film thickness of the SiO ₂ film is, for example, 200 nm. The underlying film 2 is provided mainly for the purpose of preventing mobile ions such as Na from the glass substrate from diffusing into the semiconductor layer, and is not limited to the above film configuration and film thickness. The base film may not be provided.

  Next, an amorphous semiconductor thin film 3A is formed on the upper layer of the base film 2 by a CVD method (Step 1). In the present embodiment, an amorphous silicon (αSi) film is used as the amorphous semiconductor thin film 3A. The amorphous silicon film is preferably formed to a thickness of 40 to 60 nm, more preferably 45 to 55 nm. In the present embodiment, the amorphous semiconductor thin film 3A has a thickness of 50 nm. The base film 2 and the amorphous semiconductor thin film 3A are preferably formed continuously in the same apparatus or the same chamber. Thereby, it is possible to prevent contaminants such as boron (B) existing in the air atmosphere from being taken into the interface of each film.

  Note that it is preferable to perform annealing at a high temperature after the formation of the amorphous semiconductor thin film 3A. This is to reduce hydrogen contained in a large amount in the amorphous semiconductor thin film 3A formed by the CVD method. For example, the inside of the chamber held in a low vacuum state in a nitrogen atmosphere is heated to about 480 ° C., and the substrate on which the amorphous semiconductor thin film 3A is formed is held for 45 minutes. By such treatment, when the amorphous semiconductor thin film 3A is crystallized, hydrogen is not rapidly desorbed even if the temperature rises. And it becomes possible to suppress the surface roughness of the amorphous semiconductor thin film 3A. With the above process, the configuration shown in FIG.

  Subsequently, the natural oxide film formed on the surface of the amorphous semiconductor thin film 3A is removed with hydrofluoric acid (Step 2). As hydrofluoric acid, dilute hydrofluoric acid having a concentration of several percent or buffered hydrofluoric acid can be suitably used. By removing the natural oxide film with hydrofluoric acid, dust and impurities on the surface of the amorphous silicon can be removed at the same time. Since the amorphous silicon surface from which the natural oxide film has been removed is in a state where silicon is exposed, if left untreated, a new natural oxide film is formed. Therefore, the next process is performed within several hours. Preferably, it is within 2 hours.

  Next, surface oxidation treatment is performed on the amorphous semiconductor thin film 3A (Step 3). The surface oxidation treatment is performed by using ozone or / and oxygen radicals generated by ultraviolet irradiation. As the ultraviolet irradiation light source, a low-pressure mercury lamp that emits light having a wavelength of 185 to 254 nm can be suitably used. If it is about 800W, use 2 to 4 lights. Here, “ozone or / and oxygen radicals generated by ultraviolet irradiation” means that ozone or / and oxygen radicals generated by irradiation with ultraviolet rays in an oxygen gas atmosphere are used. Note that the oxygen gas atmosphere includes the atmosphere.

  Light having a wavelength of 185 nm is absorbed by oxygen in the atmosphere, and ozone having a strong oxidizing power is generated. In addition, light having a wavelength of 254 nm generates an oxygen atom radical having a strong oxidizing power. The separation distance between the amorphous semiconductor thin film 3A and the irradiation light source is set to be within 0 to 20 mm. This is because the presence of ozone and oxygen atom radicals is limited to within 20 mm from the irradiated part.

  The ozone generation concentration by ultraviolet irradiation depends on the power and oxygen concentration of the low-pressure mercury lamp. Further, the amount of surface oxidation, that is, the oxide film thickness varies depending on the time during which the amorphous semiconductor thin film surface is exposed to the ozone atmosphere. The oxide film thickness is not particularly limited but is generally 3 nm. The oxide film thickness was measured with an ellipsometer. The exposure time is set to a time when the surface roughness Ra of the polycrystalline silicon becomes 12 nm or less by laser annealing described later. In this embodiment, the exposure is performed for about 20 seconds to 40 seconds. If it exceeds 40 seconds, the oxidation proceeds, and the polycrystalline silicon surface after laser annealing may be roughened.

  The surface oxidation apparatus applied to the present invention is not particularly novel, and the same apparatus as that used for hydrophilic treatment of the glass surface, modification of the resin surface, oxidation (ashing) of organic compounds, etc. should be used. Can do. However, in order to perform surface oxidation suitable for laser annealing, a material that satisfies the above conditions is used.

  After the surface oxidation step in Step 3, laser annealing is performed on the amorphous semiconductor thin film 3A in an inert gas atmosphere (Step 4). Here, the inert gas atmosphere refers to a state where the oxygen concentration is 50 ppm or less. The state where the oxygen concentration is 50 ppm or less can be easily obtained by blowing nitrogen gas or the like. In an inert gas atmosphere, as shown in FIG. 3B, the laser beam 20 is irradiated from above the amorphous semiconductor thin film 3A. The laser light 20 is converted into a linear beam shape through a predetermined optical system, and then irradiated to the amorphous semiconductor thin film 3A.

  In this embodiment, a XeCl excimer laser is used as the laser light 20. In the case of excimer laser annealing, a linear laser beam formed in a profile having a top flat distribution of irradiation energy density in the scanning direction is irradiated as a 300 Hz pulse. Irradiation is repeated while approximately 95% of two continuous laser beam pulses are overlapped with each other. The amorphous semiconductor thin film 3A is converted into a polycrystalline semiconductor thin film 3 by laser annealing. In this embodiment, the amorphous silicon is converted to polycrystalline silicon.

  As shown in FIG. 3 (c), the crystal grain boundary, which is a gap between crystal grains, is known to be raised when converting from an amorphous semiconductor thin film to a polycrystalline semiconductor thin film. ing. It is preferable that the raised height H (see FIG. 3C) raised from the flat portion in a protruding shape is 70 nm or less. Moreover, the surface roughness Ra of the entire polycrystalline semiconductor thin film is preferably 12 nm or less, and is generally 5 nm or more. When silicon is used as the semiconductor thin film, the raised height H is approximately 60 nm or less. Further, the surface roughness Ra is 10 nm or less. When the semiconductor thin film is used as a thin film transistor or the like, the polycrystalline silicon surface is preferably smooth, which will be described later.

  FIG. 4 shows a schematic plan view of polycrystalline silicon obtained by the laser annealing step. As shown in the figure, the polycrystallized semiconductor thin film 3 is surrounded by a crystal grain boundary 3 </ b> B that is raised when a crystal grows and collides with each other when irradiated with laser light. It is composed of crystal particles 3C. The area of the crystal particle 3C is the crystal size.

  The crystal grain boundaries 3B are arranged at substantially equal intervals and have a lattice-like periodic structure. In other words, the crystal particles 3C are arranged substantially uniformly in a lattice shape. Here, the “lattice shape” means a substantially rectangular shape having four sides as shown in FIG. However, it shall include those in which the corners are rounded. Further, in the present embodiment, as shown in FIG. 4, the crystal grains are arranged in a substantially linear manner.

  At this time, the interval between the crystal grain boundaries 3B is in the range of 300 nm or more and 400 nm or less. In other words, the linear length D of one side of the lattice-shaped crystal particle 3C is in the range of 300 nm to 400 nm. Note that the crystal grain boundary or the interval between crystal grains can be obtained by measuring with SEM or AFM.

  By performing the laser annealing treatment in an inert gas atmosphere, the surface roughness Ra in an energy density region where a lattice-arranged structure appears can be reduced to 12 nm or less. In other words, when not performed in an inert gas atmosphere, the height H of the grain boundary portion becomes large, and the surface roughness Ra becomes larger.

  The laser annealing treatment (Step 4) is preferably performed after the surface oxidation step (Step 3) without inserting any hair. If it is within several hours, there is no particular influence, but there is a possibility that contamination or the like may occur due to contact with the outside air. Therefore, it is preferable that the surface annealing apparatus is in-line with the laser annealing apparatus and continuous processing is performed.

  FIG. 5 is a schematic configuration diagram showing an example of a semiconductor thin film manufacturing apparatus in which a laser annealing apparatus and a surface oxidation apparatus are integrated. As shown in the figure, the semiconductor thin film manufacturing apparatus 50 includes a substrate carry-in / out unit 51, a surface oxidation unit 53, a laser annealing unit 54, a laser oscillator, an optical system unit, a transfer means 52, and the like.

  The transport means 52 is configured to be movable left and right, back and forth, and movable up and down so that the substrate is taken out from the unit where the processing on the substrate has been completed and transferred to the next processing unit. The substrate holding unit in each unit is configured to be able to hold the substrate horizontally by vacuum suction. The surface oxidation unit 53 is installed to perform the processing of Step 3 and includes the above-described low-pressure mercury lamp and the like. The laser annealing unit 54 is installed to perform the processing of Step 4 described above.

  The cassette in which the insulating substrate 1 on which the amorphous semiconductor thin film 3A from which the natural oxide film has been removed by Step 2 is stacked is housed on the mounting table of the substrate carry-in / out unit 51, and is transported by the transfer arm 52. Is passed on. The insulating substrate 1 is first transported to the surface oxidation unit 53 by the transport means 52. Then, the surface oxidation treatment of the insulating substrate 1 is performed with a preset irradiation intensity or the like. By this step, an oxide film is formed on the surface of the amorphous semiconductor thin film 3A.

  Then, it is conveyed to the laser annealing unit 54 and subjected to laser annealing treatment. By making the surface oxidation unit 53 and the laser annealing unit 54 in-line, contamination due to contact with outside air can be reliably prevented. Further, since the time required for the surface oxidation treatment is shorter than the time required for the laser annealing treatment, there is no fear of causing a reduction in the processing speed.

  After the laser annealing treatment in Step 4, the oxide film present on the surface of the polycrystalline silicon and the protruding portion at the grain boundary are removed with hydrofluoric acid (Step 5). For example, when buffered hydrofluoric acid is used, the inventors have conducted an experiment. As a result, the etching rate of polycrystalline silicon is 1 nm / min or less, whereas the etching rate of the protruding portion at the grain boundary is It was 4 nm / min. Therefore, by performing the buffered hydrofluoric acid treatment for 5 minutes, the projections at the grain boundary part can be cut by about 20 nm. When the buffered hydrofluoric acid treatment was performed for 5 minutes, it was confirmed that the protrusion height at the grain boundary portion was 40 nm or less.

  In the case where it is desired to cut the projections at the grain boundary portions in a short time, the surface of the polycrystalline silicon may be oxidized and then hydrofluoric acid treatment. The etching rate of the oxidized film thickness portion can be increased. These operations may be performed a plurality of times.

Here, the energy density of the laser beam irradiated in the laser annealing process (Step 4) will be described in detail. First, a method for manufacturing a semiconductor thin film according to a conventional example will be described. As described above, the amorphous semiconductor thin film is polycrystallized by performing laser annealing immediately after the step of removing the natural oxide film of Step 1 without going through the step of performing the step 2 surface oxidation treatment. When using amorphous silicon, the optimum energy density of the laser beam for obtaining a thin semiconductor film varies depending on various conditions such as the film thickness of the amorphous silicon, but is approximately around 350 to 380 mJ / cm ^2. . Note that the “optimal energy density” herein refers to a region where the crystal size is not too small for functioning as a thin film transistor and does not become a region where large crystal grains and microcrystals are mixed.

In the method for manufacturing a semiconductor thin film according to this embodiment, the optimum range of energy density shifts to an energy density that is lower than the optimum range by a predetermined energy density. As a result of repeated experiments by the present inventors, when other conditions other than the characteristic part of the present invention are made the same, an energy density lower by about 60 mJ / cm ² than the optimum energy density of the conventional example is the optimum energy range. became. That is, the laser light irradiation is performed at an energy density lower by a predetermined energy density.

  Note that the optimum range of the laser beam energy density varies depending on the film thickness of the semiconductor thin film. When an excimer laser is used as the laser light and silicon is used as the semiconductor thin film, the laser light having a wavelength of 308 nm is easily absorbed by silicon. Therefore, a temperature difference can be made in the film thickness direction. Utilizing this property, the vicinity of the surface is heated and melted to leave the crystal nucleus without being dissolved in the deep part, and the crystal is grown from this crystal nucleus. In the present embodiment, the steps 1 to 5 are followed to shift to a lower energy density than the optimum energy density range of the conventional example, and the crystal grain boundaries are substantially equidistant and lattice-like. A polycrystalline semiconductor thin film having a periodic structure can be obtained.

  As a result of earnest examination of surface observation by an electron microscope (SEM) and surface unevenness observation by an atomic force microscope (AFM), the present inventors have measured the scattered light intensity. The inventors have found that the energy density at which the crystal grain boundaries can have a lattice-like periodic structure can be easily derived at substantially equal intervals. This utilizes the fact that when an amorphous semiconductor thin film is changed to a polycrystalline semiconductor thin film, surface irregularities become large and surface irregular reflection occurs. In other words, it utilizes the fact that directivity appears in the reflected light when the crystal grain boundaries, that is, the protruding portions are linearly arranged at equal intervals. This method has an advantage that the crystal state can be easily confirmed. The correlation between the scattered light intensity data, the surface observation by SEM, and the surface irregularity observation of AFM is sufficiently verified.

  FIG. 6 is a schematic diagram of the scattered light intensity measurement device 60 used in the present embodiment. The scattered light intensity measuring device 60 includes a DC power source, a white LED 61, a lens 62, a black tube 65, a light receiving unit 66, a signal amplifier, a personal computer, and the like. The light 63 emitted from the white LED light source 61 connected to the DC power source is irradiated to the measurement sample from the normal direction through the lens 62. Then, the reflected light 64 having a predetermined angle is detected by the light receiving unit 66 among the reflected light 64 reflected on the surface of the measurement sample. The value detected by the light receiving section 66 is transmitted to a personal computer after the voltage is read and amplified by a signal amplifier.

FIG. 7 plots the value of the scattered light intensity with respect to the energy density at the time of laser annealing in the scattered light intensity measuring device 60 using polycrystalline silicon on the insulating substrate 1 manufactured by the above-described manufacturing method as a measurement sample. Shows what The energy density, which is a structure in which crystals are arranged in a uniform and equally spaced lattice, is a region of 300 to 320 mJ / cm ² . The margin of energy density is 20 mJ / cm ² . When it is less than 300 mJ / cm ² , the crystal gradually becomes smaller, and when it exceeds 320 mJ / cm ² , the arrangement structure gradually collapses to become a so-called non-uniform crystal in which large crystals and small crystals are mixed. However, no microcrystals were found.

By acquiring data as shown in FIG. 7, the energy density in the optimum state of the polycrystalline silicon crystal can be derived. In this embodiment, if it is set to 310 mJ / cm ² , variations in the film thickness of amorphous silicon and fluctuations in the management range of the production process of the output of the laser oscillator can be sufficiently tolerated. That is, it is possible to obtain a high yield of polycrystalline silicon having crystal grain boundaries at substantially equal intervals and having a lattice-like periodic structure.

FIG. 8 shows an AFM photograph of polycrystalline silicon obtained by irradiating laser light to amorphous silicon at an energy density of 310 mJ / cm ² . As shown in the figure, polycrystalline silicon has a uniform crystal grain boundary and is arranged at equal intervals, and has a lattice-like periodic structure. It was confirmed that the average length of one side of the crystal grains at this time was 330 nm. The average length variation index (%), that is, the standard deviation is 10% or less. In addition, when the present inventors examined about a disk-shaped crystal structure, the parameter | index (%) of dispersion | variation was about 20-30%. Further, it was found that the variation increases as the crystal becomes larger, and the variation index (%) becomes slightly more than 40%.

  Next, the structure of the TFT 31 and the storage capacitor 32 using the above-described semiconductor thin film will be described. FIG. 9 is a schematic cross-sectional view in the vicinity of the TFT 31 and the storage capacitor 32 according to this embodiment. FIG. 9 shows a cross-sectional structure cut along the channel length direction in which the source region and the drain region are formed. As the channel active layer of the TFT 31, polycrystalline silicon, which is a polycrystalline semiconductor thin film manufactured by the above-described method, is used.

  As shown in FIG. 9, the TFT array substrate 100 includes an insulating substrate 1, a base film 2, a semiconductor active layer 3 as a semiconductor thin film functioning as an active element, a gate insulating film 4, a gate electrode 5a, a storage capacitor element 5b, an interlayer It has an insulating film 6, a source electrode 7a, a drain electrode 7b, a passivation film 8, a contact hole 9, a pixel electrode 10, and the like.

  On the insulating substrate 1, a base film 2 and an island-shaped semiconductor active layer 3 are formed. These manufacturing methods are as described in the above-described method for manufacturing a semiconductor thin film. The island pattern is formed through a photolithography process and an etching process.

  In the TFT 31, the semiconductor active layer 3 constitutes a source region 3a, a drain region 3c, and a channel region 3b sandwiched between them, as shown in FIG. The source region 3a and the drain region 3c are conductive regions containing impurities. In the storage capacitor element 32, the semiconductor active layer 3 functions as the lower electrode 3d. The lower electrode 3d is doped with impurities so as to exhibit conductive characteristics. The semiconductor active layer 3 may have a tapered end portion. With the tapered shape, the gate insulating film 4 formed on the semiconductor active layer 3 can be satisfactorily covered. Therefore, defects such as dielectric breakdown can be sufficiently suppressed, which can contribute to the improvement of the reliability of the TFT 31.

A gate insulating film 4 that is an insulating layer is formed on the semiconductor active layer 3 so as to be in contact with and cover these layers. The gate insulating film 4 is composed of a SiO ₂ film. On the gate insulating film 4, a gate electrode 5a is formed at a position facing the channel region 3b, and an upper electrode 5b is formed at a position facing the lower electrode 3d. That is, the gate electrode 5a is formed on the TFT 31, and the upper electrode 5b is formed on the storage capacitor element 32. The gate electrode 5a and the upper electrode 5b are formed of the same conductive layer (metal layer). Impurities doped in the source region 3a and the drain region 3c formed in the semiconductor active layer 3 are doped using the gate electrode 5a and the upper electrode 5b as masks. The semiconductor active layer into which the impurities are not implanted becomes the channel region 3b.

  The interlayer insulating film 6 is formed so as to cover the gate insulating film 4, the gate electrode 5a, the upper electrode 5b, and the like. In the interlayer insulating film 6 and the gate insulating film 4, first contact holes 9 penetrating from the surface of the interlayer insulating film 6 to the source region 3 a and the drain region 3 c are respectively disposed. A first electrode is disposed in the first contact hole 9. Of the first electrodes, those electrically connected to the source region 3a function as the source electrode 7a, and those electrically connected to the drain region 3c function as the drain electrode 7b. The TFT 31 having the semiconductor thin film according to the present embodiment is configured as described above.

  When the TFT 31 according to this embodiment is mounted on a liquid crystal display device, a passivation film 8 is further formed so as to cover the source electrode 7a, the drain electrode 7b, and the interlayer insulating film 6. A second contact hole 9a that penetrates to the drain electrode 7b and an opening (not shown) such as a terminal are formed in the passivation film 8, and the pixel electrode 10 is disposed on the second contact hole 9a and the passivation film 8. It is installed. An alignment film (not shown) is formed on the uppermost surface of the TFT array substrate. Note that the configuration of the TFT 31 and the configuration of the storage capacitor 32 are not limited to the above embodiment.

  Next, a specific method for manufacturing the TFT 31 and the storage capacitor 32 using the above-described semiconductor thin film will be described. First, as described above, the base film 2 and the amorphous semiconductor thin film 3A are formed on the insulating substrate 1. Then, by the above-described method, the amorphous semiconductor thin film 3A is passed through the above Step 1 to Step 5, so that the crystal grain boundary is a polycrystalline semiconductor thin film having a lattice-like periodic structure at substantially equal intervals. A certain semiconductor active layer 3 is obtained.

  After Step 5 is processed, that is, after a step of removing the oxidized portion on the surface of the polycrystalline semiconductor thin film and a step of removing the protruding portion, a step of performing surface oxidation is further added. The surface oxidation method is not particularly limited. For example, it is possible to perform ozone oxidation by ultraviolet irradiation, ozone gas injection, ozone water cleaning or the like by the same method as the manufacturing process of Step 2 above. Further, the oxide film may be formed with oxygen gas in a plasma atmosphere. In particular, a large number of silicon atoms having dangling bonds (dangling bonds) exist at the interface of polycrystalline silicon treated with hydrofluoric acid. By this surface oxidation treatment, dangling bonds of silicon atoms can be terminated by oxygen atoms.

The semiconductor active layer 3 formed as described above is patterned into a desired shape through a photoresist process and an etching process. Thereafter, a gate insulating film 4 is formed so as to cover the entire substrate surface on the semiconductor active layer 3. A SiO ₂ film is used as the gate insulating film 4 and is formed by a CVD method. When the gate insulating film 4 is thin, when a voltage is applied between the gate electrode 5a or the upper electrode 5b and the semiconductor active layer 3, electric field concentration occurs at the protruding portion of the polycrystalline silicon grain boundary, which is the worst. In this case, dielectric breakdown may occur. Considering that the protrusion height of the grain boundary portion is about 40 nm, the thickness of the gate insulating film 4 is set to 80 nm or more. Preferably it is 1000 nm or more.

  According to the method for manufacturing a semiconductor thin film according to the present embodiment, as shown in FIG. 3C, the shape of the protrusion is a gentle inclination of about 20-30 ° and the protrusion tip is rounded. The film 4 is uniformly formed on the polycrystalline silicon surface.

Next, a layer for forming the gate electrode 5a, wiring (not shown) and the upper electrode 5b is formed. This layer can be composed of Mo, Cr, W, Ta, Al, or an alloy film containing these as main components. In this embodiment, Mo was formed to a thickness of 200 to 400 nm by a sputtering method using a DC magnetron. Then, using a known photoengraving method, patterning into a desired shape is performed to form the gate electrode 5a, the wiring and the upper electrode 5b. In this embodiment, the gate electrode 5a is etched by a wet etching method using a chemical solution in which phosphoric acid and nitric acid are mixed. Instead of this, it is also possible to carry out by a dry etching method using a gas in which SF ₆ and O ₂ are mixed.

  Next, an impurity element is introduced into the source region 3a, the drain region 3c, and the lower electrode 3d of the semiconductor active layer 3 using the formed gate electrode 5a as a mask. P, As, and B can be used as impurity elements introduced here. If P or As is introduced, an NMOS can be obtained, and if B is introduced, a PMOS can be obtained. Further, if the processing of the gate electrode 5a is performed twice for the n-type TFT gate electrode and the p-type TFT gate electrode, the n-type and p-type TFT 318 can be formed on the same substrate. The introduction of impurity elements such as P and B was performed using an ion doping method. Through the above steps, the gate electrode 5a, the source region 3a, and the drain region 3c are formed. Note that an LDD (Lightly Doped Drain) structure may be employed in order to improve the reliability of the transistor. Further, an ion implantation method may be used instead of the ion doping method.

Next, an interlayer insulating film 6 is formed so as to cover the entire substrate surface above the gate electrode 5a. In the present embodiment, the interlayer insulating film 6 is formed by plasma CVD with the SiO ₂ film having a thickness of 500 to 1000 nm. An SiN film may be used instead of the SiO ₂ film. And it hold | maintained for about 1 hour in the annealing furnace heated at 450 degreeC in nitrogen atmosphere. As a result, the impurity element introduced into the source / drain regions of the semiconductor active layer 3 is further activated.

Next, the formed gate insulating film 4 and interlayer insulating film 6 are patterned into a desired shape using a known photolithography method. Here, contact holes 9 reaching the source region 3a and the drain region 3c of the semiconductor active layer 3 are respectively formed. That is, in the contact hole 9, the gate insulating film 4 and the interlayer insulating film 6 are removed. In this embodiment, the contact hole 9 is etched by a dry etching method using a mixed gas of CHF ₃ , O ₂ and Ar.

  Next, a first electrode layer for forming a source electrode 7a, a drain electrode 7b, and a wiring (not shown) is formed. The first electrode layer may be Mo, Cr, W, Al, Ta, or an alloy film containing these as a main component. Moreover, it is good also as a multilayer structure which laminated | stacked these. In this embodiment, a Mo / Al / Mo laminated structure is used, and the film thickness is 200 to 400 nm for the Al film, and 50 to 150 nm for the Al lower layer and the upper Mo film. These were formed by a sputtering method using a DC magnetron.

Next, the formed first electrode layer is patterned into a desired shape using a known photoengraving method to form a source electrode 7a, a drain electrode 7b, and wiring (not shown). In the present embodiment, a dry etching method using a mixed gas of SF ₆ and O _{2 and} a mixed gas of Cl ₂ and Ar is used as a means for forming them. Through the above steps, the source region 3a and the source electrode 7a are electrically connected, and the drain region 3c and the drain electrode 7b are electrically connected.

The TFT 31 can be manufactured through these series of steps. Subsequently, a passivation film 8 is formed so as to cover the source electrode 7a and the drain electrode 7b, and after performing patterning by a series of photolithography processes, an etching process is performed. In this embodiment, the SiN film is formed by the CVD method so that the film thickness becomes 200 to 300 nm. A second contact hole 9a reaching the drain electrode 7b is formed from the surface of the passivation film 8. That is, in the second contact hole 9a, the passivation film 8 is removed and the drain electrode 7b is exposed. Etching of the second contact hole 9a was performed by a dry etching method using a mixed gas of CF ₄ and O ₂ .

Next, a second electrode layer for forming a pixel electrode or the like is formed. As the second electrode layer, a transparent conductive thin film such as ITO or IZO is used. In the present embodiment, ITO was formed by a sputtering method using a DC magnetron so as to have a film thickness of 80 to 120 nm. For sputtering, a mixture of Ar gas, O ₂ gas, and H ₂ O gas was used. Thereby, an amorphous transparent conductive thin film that is easy to process is obtained.

  Thereafter, the pixel electrode 10 was formed by patterning the formed second electrode layer into a desired shape using a known photolithography method. The etching process was performed by a wet etching method using a chemical solution mainly composed of oxalic acid. Then, annealing for crystallizing the amorphous transparent conductive thin film is performed. The pixel electrode 10 is connected to the drain electrode 7b through a contact hole. The TFT array substrate is formed by the above process.

  According to the method for manufacturing a semiconductor thin film according to the present embodiment, bumping can be eliminated similarly to the case where the surface of an amorphous semiconductor thin film is oxidized with ozone water. For this reason, the malfunction of the thin film transistor and the decrease in the breakdown voltage of the gate insulating film are eliminated, leading to improvement in reliability, improvement in yield, and improvement in quality.

  As described in Patent Documents 2 to 4, when surface oxidation is performed using ozone water, a spin cleaning apparatus is generally used. In this spin cleaning apparatus, equipment for generating ozone and dissolving ozone in pure water and equipment for injecting ozone water onto the glass substrate are required. For this reason, the structure where ozone water is not scattered outside and the equipment which processes a waste liquid are also required, and the enlargement of an apparatus is inevitable.

  According to the present invention, since the surface oxidation treatment is performed using ozone or / and oxygen radicals generated by irradiating the surface of the amorphous semiconductor thin film with ultraviolet rays, the apparatus configuration is very high. It is simple and can be downsized. If both ozone and oxygen radicals are used in combination, the surface oxidation treatment step can be completed in a short time. Further, since it can be oxidized dry, the surface of the amorphous semiconductor thin film can be uniformly oxidized without worrying about uneven oxidation or mist.

  According to the method for manufacturing a semiconductor thin film according to the present embodiment, a polycrystalline semiconductor thin film in which crystal grain boundaries appear in a lattice shape at substantially equal intervals can be obtained. That is, uniform crystal particles can be obtained. By arranging the crystal grain arrangement so as to be linear in the carrier movement direction, the crystal grain boundary on the orthogonal side becomes perpendicular to the carrier movement direction, and most carriers can proceed without changing the movement distance. As a result of suppressing variation in carrier mobility, fluctuations in driving capability and threshold value of the thin film transistor can be suppressed.

  When the semiconductor thin film according to this embodiment is applied to a TFT array substrate of a liquid crystal display device, the TFT is formed in a horizontal direction or a vertical direction. That is, the carrier movement direction of the semiconductor active layer is the horizontal direction or the vertical direction. Since the crystal grains are formed in a lattice shape, a difference in direction due to the arrangement of TFTs is less likely to occur, and fluctuations in the driving capability and threshold voltage performance of the thin film transistor can be suppressed. In addition, the energy density margin for obtaining a polycrystalline semiconductor thin film in which the crystal grain boundaries are substantially equidistant and appear in a lattice shape is wide. For this reason, it is possible to cover a slight change in the thickness of the amorphous semiconductor thin film and a range in which the laser oscillator can vary. In other words, since the energy density margin is high, fluctuations in transistor performance can be reduced. Furthermore, it has the merit that the device management becomes very easy and the productivity is improved.

  From the above, by applying the present invention, it is possible to provide a semiconductor thin film having improved reliability, yield, and quality, a manufacturing method thereof, a thin film transistor, and a semiconductor thin film manufacturing apparatus.

  In addition, although the example which uses an excimer laser as a light source of laser annealing was demonstrated, it is not limited to this. For example, the second harmonic (532 nm) of a YAG laser may be used. In the above-described embodiment, an example of amorphous silicon as an amorphous semiconductor thin film and an example of polycrystalline silicon as a polycrystalline semiconductor thin film have been described. However, the present invention is not limited thereto. Can be widely applied to other semiconductor thin films.

  In this embodiment, an example in which a TFT array substrate is mounted on a liquid crystal display device has been described. However, the present invention is not limited to this, and a flat surface such as an EL display device (organic EL display device or inorganic EL display device) is used. It can be suitably mounted on a mold display device (flat panel display). In the case of an organic EL display device, an anode electrode as a pixel electrode and a cathode electrode as a counter electrode are provided on the TFT array substrate 100. An organic layer is disposed between the anode electrode and the cathode electrode. Note that whether the pixel electrode is an anode electrode or a cathode electrode may be appropriately selected depending on the optical design.

  By supplying a current between the anode electrode and the cathode electrode, holes are injected from the anode electrode and electrons are injected from the cathode electrode into the organic layer to recombine. The molecules of the luminescent compound in the organic layer are excited by the energy generated at that time. The excited molecules are deactivated to the ground state, and the organic layer emits light in the process. Then, the light emitted from the organic layer is emitted to the viewing side. In order to propagate a desired current to the organic EL element, a drive circuit, a switching element, and a correction circuit are required, and a plurality of TFTs are formed. In particular, it is required to reduce fluctuations in driving capability and threshold voltage of these TFTs. Therefore, the present invention is particularly effective as a TFT array substrate mounted on an organic EL display device.

The typical top view showing the composition of the TFT array substrate concerning an embodiment. The flowchart for demonstrating the manufacturing process of the semiconductor thin film which concerns on embodiment. (A)-(c) is a manufacturing-process figure of the semiconductor thin film which concerns on embodiment. The typical explanatory view of the polycrystallized semiconductor thin film concerning an embodiment. Schematic explanatory drawing of the manufacturing apparatus of the semiconductor thin film which concerns on embodiment. Schematic explanatory drawing of the scattered light intensity measuring apparatus concerning an embodiment. The figure which plotted the value of the scattered light intensity with respect to the energy density at the time of laser annealing. The AFM photograph of the polycrystalline semiconductor which concerns on embodiment. Sectional drawing of the TFT area | region and capacitive element area | region of the TFT array substrate which concerns on embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Base film 3 Semiconductor active layer 3A Amorphous semiconductor thin film 3B Grain boundary 3C Crystal grain 3a Source region 3b Channel region 3c Drain region 3d Lower electrode 4 Gate insulating film 5a Gate electrode 5b Upper electrode 6 Interlayer insulation Film 7a Source electrode 7b Drain electrode 8 Passivation film 9 Contact hole 10 Pixel electrode 11 Gate signal line 12 Scan signal driving circuit 13 First external wiring 14 Storage capacitor wiring 20 Laser light 21 Source signal line 22 Display signal driving circuit 23 Second external Wiring 30 Pixel 31 TFT region 32 Storage capacitor element region 40 Display region 41 Frame region 50 Semiconductor thin film manufacturing device 51 Substrate carry-in / out unit 52 Transport means 53 Surface oxidation unit 54 Laser annealing unit 60 Scattered light intensity measurement device 61 White LED
62 Lens 65 Black tube 66 Light receiving unit 100 TFT array substrate

Claims (8)

Forming an amorphous semiconductor thin film on a substrate;
Removing a natural oxide film formed on the surface of the amorphous semiconductor thin film;
After removing the natural oxide film, subjecting the surface of the amorphous semiconductor thin film to surface oxidation treatment with ozone or / and oxygen radicals generated by ultraviolet irradiation;
Laser annealing for irradiating the amorphous semiconductor thin film with a laser beam in an inert gas atmosphere to obtain a polycrystalline semiconductor thin film having crystal lattice boundaries with substantially regular intervals and a lattice-like periodic structure A process,
In the laser annealing step, the optimum laser light for obtaining a polycrystalline semiconductor thin film by performing laser annealing immediately after the step of removing the natural oxide film without going through the step of performing the surface oxidation treatment A method for producing a semiconductor thin film, wherein the laser light irradiation is performed at an energy density lower than the energy density by a predetermined energy density. In the manufacturing method of the semiconductor thin film of Claim 1,
A method for producing a semiconductor thin film, comprising: a step of removing an oxidized portion on a surface of the semiconductor thin film and a step of cutting a protruding portion after the laser annealing step. In the manufacturing method of the semiconductor thin film of Claim 1 or 2,
A method for producing a semiconductor thin film, wherein the amorphous semiconductor thin film is amorphous silicon, and the polycrystalline semiconductor thin film is polycrystalline silicon. A semiconductor thin film polycrystallized by the method for producing a semiconductor thin film according to claim 1, 2 or 3,
An interval between adjacent crystal grain boundaries is 300 nm or more and 400 nm or less,
The crystal grain boundary protrudes in a protruding shape from a flat portion of the crystal grain divided by the crystal grain boundary, and the height of the protrusion is 60 nm or less,
A semiconductor thin film in which the polycrystalline semiconductor thin film has a surface roughness Ra of 10 nm or less.   A thin film transistor array substrate comprising the semiconductor thin film according to claim 4 in a semiconductor active layer.   A method for producing a thin film transistor array substrate, comprising obtaining a polycrystalline semiconductor thin film by the method for producing a semiconductor thin film according to claim 2, and further subjecting the semiconductor thin film to surface oxidation treatment. An apparatus for manufacturing a semiconductor thin film used in the method for manufacturing a semiconductor thin film according to claim 1, 2 or 3,
A surface oxidation unit used in the step of performing the surface oxidation treatment,
The surface oxidation unit includes an irradiation light source that emits ultraviolet rays that generate ozone or / and oxygen radicals in an oxygen gas atmosphere;
An apparatus for manufacturing a semiconductor thin film, comprising an irradiation unit for irradiating the amorphous semiconductor thin film with the ultraviolet light. In the manufacturing apparatus of the semiconductor thin film of Claim 7,
A laser annealing unit used for the laser annealing step is provided,
The apparatus for producing a semiconductor thin film, wherein the laser annealing unit is disposed in-line from the surface oxidation forming unit using a conveying means.