JP2009113325A - Inkjet recording device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To share a board with a plurality of types of machine by sharing a main board circuit. <P>SOLUTION: A long flexible I/F signal is shared with a one-head machine and a two-head head machine. Data transferred to a recording head is serialized on a main board and data for a plurality of head is transferred with a signal line for one head. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an inkjet recording apparatus and a recording method thereof, and more particularly to a method of transmitting image data to a recording head.

  An ink jet printer forms an image on a recording sheet by alternately repeating an operation of ejecting ink droplets onto a medium and an operation of conveying the recording sheet while the recording head reciprocates in the main scanning direction.

  The recording head is mounted on a unit called a carriage, and a carriage substrate for receiving print data transmitted from a host interface or a main substrate that performs image processing is mounted on the carriage. The print data is sent to the recording head via the carriage substrate, and the transfer method of the print data signal is one clock signal, a data signal synchronized with the clock signal, and a latch signal for determining the data. Consists of three types of signal lines.

In addition, when using a plurality of recording heads having the same interface, as a technique for transmitting recording data, a method of serially transmitting data of a plurality of recording heads in a time division manner using a common data line is known. (See Patent Document 1). With this method, even when a large number of recording heads are used, data can be efficiently transmitted with a small number of signal lines.
Japanese Patent No. 3142698

  For example, when a main board is used in common for a model that uses a single recording head and a model that uses two recording heads, the main board and carriage It is necessary to provide a number of interface signals between them.

  In this case, for a model using a single recording head, it is necessary to prepare a connector, a cable, and an interface circuit that are not used, which may incur unnecessary costs.

  When the method according to the above-mentioned Japanese Patent No. 3142698 is used, the data transfer speed is constant regardless of the number of recording heads. Therefore, in order to perform data transfer for multiple print heads, despite the fact that only a single print head is installed, it is necessary to construct a signal transmission system that is faster than necessary. There is a problem that you have to apply. Furthermore, there is a problem that radiation noise increases.

  In order to solve the above-described problems, the present invention is characterized in that data is transferred to a recording head using a common signal line regardless of the number of recording heads mounted. That is, when a single head is mounted, serial data is transferred using the conventional interface, and when multiple heads are mounted, the clock cycle is set to the number of recording heads in synchronization with the clock signal. The data is divided and output to a common data signal while switching the data signal of each print head, and data for a plurality of print heads is sent out by common hardware in a time division manner.

  By sharing the clock signal and data signal, it is possible to support driving of a plurality of recording heads, so that the same circuit can be applied to a plurality of models, and the cost of the substrate can be reduced. .

  When multiple recording heads are installed, the serial data is time-divided by the number of recording heads, so the timing of the clock signal and data signal becomes stricter, and the data receiving circuit and data transfer for that amount. High accuracy is required by the cable, but there is an effect of reducing the number of signal lines of the interface. On the other hand, when a single recording head is installed, compared to the case where multiple recording heads are installed, Since there is little change in the data signal, there is little radiation noise, and there is a margin in timing, so it is not necessary to spend the cost.

  As described above, even in a model having a different number of print heads, data transfer to the optimum print head can be performed.

  Hereinafter, an embodiment of a printing apparatus embodying the present invention will be described with reference to the drawings.

  FIG. 1 is a view showing the appearance of an ink jet printer using a single head.

  In FIG. 1, a carriage 101 has a recording head 102 and a carriage substrate 111 mounted thereon. The carriage 101 is driven by a carriage motor (not shown) and reciprocates in a direction perpendicular to the recording medium conveyance direction. Further, in order to detect the position of the carriage, a linear scale 104 is disposed along the moving direction of the carriage 101, and a slit of the linear scale 104 is detected by a linear scale sensor 103 provided on the carriage 101. The recording head is mounted on the carriage 101 and ejects ink at a timing based on the output timing of the linear scale sensor 103 while the carriage 101 reciprocates. Ink ejection data signals and power to the recording head are supplied from the electric circuit of the main body via the cable 105.

  FIG. 16 is a view showing the appearance of an ink jet printer using two heads. The difference from FIG. 1 is that two identical recording heads, a recording head 1112 and a recording head 2 113, are mounted.

  The recording medium is transported on the platen 109 by the transport motor 107. The image formation of one sheet is realized by alternately repeating the reciprocating motion of the carriage 101 and the conveyance of the recording medium.

  FIG. 2 shows an electrical configuration of the ink jet printer according to the present invention. Here, first, it is assumed that two recording heads A and B are mounted on the recording head. The main board 201 controls the entire apparatus such as driving of the host I / F, each motor, and the recording head, and is connected to the carriage board 111 by the cable 105. The carriage substrate receives the print data signal sent from the main substrate and transmits the head data signal to the recording head 102.

  FIG. 3 shows a data transfer chart of the recording head 102. Even if the number of recording heads increases, the data transfer interface of the recording heads is the same. As shown in FIG. 3, three types of signals, clock, serial data, and latch, are connected to this recording head. A parallel register of 8 bits per serial data line is provided by a shift register inside the recording head. Converted to data, print data is formed. The number of serial data lines varies depending on the resolution of the recording head, the number of ink colors, etc. Even if the number of data lines per recording head changes or the number of bits of serial data changes, It does not change the essence of the present invention.

  FIG. 4 specifically shows a print data transmission circuit on the main board 201 side in the present invention. According to FIG. 4, when the CLK signal is at the “L” level, the DATA_A signal as the DATA signal, that is, the serial data of the recording head A, and when the CLK signal is at the “H” level, the DATA_B signal as the DATA signal, that is, the recording. The serial data of head B is selected and transmitted.

  FIG. 5 shows a timing chart of each signal in the circuit of FIG. As shown in FIG. 5, it can be seen that the two recording head data are switched in synchronization with the rise and fall of the CLK. Considering the waveform of FIG. 5, the DATA signal at the rising edge of the CLK signal indicates the DATA signal of the recording head A, and the DATA signal at the falling edge of the CLK signal indicates the data of the DATA signal of the recording head B. become.

  FIG. 6 shows a recording head I / F circuit of the carriage substrate 111. As described above, the CLK, DATA, and LT signals output from the main board may be connected to the recording head A as they are, and the CLK signal of the recording head B is converted into a rising edge by way of the inverter 601. Is typing.

  7A and 7B are timing charts of signal lines input to the recording head A and FIG. 7B to the recording head B. FIG. For the recording head A, the serial data DATA can be input as it is because the data of the recording head A is transferred at the rising edge of the CLK signal, and the serial data of the recording head B is transferred at the falling edge of the CLK signal. Therefore, the inverted signal CLK ′ of the CLK signal is input as the transfer CLK.

  As described above, when two recording heads are mounted, it is possible to use the interface signal line for outputting data transmission of two recording heads to one recording head as it is.

  When only one print head is mounted, data transfer is performed with a normal print head interface. Even in this case, the number of signal lines of the interface is the same as in the case of two recording heads. In this way, the main board can be shared by a model equipped with one recording head and a model equipped with two recording heads.

  Next, a method for determining whether one recording head or two recording heads are mounted will be described.

  According to the above-described embodiment, it is possible to share the main board. However, when the carriage board is equipped with two recording heads compared with the case where one recording head is installed, the interface signal The number of lines will double. Therefore, the carriage substrate cannot be used in common. Therefore, if the type of carriage substrate is known, the number of recording heads can be determined.

  FIG. 8 shows an embodiment of a method for determining the number of recording heads using the carriage substrate. FIG. 8A relates to a method of determining the number of mounting heads when one recording head is mounted, and FIG. 8B relates to the number of mounting heads when two recording heads are mounted. First, a circuit on the main board side will be described. A CPU is mounted on the main board, and a pull-up resistor is connected to a general-purpose port of the CPU and is passed to the carriage board as a mounting head discrimination signal. The circuit of this part is common to FIGS. 8A and 8B. In FIG. 8A, the mounting head discrimination signal is connected to the ground on the carriage substrate, and the mounting head discrimination signal becomes 'L' level. In FIG. 8B, the mounting head discrimination signal is the carriage substrate. The mounted head discriminating signal becomes “H” level. On the main board, the type of carriage board can be determined by determining whether this mounted head determination signal is at the 'H' level or the 'L' level, and the number of connected print heads Can know.

  As another method, if the number of recording heads to be installed is determined according to the model, it is also possible to transfer the head data in a specific transfer mode within each firmware separately for each firmware. It is.

  Since the number of recording heads can be detected in this way in advance, when transferring head data to the recording head, by changing the head data transfer mode according to the determined number of recording heads, Whether the number of recording heads is one or two, data can be transferred using a common main board.

  As another embodiment of the present invention, a data transfer method in the case of using a recording head that transfers data in synchronization with rising and falling of a clock signal as shown in FIG. 9 will be described.

  FIG. 10 shows a data transmission circuit. This is the same as the data transmission circuit of the previous embodiment. When the CLK signal is at the “L” level, the DATA_A signal as the DATA signal, that is, the serial data of the recording head A, and when the CLK signal is at the “H” level, the DATA_B signal, that is, the serial data of the recording head B, as the DATA signal. Select and send. Only the CLK, DATA, and LT signals are sent to the carriage substrate 111.

  FIG. 11 shows a timing chart of each part in the circuit of FIG. As shown in FIG. 11, the DATA signal to be transferred is alternately selected by the recording head A and the recording head B in accordance with the level of the CLK signal.

  FIG. 12 shows a data receiving circuit of the carriage substrate 111 when two recording heads are mounted in this embodiment. In FIG. 12, the CLK signal is first connected to the delay circuit 1, and the output signal of the delay circuit 1 is the DELAY_CLK signal. A signal obtained by logically summing the CLK signal and the DELAY_CLK signal is set as CLK_A as a data transfer clock signal of the recording head A, and a signal obtained by calculating a logical product of the CLK signal and the DELAY_CLK signal is set as CLK_B. It is said. The DATA signal is output to the recording head A and the recording head B through the delay circuit 2 as an output of the DATA signal as a DELAY_DATA signal. Here, it is assumed that the delay time of the delay circuit 1 is shorter than the delay time of the delay circuit 2, and the delay times of the delay circuit 1 and the delay circuit 2 are shorter than ½ period of CLK.

  FIG. 13 is a timing chart showing the operation of the circuit of FIG. Hereinafter, the operation of the receiving circuit of FIG. 12 will be described with reference to FIG.

  The CLK signal and the DATA signal transferred from the main board become DELAY_CLK and DELAY_DATA by the respective delay circuits. Considering the timing at which the recording head A captures the serial data, first, the timing for capturing the “D0A” data is the rising edge of the DELAY_DATA signal at the rising edge of the CLK signal, and the timing for capturing the “D1A” data is Latch at the falling edge. A signal obtained by ORing the CLK signal and the DELAY_CLK signal is defined as a CLK_A signal. The CLK_A signal rises at the rising edge of the CLK signal and falls at the falling edge of the DELAY_CLK signal. Since the recording head captures serial data at the rising and falling edges of the CLK signal, serial data transfer can be performed by outputting the DELAY_DATA signal as the DATA signal and the CLK_A signal as the CLK signal to the recording head A. .

  Considering the recording head B in the same manner, the data transfer timing of the recording head B may be transferred at the rise of the DELAY_CLK signal and the fall of the CLK signal, and the logical product of the CLK signal and the DELAY_CLK signal is obtained. Generates a signal that realizes rising / falling at the above timing by making the signal CLK_B, and outputs serial data transfer by outputting the DELAY_DATA signal as the DATA signal and the CLK_B signal as the CLK signal to the recording head B I do.

  Next, an implementation example of the delay circuit will be specifically described.

  FIG. 14 shows a delay circuit using a resistor and a capacitor. The delay time can be arbitrarily set by changing the constants of the resistor and the capacitor, and is the simplest delay circuit. Since there is an input capacitance in the recording head, there is a case where only a damping resistor may be used as a capacitor without special provision.

  FIG. 15 shows a delay circuit using a buffer. A delay time is generated from the change of the input signal to the response of the output signal depending on the switching time of the transistors in the buffer. The delay time can be adjusted according to the number of buffers to be inserted. In FIG. 15, a non-inveting buffer is used. Even if an even number of inverters are connected, the functions are equivalent.

Represents the appearance of the ink jet recording apparatus in this embodiment An electric block diagram of a two-head mounted ink jet recording apparatus in this embodiment is shown. 1 represents a data transfer timing chart of the recording head of the first embodiment. 1 represents a data transmission circuit on the main board side of the first embodiment. 2 shows a data transmission timing chart on the main board side of the first embodiment. 1 represents a data receiving circuit on the carriage board side of the first embodiment. 2 shows a timing chart of a data transfer signal input to each recording head of the first embodiment. 2 represents a determination circuit for the number of mounted recording heads in the invention. 2 shows a data transfer timing chart of the recording head of the second embodiment. 2 represents a data transmission circuit on the main board side of the second embodiment. The data transmission timing chart by the side of the main board of the 2nd example is expressed 2 shows a data receiving circuit on the carriage board side of the second embodiment. 2 shows a timing chart of a data transfer signal input to the recording head of the second embodiment. An example of the delay circuit of the second embodiment is shown. Represents another example of the delay circuit of the second embodiment; The figure which shows the external appearance of the inkjet printer using two heads.

Explanation of symbols

101 Carriage
102 Recording head
103 linear scale sensor
104 linear scale
105 cable
106 plates
107 Conveyor motor
108 Transport roller
109 platen
110 Recording media
111 Carriage board
112 Recording head 1
113 Recording head 2
201 Main board

Claims (2)

An inkjet recording apparatus that ejects ink according to a serial data signal transferred in synchronization with a clock signal,
Detecting means for detecting the number of mounted recording heads;
When multiple heads are installed, data transfer is performed while switching the common data signal to the data signal sent to the corresponding head at predetermined time intervals according to the number of recording heads, and the common data signal and clock signal are transferred. An ink jet recording apparatus comprising: means for transferring print data by use.   2. The ink jet recording apparatus according to claim 1, wherein when two heads are mounted, a time interval for switching the data signal is set to a half of a data transfer cycle when a single head is mounted.

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