JP2009111304A - Overvoltage protection function built-in MOS semiconductor device and manufacturing method thereof. - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance destructive resistance caused by overvoltage in an MOS semiconductor apparatus which has a Zener diode between drain and gate for overvoltage protection. <P>SOLUTION: The overvoltage protective function built-in MOS semiconductor apparatus includes an n-type region 17 which is deeper than a well 4 of a main IGBT or an MOSFET and is formed on a surface of a drain region 16 electrically connected to a Zener diode 16. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an improvement of a MOS type semiconductor device having a built-in structure for preventing breakdown of a semiconductor device due to the overvoltage when an overvoltage is applied to the IGBT or power MOSFET which is a gate drive type vertical power MOS type semiconductor device. .

  In the prior art, a configuration in which a plurality of Zener diodes or bidirectional Zener diodes are connected in series between a collector (or drain) and a gate is widely known as overvoltage protection for a single MOS type semiconductor device such as IGBT or MOSFET. Yes. FIG. 9 is a cross-sectional view of a main part of a MOS semiconductor device incorporating such a bidirectional Zener diode, and FIG. 10 is an equivalent circuit diagram of a MOS semiconductor device including an overvoltage protection device including the bidirectional Zener diode. Are shown respectively. As shown in the equivalent circuit of FIG. 10, a Zener diode 33 designed to break down at a breakdown voltage lower than the breakdown voltage of the main MOS type semiconductor device 30 is provided between the drain and the gate. As a result, when a surge voltage higher than the withstand voltage of the main MOS type semiconductor device 30 is applied, the Zener diode 33 breaks down and a current flows. At that time, the gate electrode of the MOS semiconductor device 30 is biased to be turned on, and an on-current flows to the collector (or drain), so that a large surge energy is absorbed by the entire MOS semiconductor device. . The Zener diode is monolithically formed of polysilicon or the like through an insulating film between a collector (drain) and a gate on a single chip of a MOS type semiconductor device, as indicated by reference numeral 16 in FIG.

In such a MOS type semiconductor device, when an overvoltage is applied to the main drain electrode, a Zener reversely connected in series between the drain and gate via the on-current of the second (sub) MOS type semiconductor device. A structure is known in which a main MOS semiconductor device is protected from an overvoltage by turning on the main MOS semiconductor device through a diode (Patent Document 1).
Also, a structure is known in which a Zener diode is connected between the collector and gate of the IGBT that is 100 V or more lower than the IGBT breakdown voltage and has an operating resistance of 5 kΩ or less at a current value of 10 to 20 mA (Patent Document 2).
The known structure of the IGBT including a reverse conducting diode provided to improve the reverse surge withstand capability of the IGBT is damaged when the power supply voltage is erroneously connected in the reverse direction between the collector and the emitter. In order to solve this problem, it is known to connect a resistor between the reverse conducting diode and the collector (Patent Document 3).
In order to prevent an increase in on-resistance due to an up-drain MOSFET, a method is described in which a deep and high-concentration n ⁺ layer provided on the surface is formed using a trench without increasing the area ( Patent Documents 4 and 5).
Japanese Patent Laid-Open No. 10-321857 (paragraph 0011, FIG. 1) JP 2001-153011 A (summary, FIG. 1) JP 2006-332182 (paragraph 0011, abstract) JP 2001-127294 A (summary) JP 2004-363302 A (paragraphs 0007 to 0009)

However, as shown in the equivalent circuit of FIG. 10 described above, a Zener diode 33 designed to break down at a breakdown voltage lower than the breakdown voltage of the main MOS type semiconductor device 30 is provided between the drain and the gate. With IGBTs, a high surge resistance can be obtained, but it has been found that the following disadvantages may occur.
First, as shown in FIG. 9, the IGBT mainly includes a high resistance drift layer 3 below a surface layer of a semiconductor substrate provided with a drain region 7 electrically connected in series with the Zener diode 16. Thus, the resistor 13 is inserted equivalently. The Zener diode 16 can be designed in advance by changing the resistivity, cross-sectional area, and length of the pn diffusion layer. However, the resistor 13 mainly composed of the drift layer (semiconductor substrate) 3 is a semiconductor device. A dicing cut surface of a single chip is included, and the resistance value is not constant depending on the state of the cut surface. In addition, since the resistivity of the semiconductor substrate itself is closely related to the design withstand voltage value and is subject to the restrictions, it is difficult to select the resistivity for the purpose of setting an arbitrary resistance value regardless of the design withstand voltage value. There is an inconvenience. This means that when a very fast surge of 1 μs or less is applied, the potential of the front-side drain electrode 8 cannot follow the voltage due to the charging time of the resistor 13 and the voltage rise is delayed. In this case, a high voltage is instantaneously applied between the Zener diode 16 and the semiconductor surface immediately below the Zener diode 16, which causes dielectric breakdown of the oxide film 20. Further, since the surface of the oxide film 20 is not particularly protected from the outside, it is expected that the surface state changes due to the influence of various external ions and the like, and the surface resistance value also changes. Problems can also arise from the point of view. 9 shows a cross section in a state where the Zener diode 16 is placed on the oxide film 20, but the portion where the Zener diode 16 is placed on the oxide film 20 is the surface of the oxide film 20. This is because it is only a small part.

Further, particularly in the case of an IGBT, there is a collector layer 1 made of a p region on the back side of a semiconductor single chip, and a forward pn diode 14 is formed by this p region. For this reason, when a surge voltage enters and current starts to flow through the Zener diode 16, a forward current flows through the pn diode 14 consisting of reference numerals 1, 2, 3, and 7 existing on the semiconductor substrate side. Holes are injected from the anode side, that is, the collector C side, and also flow through the semiconductor substrate to the IGBT active region (region where the main current flows) side through the path 12. The current also flows in the IGBT in the sense that the resistance between the gate G and the collector C is lowered. On the other hand, it has a good effect. There is a problem that it takes about several μs until the conductivity modulation in the layer 3) is completed, and it is difficult to control the path through which the current flows. This means that when the IGBT enters an avalanche breakdown state and an avalanche current flows, a large amount of current may be concentrated in the peripheral portion of the IGBT, leading to a reduction in breakdown resistance.
The present invention has been made in view of the above-described problems, and an object of the present invention is to further provide a breakdown tolerance due to overvoltage in a MOS semiconductor device having a Zener diode for overvoltage protection between a drain and a gate. An object is to provide an improved MOS semiconductor device.

According to the first aspect of the present invention, the other conductivity type base region and the surface layer in the other conductivity type base region are selectively formed on one main surface of the one conductivity type semiconductor substrate. A source region, and a MOS gate structure including a gate electrode placed on a surface of the other conductivity type base region sandwiched between the source region surface and the one conductivity type semiconductor substrate surface via a gate insulating film, Further, the one main surface includes a breakdown voltage structure portion surrounding the MOS gate structure and a one-conductivity type drain region surrounding the breakdown voltage structure portion, and a Zener diode is electrically connected between the drain region surface and the gate electrode. In the overvoltage protection type MOS semiconductor device having a structure in which a main current flows between the one main surface and the other main surface, the one conductivity type drain region includes the MOS gate The overvoltage protection function built-in type MOS semiconductor device in which the other conductivity type base region depth from the one main surface than that constitute the granulation is formed as a deep region.
According to the second aspect of the present invention, the depth of the one conductivity type drain region reaches the diffusion region formed on the other main surface. The overvoltage protection function built-in MOS semiconductor device described above is used.
According to a third aspect of the present invention, the one conductivity type low resistance layer in which the one conductivity type drain region and the diffusion region formed in the other main surface are formed along a cut surface. An overvoltage protection function built-in MOS semiconductor device according to claim 1 is connected.

According to the invention of claim 4, the one-conductive type low resistance layer formed along the cut surface is formed by laser dicing performed in a phosphorus atmosphere. The manufacturing method of the MOS type semiconductor device with built-in overvoltage protection function according to 3.
According to the invention of claim 5, the one conductivity type low resistance layer formed along the cut surface is formed by ion implantation and subsequent heat treatment after dicing. According to a third aspect of the present invention, there is provided a method for manufacturing an overvoltage protection function built-in MOS semiconductor device.
According to the invention described in claim 6, it is selectively formed on one main surface of the one conductivity type semiconductor substrate on the other conductivity type base region and the surface layer in the other conductivity type base region. A source region, and a MOS gate structure including a gate electrode placed on a surface of the other conductivity type base region sandwiched between the source region surface and the one conductivity type semiconductor substrate surface via a gate insulating film, Further, the one main surface includes a breakdown voltage structure portion surrounding the MOS gate structure and a one-conductivity type drain region surrounding the breakdown voltage structure portion, and a Zener diode is electrically connected between the drain region surface and the gate electrode. In an overvoltage protection function built-in MOS semiconductor device having a structure in which a main current flows between the one main surface and the other main surface, formed on one main surface of the one-conductivity-type semiconductor substrate. A trench formed in the drain region surface, the overvoltage protection function built-MOS type semiconductor device having one conductivity type diffusion layer formed on the inner surface of the trench.

According to the seventh aspect of the present invention, the overvoltage protection function built-in MOS semiconductor device according to any one of the first to sixth aspects or the Let it be a manufacturing method.
According to the invention described in claim 8, the overvoltage protection function built-in MOS semiconductor device according to any one of claims 1 to 6, or a semiconductor device thereof, wherein the semiconductor device is an IGBT. Let it be a manufacturing method.
In short, in the present invention, in order to achieve the object of the invention, (1) an n-type region deeper than the well diffusion of the main IGBT or MOSFET is formed on the drain side surface electrically connected to the Zener diode. Relating to claims 1, 2, 7, 8 of the claims. Related to FIGS. (2) A high concentration n-type impurity diffusion region is formed on the end face of the semiconductor chip electrically connected to the Zener diode. Related to claims 3, 4, 5, 7, 8 of the claims. Related to FIGS. (3) A trench groove is formed from the drain side surface electrically connected to the Zener diode, and a high concentration n-type region is formed on the bottom and side surfaces thereof. Related to claims 6, 7, 8 of the claims. Related to FIG. The present invention provides an overvoltage protection function built-in MOS semiconductor device having a configuration characterized by any one of (1), (2), and (3) or a method for manufacturing the same.

  According to the present invention, in a MOS semiconductor device having a Zener diode for overvoltage protection between a drain and a gate, it is possible to provide a MOS semiconductor device that can further improve the breakdown tolerance due to overvoltage.

Preferred embodiments of an overvoltage protection function built-in MOS semiconductor device and a method for manufacturing the same according to the present invention will be described below in detail with reference to the accompanying drawings. Hereinafter, in the description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and overlapping descriptions are avoided as much as possible. Moreover, this invention is not limited to description of the Example demonstrated below, unless the summary is exceeded.
1-3 is principal part sectional drawing of IGBT concerning Example 1 of this invention. 4 to 6 are cross-sectional views of main parts of an IGBT according to Example 2 of the invention. 7 and 8 are cross-sectional views of the main part of an IGBT according to Example 3 of the present invention.

FIG. 1 is a cross-sectional view of the main part showing the basic structure of an IGBT according to Example 1 of the present invention. In the description of the first embodiment using the IGBT, the basic structure and manufacturing method of the IGBT itself are the same as the well-known structure and manufacturing method. Therefore, the detailed description is omitted and is closely related to the characteristic part of the present invention. The explanation will focus on the part. In the first embodiment, an IGBT including a Zener diode 16 connected in a direction in which an anode is a gate and a cathode is a collector (drain) side between a gate G and a collector C, and an end portion on the collector side of the Zener diode 16 is provided. In order to reduce the internal resistance of the portion of the semiconductor substrate 3 that is electrically connected in series with the Zener diode 16 between the drain electrode 8 in contact with the collector C and the collector C, a high-concentration n-type diffusion region 17 is It is formed by deep impurity diffusion from the surface of the semiconductor substrate with which the drain electrode 8 contacts. In the following description, the Zener diode is preferably a bidirectional Zener diode formed of polysilicon. In the description, the term “concentration” refers to the impurity concentration. The high-concentration n-type diffusion region 17 has a surface concentration of 1 × 10 ¹⁹ cm ⁻³ or more, and the depth thereof is a p base region 4 (forming a MOS gate structure in an active region through which the main current of the main IGBT flows. It is necessary to make it deeper than the depth of the p-well region, and substantially 5 μm or more. In practice, it is preferable to make the depth as deep as the thickness of the drift layer 3. For example, in the case of an IGBT with a withstand voltage of 600 V, the thickness of the drift layer 3 is about 50 μm, and if possible, it should be 20 μm or more. preferable. In the IGBT of FIG. 1, the depth of the high concentration n-type diffusion region 17 reaches the buffer layer 2. FIG. 2 shows a case where the buffer layer 2 has not been reached. FIG. 3 shows a case where it reaches even deeper than FIG. 1 and reaches the collector layer on the back surface side. 1 is a collector layer, 2 is a buffer layer, 3 is a drift layer, 4 is a p base region, 5 is a gate oxide film, 5-1 is a gate electrode, 6 is an emitter electrode, 8 is a drain electrode, 9 Is a gate resistance, and 10 is a G-K capacitance. These symbols for the IGBT are common to other figure numbers.

  The manufacturing method of the characteristic part of this invention is demonstrated with reference to FIG. 4 about the manufacturing method of IGBT concerning Example 1 of this invention. An oxide film 21 is formed on the surface of the semiconductor substrate as a diffusion mask (FIG. 4A). The opening 22 is formed by a photolithography process (FIG. 4B). By this opening window, a deep n-type diffusion region 17 having a high concentration is selectively formed using phosphorus, which is an n-type impurity, by ion implantation, vapor phase diffusion, or solid phase diffusion method (FIG. 4C). . The oxide film 21 is removed (FIG. 4D). The subsequent steps are in accordance with a normal IGBT or MOSFET manufacturing method. At this time, the diffusion depth and surface concentration of the n-type diffusion region 17 can be controlled by the diffusion time and the diffusion temperature. The diffusion depth is as deep as possible and preferably a high concentration. However, for this purpose, the diffusion temperature becomes high and the diffusion time also becomes long. Therefore, it is necessary to decide in accordance with the process design. It should be noted that as the depth increases, the n-type diffusion region 17 spreads in the horizontal direction to the same extent, so that the peripheral region of the device increases, which is disadvantageous in terms of device size.

FIG. 5 is a cross-sectional view of the main part showing the basic structure of an IGBT according to Example 2 of the present invention. This IGBT is an IGBT including a Zener diode 16 connected in a direction in which an anode is a gate between a gate G and a collector C and a cathode is a collector (drain) side, and the Zener diode 16 has an end on the collector side. Same as the IGBT of the first embodiment in that a high concentration n-type diffusion region is formed on the surface of the semiconductor substrate between the drain electrode 8 and the collector C that are in contact with each other and the drain electrode 8 is in contact with the surface. However, in Example 2, the depth of the high-concentration n-type diffusion region 7 by diffusion from this surface may be shallower than that in Example 1, and instead, in Example 2, on the cut end surface of the semiconductor substrate end, The difference is that it has an n-type region 18 formed by directly introducing impurities.
The manufacturing method is shown in the sectional view of the main part of the IGBT in FIG. When the main IGBT or MOSFET wafer manufacturing process is almost completed and the wafer is diced in order to cut the wafer and take out the chips, laser dicing is performed in an atmosphere containing phosphorus. At this time, a large amount of energy is injected into the semiconductor substrate by the laser and locally becomes high temperature, and the semiconductor substrate becomes liquid or is removed by evaporation. An n-type region 18 formed by being taken into the cut surface of the substrate is formed on the dicing cut surface. Alternatively, after dicing mechanically with a dicer using a normal diamond blade, before cutting into chips with an expander, phosphorus ions are implanted into the cut surface and heat treatment at about 400 ° C. is performed. You can also. In these methods, an n-type conductive layer having a low resistance can be easily formed on the cut surface of the semiconductor substrate, which is simpler than the manufacturing method of Example 1 of the present invention. However, the above-described method shown in FIG. 6 has a demerit that variation in resistance increases because it is difficult to control the amount of impurities actually introduced into the semiconductor.

FIG. 7 is a cross-sectional view of the main part showing the basic structure of an IGBT according to Example 3 of the present invention. This IGBT is an IGBT including a Zener diode 16 connected in a direction in which an anode is a gate between a gate G and a collector C and a cathode is a collector (drain) side, and the Zener diode 16 has an end on the collector side. A trench 50 having a depth penetrating the diffusion region 7 is formed on the surface of the semiconductor substrate between the drain electrode 8 and the collector C which are in contact with each other and the drain electrode 8 is in contact. In this structure, a relatively shallow n-type diffusion layer 18-1 is formed on the inner surface of the substrate to replace the high-concentration deep n-type diffusion region 17 of Example 1 and the n-type region 18 of Example 2. The manufacturing method.
According to this structure or the manufacturing method thereof, since the deep diffusion region 17 as in the first embodiment of the present invention is not required, there is an advantage that the production throughput is improved. The deeper the trench 50, the deeper the n-type region 18-1. In FIG. 7, the depth of the trench 50 does not reach the buffer layer 2, but it is preferable to set the depth so as to reach the buffer layer 2 or the collector layer 1. However, in that case, for example, in the case of a device of 600 V, since the drift layer 3 is about 50 μm, it is necessary to form a deep trench 50 of 50 μm or more. In FIG. 8, the characteristic part of the manufacturing method of IGBT of Example 3 was shown. The trench 27 is formed on the surface in the drain region 7 using the etching mask 26 on the wafer at the stage where the manufacturing process of the IGBT or MOSFET is almost completed (FIG. 8A). ). An n-type region 29 is formed on the inner surface of the trench 27 by ion implantation 28 (FIG. 8C) or vapor phase diffusion (FIG. 8D). At this time, it is preferable that the formed n-type region 29 has a high concentration of 1 × 10 ¹⁹ cm ⁻³ or more.

In the first, second, and third embodiments, the IGBT has been described as an example. However, a similar structure is possible in the MOSFET, and the same effect can be obtained. In particular, in the case of a MOSFET, since there is no minority carrier injection from the back side, conductivity modulation does not occur, and even if a current flows through the Zener diode, the resistance in the MOSFET substrate does not decrease. For this reason, the effect by reducing the resistance between the GC and the resistance of the semiconductor substrate is particularly great.
According to the first, second, and third embodiments described above, it is possible to effectively reduce the resistance on the semiconductor substrate side connected in series with the Zener diode, and it is possible to sufficiently protect against a fast surge. Become. In addition, in the case of an IGBT, the current flowing through the Zener diode can be limited to the newly added n-type region, so that unnecessary current diffusion can be prevented, current concentration can be prevented, and breakdown resistance can be reduced. Can be prevented.

  As described above, the MOSFET or IGBT with an overvoltage protection function according to the present invention is useful as various power switches such as an automobile igniter in which surge frequently occurs or a switch for relay replacement.

It is principal part sectional drawing of IGBT concerning Example 1 of this invention. It is principal part sectional drawing of the example of a variation | mutation of IGBT concerning Example 1 of this invention. It is principal part sectional drawing of the example of a variation | mutation of IGBT concerning Example 1 of this invention. It is sectional drawing for every main manufacturing processes for demonstrating the manufacturing method of Example 1 of this invention. It is principal part sectional drawing of IGBT concerning Example 2 of this invention. It is sectional drawing for every main manufacturing processes for demonstrating the manufacturing method of Example 2 of this invention. It is principal part sectional drawing of IGBT concerning Example 3 of this invention. It is sectional drawing for every main manufacturing process for demonstrating the manufacturing method of Example 3 of this invention. It is principal part sectional drawing of IGBT which has the conventional overvoltage protection structure. It is the equivalent circuit of IGBT which has the conventional overvoltage protection structure.

Explanation of symbols

1 collector layer 2 buffer layer 3 drift layer 4 p base region 5 gate insulating film 5-1 gate electrode 6 emitter electrode 7 drain region 8 drain electrode 9 gate resistance 10 G-K capacitance 12 path 13 resistor 16 Zener diode 17 deep n-type diffusion layer 18 n-type diffusion layer 20, 21 oxide film 22 opening 26 dry etching mask 27 trench 28 phosphorus ion implantation 29 n-type diffusion layer

Claims (8)

Another conductivity type base region on one main surface of the one conductivity type semiconductor substrate, a source region selectively formed on a surface layer in the other conductivity type base region, the surface of the source region, and the one conductivity type semiconductor A MOS gate structure having a gate electrode mounted on the surface of the other conductivity type base region sandwiched between the substrate surface and a gate insulating film; and the one main surface surrounds the MOS gate structure And a one-conductivity-type drain region surrounding the breakdown voltage structure portion, wherein a Zener diode is electrically connected between the drain region surface and the gate electrode, and the one main surface and the other main surface In a MOS semiconductor device with a built-in overvoltage protection function having a structure in which a main current flows therebetween, the one conductivity type drain region is located before the other conductivity type base region constituting the MOS gate structure. Overvoltage protection, characterized in that the depth from the one main surface is formed as a deep region embedded MOS type semiconductor device. 2. The overvoltage protection function built-in MOS semiconductor device according to claim 1, wherein a depth of the one conductivity type drain region reaches a diffusion region formed on the other main surface. 2. The overvoltage according to claim 1, wherein the one conductivity type drain region and the diffusion region formed on the other main surface are connected by a one conductivity type low resistance layer formed along a cut surface. Protection function built-in MOS semiconductor device. 4. The method of manufacturing a MOS semiconductor device with a built-in overvoltage protection function according to claim 3, wherein the one conductivity type low resistance layer formed along the cut surface is formed by laser dicing performed in a phosphorus atmosphere. . 4. The overvoltage protection function built-in MOS semiconductor device according to claim 3, wherein the one conductivity type low resistance layer formed along the cut surface is formed by ion implantation and subsequent heat treatment after dicing. Production method. Another conductivity type base region on one main surface of the one conductivity type semiconductor substrate, a source region selectively formed on a surface layer in the other conductivity type base region, the surface of the source region, and the one conductivity type semiconductor A MOS gate structure having a gate electrode mounted on the surface of the other conductivity type base region sandwiched between the substrate surface and a gate insulating film; and the one main surface surrounds the MOS gate structure And a one-conductivity-type drain region surrounding the breakdown voltage structure portion, wherein a Zener diode is electrically connected between the drain region surface and the gate electrode, and the one main surface and the other main surface In a MOS type semiconductor device with a built-in overvoltage protection function having a structure in which a main current flows in between, formed on the inner surface of the one conductivity type drain region formed on one main surface of the one conductivity type semiconductor substrate Wrench, over-voltage protection function built-MOS type semiconductor device, characterized in that it comprises a one conductivity type diffusion layer formed on the inner surface of the trench. 7. The overvoltage protection function built-in MOS semiconductor device according to claim 1, wherein the semiconductor device is a MOSFET, or a manufacturing method thereof. 7. The overvoltage protection function built-in MOS semiconductor device according to any one of claims 1 to 6, or a method of manufacturing the same, wherein the semiconductor device is an IGBT.

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