JP2009111302A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a fixed charge in a gate insulating film in order to realize a bottom gate structure TFT using a directly grown polycrystalline silicon film as a channel layer in order to obtain a display panel having excellent display performance at a low cost, and The temperature for forming the semiconductor polycrystalline film by the direct growth method is lowered.
By using a silicon oxynitride film as a gate insulating film, the fixed charge density of the entire film is reduced and at the same time, the adsorption of source atoms during the formation of a semiconductor film is promoted. Further, gas containing germanium is mixed at the initial stage of the semiconductor film formation to promote surface adsorption and promote film formation. These lower the film formation temperature of the semiconductor polycrystalline film.
[Selection] Figure 3

Description

  The present invention relates to a thin film transistor (TFT) used in a flat panel display panel such as an organic EL (OLED) panel or a liquid crystal panel.

  The OLED display is a display with excellent features such as high contrast and high response speed, and its practical application is beginning to be centered on small and medium-sized panels. As a TFT necessary for the pixel, a top gate type TFT using a low-temperature poly-Si film by a laser annealing method in which the formation temperature of a polycrystalline Si film is about 650 ° C. at most is used. However, the low-temperature poly-Si TFT has a limited substrate size in the laser crystallization process (currently G4 size, up to 73 cm × 92 cm) and is not suitable for large OLED panel applications. Even if the size of the substrate that can be processed in the future increases, there is a problem that the manufacturing cost is higher than that of a bottom gate type amorphous Si TFT used in a large liquid crystal panel. The reason for the high manufacturing cost is that the low-temperature poly-Si TFT has a polycrystalline Si film deposition process consisting of three processes: amorphous Si film deposition, dehydrogenation annealing, and laser annealing. This is because the number of processes such as a contact processing process increases.

  Amorphous Si has low resistance to electrical stress, and the threshold value due to electrical stress during use shifts, so there is no problem in liquid crystal applications that are insensitive to on-current fluctuations, but it is not suitable for OLED panel applications that are sensitive to on-current fluctuations. . Therefore, if the TFT can be manufactured with a bottom gate type structure with fewer steps than the top gate structure if a polycrystalline Si film is formed as a semiconductor layer by a direct growth method that directly deposits a film instead of a laser annealing method, the electrical stress of the TFT Both resistance and high-efficiency manufacturing on large substrates can be achieved.

  For liquid crystal display applications, the use of a polycrystalline Si film compared to an amorphous Si film improves the on-current of the TFT, so it is hoped that higher definition and higher image display refresh rate will be achieved. Therefore, the directly grown polycrystalline Si TFT can improve the image display performance without increasing the number of processes.

  In a bottom gate type amorphous Si TFT for liquid crystal, a silicon nitride film has been mainly used as a gate insulating film. This is because the silicon nitride film has a barrier performance against alkali ions that cause a change in the threshold over time, and has an effect of preventing diffusion of alkali ions from the glass substrate. The silicon nitride film easily has a positive fixed charge, and the positive fixed charge shifts the threshold value in the minus direction. On the other hand, the amorphous Si film contains many negatively charged defect levels, and this negative charge shifts the threshold value in the plus direction. Therefore, by using both in combination, positive and negative charges apparently cancel each other, and a threshold having a low absolute value can be obtained.

When a polycrystalline Si film is used for the channel layer, the defect level in the channel layer is reduced, so that the on-current and electrical stress resistance are improved. However, the above-described charge balance is lost, and the threshold value is increased in the negative direction. Value. Therefore, when a polycrystalline Si film is used for the channel layer, it is necessary to reduce the fixed charge in the gate insulating film. For example, when the nitride film thickness is 300 nm (equivalent to a gate insulating film capacitance of 17 nF / cm ² ) and the absolute value of the threshold value is to be suppressed within 3 V, the charge density needs to be suppressed to 3 × 10 ¹¹ cm ⁻² or less.

  In the bottom gate structure, it is desirable that the formation temperature of the polycrystalline Si film is low. This is to prevent deformation of the glass substrate, as well as to prevent alteration such as hillocks of the gate electrode already formed. Since the gate electrode is altered at a peak temperature of 500 to 600 ° C., the formation temperature of the polycrystalline Si film is preferably, for example, 450 ° C. or less.

Furthermore, in order to reduce positive fixed charges in the gate insulating film, it is better to use a silicon oxide film than a silicon nitride film. In a bottom gate type TFT using polycrystalline silicon by a laser annealing method, there is an example using a gate insulating film in which an oxide film is stacked on a nitride film (Patent Document 1).
[Patent Document 1] Japanese Patent Laid-Open No. 11-17191
However, the film formation on the silicon oxide film requires a higher temperature than that on the silicon nitride film, and a polycrystalline Si film cannot be obtained at a desired low temperature. This reason can be interpreted as follows. In the covalent bond between silicon and oxygen, electrons in bond orbitals are attracted to oxygen atoms with high electronegativity. Even if the silicon atoms of the deposited material reach the surface of the silicon oxide film covered with such Si-O bonds, the binding of electrons by the oxygen atoms is strong, so the silicon atoms do not adsorb or recombine, This is because film deposition does not start.

Therefore, although it is desired to use a silicon oxide film as the gate insulating film, the temperature at which the polycrystalline Si film can be formed by the direct growth method becomes high, resulting in inconvenience.

  In view of these, it is conceivable to use a gate insulating film in which oxygen and nitrogen are further mixed. However, even with this gate insulating film, if the nitrogen concentration on the upper surface of the insulating film is too high, positive fixed charges increase, which is not preferable.

  An object of the present invention is to realize a bottom gate structure TFT using a semiconductor polycrystalline film by a direct growth method as a channel layer in order to obtain a display panel excellent in display performance at a low cost.

  In order to achieve the above object, first, the present invention uses a silicon oxynitride film containing Si, O, and N as a gate insulating film, and adsorbs raw material atoms during the formation of a semiconductor film by Si-N bonding on the surface. To lower the temperature of the semiconductor film (450 ° C or lower). At this time, the positive fixed charge of the film is suppressed by limiting the nitrogen concentration on the surface. Furthermore, since it is only the surface that affects the formation of the semiconductor film, the nitrogen concentration in the lower part of the gate insulating film is increased to suppress the diffusion of alkali ions.

A suitable nitrogen concentration related to the present invention will be described with reference to FIG. The grain size of the semiconductor polycrystalline film is preferably a fine grain size of 10 to 50 nm. This is to suppress image roughness caused by variations in TFT characteristics in image display of the OLED panel. The horizontal axis is the distance between the centers of the grains that is the starting point of crystal growth, and is approximately equal to the grain size. The line indicated by the white triangle in (1) shows the relationship between the distance between the growth start points and the growth start surface density. Semiconductor source molecules are repeatedly adsorbed and desorbed at the Si-N bond, which is the surface adsorption site, and not all of the adsorption sites become the growth starting point. The line indicated by the black triangle in (2) is the nitrogen surface density necessary to obtain the growth starting surface density in (1). Wherein the ratio of nitrogen surface density and growth starting point surface density is adsorption site is 10 ^2. The line indicated by the black circle in (3) is the nitrogen volume density obtained from the surface density in (2). From the figure, the preferable nitrogen concentration is 1 × 10 ¹⁸ cm ⁻³ to 2 × 10 ²⁰ cm ⁻³ . This concentration range is preferably in the region of at least 5 nm or more of the surface of the gate insulating film.

  Since it is only the surface that determines the formation of the semiconductor film, the above limitation is related to the surface of the gate insulating film in the gate insulating film. Therefore, diffusion of alkali ions can be suppressed by increasing the nitrogen concentration below the gate insulating film.

In order to suppress the diffusion of alkali ions from the glass substrate during the TFT manufacturing process at a temperature of 400 ° C., the nitrogen concentration is 2 × 10 ²¹ cm ⁻³ or more in a region of at least 20 nm or more from the bottom surface of the gate insulating film. It is preferable that

FIG. 2 shows the concept again. The lower limit C1 of the preferable nitrogen concentration on the surface of the gate insulating film is 1 × 10 ¹⁸ cm ⁻³ and the upper limit C2 is 2 × 10 ²⁰ cm ⁻³ . A preferable lower limit C3 of the nitrogen concentration on the lower surface of the gate insulating film is 2 × 10 ²¹ cm ⁻³ . When these preferable nitrogen concentrations are described by the concentration ratio of nitrogen to oxygen, they are 3 × 10 ⁻⁵ or more and 0.006 or less on the upper surface and 0.2 or more on the lower surface.

  Further, in the present invention, secondly, a gas containing Ge is added to the source gas at least at the initial stage of the formation of the semiconductor film, and a part of the oxygen atoms on the surface are removed to adsorb the semiconductor source gas. The film formation temperature of the semiconductor film is lowered by promoting the increase.

The activation energy required for decomposition of typical monosilane (SiH ₄ ) as a source gas for the semiconductor film and germane (GeH ₄ ), which is an example of a gas containing Ge, is shown in the following table. From this table, it can be seen that the activation energy of GeH ₄ is lower than that of SiH ₄ . Therefore, if GeH ₄ is added to the source gas for the semiconductor film, the film formation can be promoted.

In addition, when GeH ₄ gas of about 0.01 to 1 Torr is introduced into a sample whose substrate temperature is kept at 400 ° C. in a vacuum and the substrate surface is covered with a SiO _x film (x = 1 to 2), the following endothermic reaction occurs. Occurs and the oxygen component is desorbed from the surface.
GeH ₄ + SiO ₂ (surface) → H ₂ O ↑ + Si ₂ GeH ₂ (surface) (1.2 eV endotherm) (1)
When GeH ₄ gas is mixed and introduced at least at the initial stage of the semiconductor film formation, the growth starting point on the surface of the gate insulating film can be formed by the reaction (1). Therefore, if this reaction is used, the growth starting point can be efficiently formed without increasing the internal nitrogen concentration in the gate insulating film, and the semiconductor film can be formed at a lower temperature.
Therefore, in order to promote the formation of the growth starting point on the gate insulating film, it is desirable to set it to 10 atom% or more in the region of at least 5 nm or more on the gate insulating film side in the semiconductor film.

  According to the present invention, since the semiconductor film can be formed at a low temperature without increasing the fixed charge in the gate insulating film, the bottom gate structure TFT using the semiconductor polycrystalline film as the channel layer on the large substrate is highly efficient. Therefore, a display panel having excellent display performance can be obtained at a low cost.

An embodiment of the present invention will be described below with reference to FIG. First, an AlNd film having a thickness of 250 nm was formed as a gate electrode wiring 2 on the insulating substrate 1 by a sputtering method, and was processed using photolithography. A silicon oxynitride film was formed thereon as the gate insulating film 3 by a parallel plate plasma CVD method at an RF frequency of 13.56 MHz, an RF power of 500 W, a film formation temperature of 350 ° C., and a pressure of 1.0 Torr. First 25 _{seconds, SiH 4 / NH 3 / N} 2 O / N 2 = 100/1500/1000/6000 was deposited by sccm, subsequently 70 sec _{SiH 4 / NH 3 / N 2} O / N 2 = 100/100 Film formation was performed at / 7000/1400 sccm to obtain a 240 nm gate insulating film. FIG. 4 shows the SIMS analysis result of the gate insulating film. The vertical axis represents SIMS count. In the figure, the effective nitrogen concentration in the horizontal axis from 0 to 100 nm is shown next to the vertical axis. In order to convert the count number into the concentration of each element, it is necessary to consider the host effect (the ionization probability depends on the composition) and the like, so this axis is effective only in the horizontal axis from 0 to 100 nm. The nitrogen concentration on the upper surface of the gate insulating film is 4 × 10 ¹⁹ cm ⁻³ . The density on the lower surface was 6 × 10 ²¹ cm ⁻³ .

On top of that, film formation was performed for 60 minutes using thermal CVD at a film formation temperature of 450 ° C., a pressure of 0.08 Torr, and SiH ₄ = 5 sccm, to obtain a 10 nm semiconductor film 4a made of a polycrystalline Si film. Further, subsequently, film formation was performed using thermal CVD at a film formation temperature of 450 ° C., a pressure of 10 Torr, and SiH ₄ / He = 10/500 sccm for 60 minutes to obtain a 190 nm semiconductor film 4b made of a polycrystalline Si film. It was.

In this embodiment, the thermal CVD is used for forming the semiconductor film 4b. However, the film forming method is not limited to this, and for example, plasma CVD for supplying SiH ₄ as a source gas in order to improve the film forming throughput. The method may be used.

Next, an n ⁺ Si film was formed as the contact layer 5 by a plasma CVD method. Thereafter, the n ⁺ Si film / polycrystalline film was processed into an island shape using photolithography. An AlNd film was formed thereon by a sputtering method, and processed into a source electrode wiring 6 and a drain electrode wiring 7 using photolithography. Further, a silicon nitride film was formed thereon as a protective insulating film 8 by a plasma CVD method. In addition, a protective insulating film 9 was formed with an organic coating film, and a contact hole 10 was formed using photolithography. Next, an ITO film was formed as the pixel electrode 11 by a sputtering method and processed using photolithography. The absolute value of the threshold value of the obtained TFT was 2.6V.

  By the above method, a bottom gate type TFT having a polycrystalline semiconductor film as a channel layer can be manufactured with high efficiency by a direct growth method at a low temperature of 450 ° C. or less without increasing the fixed charge in the gate insulating film. did it.

A second embodiment of the present invention will be described with reference to FIG. This embodiment differs from the first embodiment in that a polycrystalline SiGe film is used as the semiconductor polycrystalline film. The gate electrode wiring 2 and the gate insulating film 3 on the insulating substrate 1 were formed using the same conditions as in the first embodiment. Next, a film is formed on the gate insulating film 3 using thermal CVD at a film forming temperature of 440 ° C., a pressure of 0.4 Torr, and SiH ₄ / GeH ₄ / He = 120/60/50 sccm for 15 minutes. A 200 nm semiconductor film 30 made of the film was obtained. In the analysis result by the RBS (Rutherford backscattering) method, the Ge concentration on the lower surface of the semiconductor layer was about 20 atom%. Although a polycrystalline SiGe film is used as the TFT semiconductor film 30, the type of film is not limited to this. For example, a polycrystalline SiGe film is formed to a thickness of 10 nm, and a polycrystalline SiGe film is formed thereon using a plasma CVD method. A film may be deposited at 190 nm.

  Thereafter, the contact layer 5, the source electrode wiring 6, the drain electrode wiring 7, the protective insulating films 8 and 9, the contact hole 10, and the pixel electrode 11 were formed in the same manner as in Example 1.

In this example, since GeH ₄ was added when forming the semiconductor polycrystalline film, the film formation time was shortened compared to Example 1, and the film formation temperature could be further reduced.

  An embodiment of the present invention will be described below with reference to FIG. An organic EL charge transport layer 12, a light emitting layer 13, and a charge transport layer 14 are formed on the TFT formed by the same method as in Example 2 by vapor deposition, and a transparent conductive film is deposited and sputtered as the upper electrode 15. Then, a silicon nitride film was formed as the sealing layer 16 by catalytic CVD to produce an OLED panel. The manufactured OLED panel exhibited a long life because of high contrast, high response speed, and good TFT stability.

  In the present embodiment, the TFT of the second embodiment is used as the TFT, but the TFT of the first embodiment is also applicable. The same applies to the fourth embodiment.

  Hereinafter, an embodiment of the present invention will be described with reference to FIG. In the same manner as in Example 1, a gate electrode wiring 2, a gate insulating film 3, a polycrystalline SiGe film 30, a contact layer 5, a source electrode wiring 6, a drain electrode wiring 7, a protective insulating film 8, 9 was formed. Next, an ITO film was formed as the pixel electrode 17 by a sputtering method and processed using photolithography.

  An alignment film 18 was formed thereon, the counter substrate 20 was bonded through a spacer 19, and a liquid crystal 29 was sealed to produce a liquid crystal panel. The counter substrate 20 includes a color filter 23, a transparent electrode 24, an alignment film 25, and the like. The manufactured liquid crystal panel was rewritable at high speed and showed a high-definition image.

The figure which showed the suitable nitrogen concentration of this invention. The figure which showed the suitable nitrogen concentration of this invention by the concentration ratio of nitrogen with respect to oxygen. 1 is a schematic cross-sectional view showing a first embodiment of a thin film transistor of the present invention. The SIMS analysis result of the oxynitride film | membrane used for the gate insulating film in the Example of this invention. The cross-sectional schematic diagram which shows 2nd Embodiment of the thin-film transistor of this invention. The cross-sectional schematic diagram of the OLED display apparatus using this invention. The cross-sectional schematic diagram of the liquid crystal display device using this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 2 ... Gate electrode wiring, 3 ... Gate insulating film, 4a ... Polycrystalline Si film, 4b ... Polycrystalline Si film, 5 ... Contact layer, 6 ... Source electrode wiring, 7 ... Drain electrode wiring, 8 ... Protective insulating film, 9 ... Protective insulating film, 10 ... Contact hole, 11 ... Pixel electrode, 12 ... Charge transport layer, 13 ... Light emitting layer, 14 ... Charge transport layer, 15 ... Upper electrode, 16 ... Sealing layer, DESCRIPTION OF SYMBOLS 17 ... Pixel electrode, 18 ... Orientation film, 19 ... Spacer, 20 ... Opposite substrate, 23 ... Color filter, 24 ... Transparent electrode, 25 ... Orientation film, 29 ... Liquid crystal, 30 ... Polycrystal SiGe film | membrane

Claims (9)

In a bottom gate thin film transistor including a gate electrode film, a gate insulating film, a semiconductor film, a source electrode film, and a drain electrode film on an insulating substrate,
The gate insulating film is made of a film containing Si, O, N, and the N concentration in the gate insulating film is lower on the semiconductor film side than on the gate electrode film side,
A semiconductor device, wherein the semiconductor film is a polycrystalline film containing Si. In claim 1,
The semiconductor device according to claim 1, wherein an N concentration in the gate insulating film is 1 × 10 ¹⁸ cm ⁻³ or more and 2 × 10 ²⁰ cm ⁻³ or less in a region of at least 5 nm or more on the semiconductor film side. In claim 2,
The semiconductor device according to claim 1, wherein the N concentration in the gate insulating film is 2 × 10 ²¹ cm ⁻³ or more in a region of at least 20 nm or more on the gate electrode film side.   A bottom comprising a step of forming a gate electrode film on an insulating substrate, a step of forming a gate insulating film, a step of forming a semiconductor film, a step of forming a source electrode film, and a step of forming a drain electrode film In the method for manufacturing a gate thin film transistor, in the step of forming the gate insulating film, a film containing Si, O, and N and having a N concentration lower on the semiconductor film side than the gate electrode film side is formed. A method for manufacturing a semiconductor device, comprising forming a polycrystalline film containing Si in the step of forming a semiconductor film. In a bottom gate thin film transistor including a gate electrode film, a gate insulating film, a semiconductor film, a source electrode film, and a drain electrode film on an insulating substrate,
The gate insulating film is made of a film containing Si, O, N, and the N concentration in the gate insulating film is lower on the semiconductor film side than on the gate electrode film side,
A semiconductor device, wherein the semiconductor film is made of a polycrystalline film containing Ge in addition to Si. In claim 5,
The semiconductor device according to claim 1, wherein an N concentration in the gate insulating film is 1 × 10 ¹⁸ cm ⁻³ or more and 2 × 10 ²⁰ cm ⁻³ or less in a region of at least 5 nm or more on the semiconductor film side. In claim 6,
A semiconductor device characterized in that a Ge concentration in a semiconductor film made of a polycrystalline film containing Si and Ge is 10 atom% or more in a region of at least 5 nm or more on the gate insulating film side. In claim 6,
The semiconductor device according to claim 1, wherein the N concentration in the gate insulating film is 2 × 10 ²¹ cm ⁻³ or more in a region of at least 20 nm or more on the gate electrode film side.   A bottom comprising a step of forming a gate electrode film on an insulating substrate, a step of forming a gate insulating film, a step of forming a semiconductor film, a step of forming a source electrode film, and a step of forming a drain electrode film In the method for manufacturing a gate thin film transistor, in the step of forming the gate insulating film, a film containing Si, O, and N and having a N concentration lower on the semiconductor film side than the gate electrode film side is formed. A method for manufacturing a semiconductor device, comprising forming a polycrystalline film containing Si and Ge in the step of forming a semiconductor film.

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