JP2009188234A - Semiconductor stacking method and semiconductor package using semiconductor stacked by the method - Google Patents

Abstract

An object of the present invention is to eliminate the labor and time required to connect each external connection terminal one by one with a conventional wire, and to greatly improve work efficiency.
First, a semiconductor wafer 3 is diced, and semiconductors 2, 2, 2,. Next, the insulating layer 6 is formed on the entire upper surface of the semiconductor wafer 3 by printing. Next, the part of the external connection terminal 2A of the semiconductor 2 of the insulating layer 6 is opened. Next, conductive lines 8 made of a conductive paste are formed by printing so as to straddle between the external connection terminals 2A and 2A of the adjacent semiconductors 2 and 2. Next, the semiconductor wafer 3 is diced again at the center of the dicing line with a blade thinner than the blade used in the dicing, and each of the semiconductors 2, 2, 2,. Peel off. Next, a plurality of semiconductors 2, 2, 2 are stacked and bonded together, and a conductive paste is printed by printing so as to straddle the cut surface of the conductive wire 8 exposed on the side surfaces of each semiconductor 2, 2, 2. The wiring 9 is formed.
[Selection] Figure 14

Description

  The present invention relates to a semiconductor stacking method and a semiconductor package using a semiconductor stacked by the method.

  With the development of semiconductor technology, higher integration and higher performance of semiconductor elements are progressing, and there is a method of stacking a plurality of semiconductors as one means for increasing the capacity of semiconductor elements (see, for example, Patent Document 1).

JP 2001-189415 A

  FIG. 18 shows one example of a conventional example in which a plurality of semiconductors are stacked and mounted on an interposer to form a semiconductor package, and external connection terminals of a plurality of semiconductors 100, 101, and 102 positioned above and below, respectively. 100A, 101A, 102A are wire-bonded with wires 103, 103, 103... And then the upper and lower semiconductors 100, 101, 102 are connected and integrated with an adhesive, and then bonded onto the interposer 104. The external connection terminal 102A of the semiconductor 102 is wire bonded to the electrode pad of the interposer 104 with the wire 103. In the figure, subsequent resin sealing is omitted.

  As described above, the conventional semiconductor stacking method and the semiconductor package using the semiconductors stacked by the method are arranged such that the terminals 100A, 101A, 102A of the plurality of semiconductors 100, 101, 102 positioned above and below are connected to the wires 103, 103, Although wire bonding is performed with 103..., The work and time required for this wire bonding work has been a cause of a decrease in work efficiency.

  The present invention has been made in view of the above points, and is intended to achieve electrical continuity between external connection terminals of a plurality of semiconductors positioned above and below with a wiring made of a conductive paste formed by printing means, Accordingly, it is an object of the present invention to provide a semiconductor stacking method and a semiconductor package using the semiconductor stacked by the method, which can improve the working efficiency far more than the work by the conventional wire bonding.

Thus, the gist of the present invention resides in a semiconductor stacking method comprising the following steps.
a. In a dicing line, a semiconductor wafer formed by aligning a large number of semiconductors formed by forming a large number of external connection terminals aligned on the upper surface of the outer edge on the wafer is attached to an adhesive film having a reinforcing plate attached to the back surface. Dicing is performed to divide each semiconductor into chips.
b. An insulating layer such as polyimide is formed on the entire top surface of the semiconductor wafer by printing.
c. The portion of the semiconductor external connection terminal of the insulating layer is opened by photolithography.
d. Conductive lines are formed by printing or plating so as to straddle between the external connection terminals of adjacent semiconductors.
e. The semiconductor wafer is diced again at the center of the dicing line with a blade thinner than the blade used in the dicing.
f. Each semiconductor is peeled from the adhesive film.
g. A plurality of semiconductors are stacked and bonded vertically, and a wiring made of a conductive paste is formed by printing so as to straddle the cut surface of the conductive wire connected to the external connection terminal exposed on the side surface of each semiconductor.

  In addition, the present invention provides a required number of semicircular cutouts on the left and right side walls of a silicon interposer formed with a memory controller IC in the center of the back surface, and rewiring both sides of the silicon interposer. A circuit is formed, and a rewiring circuit on both the front and back sides of the silicon interposer is electrically connected by a conductor applied by plating or the like in the notch, and the memory controller IC is formed on the back surface of the silicon interposer. On the surface of the interposer, a semiconductor to be a memory IC stacked by the method according to claim 1 is placed on the surface of the interposer so that the external connection terminal is on the lower side. A semiconductor formed by connecting a conductive line connected to an external connection terminal to a rewiring circuit formed on the surface of the silicon interposer. Also Kkeji is for its gist.

  The present invention is designed to achieve electrical continuity between the external connection terminals of a plurality of semiconductors positioned above and below by wiring with a conductive paste formed by printing means. The labor and time for connecting the connection terminals one by one are not required, and the work efficiency can be greatly improved. Further, by using a semiconductor stacked by such a stacking method and placing it on the surface of the silicon interposer, the working efficiency can be greatly improved and the size can be reduced as compared with the case of wire bonding. A semiconductor package can be obtained.

  The best mode for carrying out a semiconductor stacking method according to the present invention will be described below with reference to the drawings.

  FIG. 1 to FIG. 15 are process explanatory views of a semiconductor stacking method according to the present invention.

A semiconductor stacking method according to the present invention includes the following a. ~ G. It consists of these processes.
a. A semiconductor wafer 3 formed by aligning a large number of semiconductors 2, 2, 2,... Formed by forming a large number of external connection terminals 2A, 2A, 2A. Dicing is performed in the dicing line 5 in a state of being attached to the adhesive film 4 to which the reinforcing plate 4A is attached, and each of the semiconductors 2, 2, 2,. The blade (not shown) used in this dicing has a thickness of 70 to 100 μm, and W1 is the width of the gap formed by dicing. The thickness of the semiconductor 2 is about 25 μm.

  1 to 3 show such a process. In these drawings, the rewiring circuit and the like in each of the semiconductors 2, 2, 2,... Are omitted, and only the external connection terminal is denoted by reference numeral 2A. ing. 1 is a plan view of the semiconductor wafer 3 before dicing, FIG. 2 is a partial enlarged sectional view of the semiconductor wafer 3 after dicing, and FIG. 3 is an enlarged view of a portion A in FIG.

  b. An insulating layer 6 such as polyimide is formed on the entire upper surface of the semiconductor wafer 3 by printing. 4 and 5 show such a process, and polyimide or the like is filled in a gap formed by dicing. The polyimide is a photosensitive polyimide.

  c. Open portions 7 of the external connection terminals 2A of the semiconductors 2, 2, 2,... Of the insulating layer 6 are formed by photolithography. 6 and 7 show such a process.

  d. Conductive lines 8 made of conductive paste are formed by printing so as to straddle between the external connection terminals 2A and 2A of adjacent semiconductors 2 and 2. 8 to 10 show such a process, and FIG. 10 is a plan view of the wafer 3. Although not shown, the conductive wire 8 may be formed by plating.

  e. The semiconductor wafer 3 is diced again at the center of the dicing line 5. 11 and 12 show such a process. The dicing is performed using a blade (not shown) thinner than the blade used for dicing in the step a, and the thickness of the blade is 30 to 40 μm. W2 is a gap formed by dicing. As a result, the coating of the insulating layer 6 such as polyimide remains on the side surfaces of the semiconductors 2, 2, 2,.

  f. Each semiconductor 2, 2, 2 ... is peeled from the adhesive film 4. FIG. 13 is a perspective view of the semiconductor 2 peeled from the adhesive film 4.

  g. A plurality of semiconductors 2, 2, 2... Are stacked and bonded vertically, and are exposed on the side surfaces of the respective semiconductors 2, 2, 2... Across the cut surface of the conductive wire 8 connected to the external connection terminal 2 A. As shown, the wiring 9 made of conductive paste is formed by printing. FIG. 14 and FIG. 15 show such a process, FIG. 14 is a perspective view of the completed state, and FIG. 15 is an enlarged sectional view taken along the line II in FIG. Reference numeral 10 denotes an adhesive.

  In the present invention, as described above, the electrical connection between the external connection terminals 2A, 2A and 2A of the plurality of semiconductors 2, 2 and 2 positioned above and below is performed by the wiring 9 made of conductive paste formed by printing. Therefore, the labor and time for connecting each external connection terminal one by one with a conventional wire are not required, and the work efficiency can be greatly improved.

  16 and 17 show a semiconductor package using semiconductors stacked by the above method. In addition, the semiconductor package integrates a memory IC and a memory controller IC that controls the memory IC, and is externally referred to as a silicon disk or a memory card that is detachably mounted on a personal computer or a digital still camera. A semiconductor package used as a component of a storage device.

  Thus, the semiconductor package 11 has the required number of semicircular cutouts 14, 14, 14... On the left and right side walls of the silicon interposer 13 formed with the memory controller IC 12 at the center of the back surface. And rewiring circuits 15 and 16 are formed on both front and back surfaces of the silicon interposer 13, and the rewiring circuits 15 and 16 on both front and back surfaces of the silicon interposer 13 are placed in the notches 14, 14, 14. In this embodiment, the conductors are electrically connected by copper platings 17 and 17, and the memory controller IC 12 is connected to the rewiring circuit 16 formed on the back surface of the silicon interposer 13. The semiconductors 2, 2, 2,... To be memory ICs stacked on the surface by the method described above are connected to the external connection terminals 2 The conductive wire 8 connected to the external connection terminal 2A of the lowermost semiconductor 2 is connected to the rewiring circuit 15 formed on the surface of the silicon interposer 13. .

  The semiconductor package 11 according to the present embodiment uses the semiconductors 2, 2, 2,... Stacked by the stacking method described above and is mounted on the surface of the silicon interposer 13, so that wire bonding is performed. Compared with this, the working efficiency can be greatly improved and the size can be reduced.

It is process explanatory drawing of the semiconductor stacking method which concerns on this invention, and is a top view of a semiconductor wafer. It is a partial expanded sectional view of the state which diced the semiconductor wafer. It is an enlarged view of A part in FIG. It is the elements on larger scale of the state where the insulating layer was formed in the whole upper surface of a semiconductor wafer. FIG. 4 is an enlarged view of a portion B in FIG. 3. It is a partial expanded sectional view of the state opened to the insulating layer. FIG. 7 is an enlarged view of a portion C in FIG. 6. It is a partial expanded sectional view of the state in which the conductive wire by the conductive paste was formed. It is an enlarged view of D part in FIG. It is a partial expanded sectional view of the state in which the conductive wire by the conductive paste was formed. It is a partial expanded sectional view of the state where the semiconductor wafer was diced again. It is an enlarged view of E part in FIG. It is a perspective view of the semiconductor peeled from the adhesive film. It is a perspective view of the state where a plurality of semiconductors were stacked and wiring with conductive paste was formed on the side surface. It is the II sectional view taken on the line in FIG. FIG. 16 is a plan view of a semiconductor package using semiconductors stacked in the steps of FIGS. It is the II-II sectional view taken on the line in FIG. It is explanatory drawing of the conventional semiconductor stacking method and a semiconductor package.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wafer 2, 2, 2 ... Semiconductor 2A, 2A, 2A External connection terminal 3 Semiconductor wafer 4 Adhesive film 4A Reinforcement board 5 Dicing line 6 Insulating layer 7 Opening of insulating layer 8 Conductive wire 9 Wiring with conductive paste 10 Adhesion Agent 11 Semiconductor package 12 Memory controller IC
13 Silicon interposer 14, 14 Semicircular cutout 15, 16 Rewiring circuit 17, 17 Copper plating

Claims (2)

A semiconductor stacking method comprising the following steps.
a. In a dicing line, a semiconductor wafer formed by aligning a large number of semiconductors formed by forming a large number of external connection terminals aligned on the upper surface of the outer edge on the wafer is attached to an adhesive film having a reinforcing plate attached to the back surface. Dicing is performed to divide each semiconductor into chips.
b. An insulating layer such as polyimide is formed on the entire top surface of the semiconductor wafer by printing.
c. The portion of the semiconductor external connection terminal of the insulating layer is opened by photolithography.
d. Conductive lines are formed by printing or plating so as to straddle between the external connection terminals of adjacent semiconductors.
e. The semiconductor wafer is diced again at the center of the dicing line with a blade thinner than the blade used in the dicing.
f. Each semiconductor is peeled from the adhesive film.
g. A plurality of semiconductors are stacked and bonded vertically, and a wiring made of a conductive paste is formed by printing so as to straddle the cut surface of the conductive wire connected to the external connection terminal exposed on the side surface of each semiconductor. A predetermined number of semicircular cutouts are provided on the left and right side walls of the silicon interposer formed with the memory controller IC in the center of the back surface, and a rewiring circuit is formed on both the front and back surfaces of the silicon interposer. While electrically connecting the rewiring circuits on both the front and back sides of the silicon interposer by a conductor applied by plating or the like in the notch, and connecting the memory controller IC to the rewiring circuit formed on the back surface of the silicon interposer, A semiconductor to be a memory IC stacked by the method according to claim 1 is placed on the surface of the interposer so that its external connection terminal is on the lower side, and is connected to the external connection terminal of the lowermost semiconductor. A semiconductor package in which wires are connected to a rewiring circuit formed on the surface of the silicon interposer.

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