JP2009188231A - Solid-state imaging device and manufacturing method thereof - Google Patents

Abstract

The resistance of a gate electrode is reduced when silicide is not formed in a transistor region of a pixel array portion.
A silicide layer is formed in a region of a transistor constituting a peripheral circuit portion. Although the silicide layer 140 is not formed in the photodiode and transistor regions of the pixel array portion 10, the gate electrode 122_10 of the transistor is formed of a metal material. As a manufacturing method thereof, photodiodes and transistors are formed in the pixel array unit 10 and the peripheral circuit unit 11, and then covered with silicon nitride or the like so that silicide is not formed in the transistor region of the pixel array unit. A silicide layer 140 is formed in the region of the transistor constituting the. Thereafter, the electrode material existing in the gate electrode 122_10 portion of the transistor of the pixel array section 10 is replaced with a metal material.
[Selection] Figure 6

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof. In particular, the present invention relates to a transistor in which silicide is formed in a transistor region.

  Along with higher integration of semiconductor integrated circuit devices, miniaturization of transistors that are constituent elements of the device progresses, gate lengths become shorter, and source / drain regions become shallower. In order to reduce the resistance of the source / drain region, it is known to perform self-aligned silicidation (salicide process). It is also known that the gate electrode is silicided in order to reduce the gate resistance.

  In order to further reduce the resistance of the gate electrode, a mechanism has been proposed in which a gate is made of a metal having a resistance lower than that of silicide (see, for example, Patent Document 1). In this mechanism, a disposable gate is first formed of a silicon layer, and then a replacement metal gate electrode is formed by replacing silicon with a metal such as aluminum.

JP 2007-53394 A

  On the other hand, for example, in the field of video equipment, solid-state imaging of a CCD (Charge Coupled Device) type, a MOS (Metal Oxide Semiconductor) type, or a CMOS (Complementary Metal-oxide Semiconductor) type that detects light (an example of an electromagnetic wave) in a physical quantity. The device is in use. These read out, as an electrical signal, a physical quantity distribution converted into an electrical signal by a unit component (a pixel in a solid-state imaging device). Here, “solid” means made of semiconductor.

  In addition, among solid-state imaging devices, an amplifying solid-state imaging device (APS; Active Pixel Sensor) that has a driving transistor for amplification in a pixel signal generation unit that generates a pixel signal corresponding to the signal charge generated in the charge generation unit There is an amplification type solid-state imaging device including a pixel having a configuration (also called a gain cell). For example, many MOS and CMOS solid-state imaging devices have such a configuration.

  A CCD type solid-state image pickup device (hereinafter referred to as a CCD solid-state image pickup device or a CCDS image sensor) requires a dedicated process for its manufacture, and requires a plurality of power supply voltages for its operation, and a plurality of peripheral ICs. There is a problem that the system becomes very complicated because it is necessary to operate in combination with (Integrated Circuit).

  On the other hand, a CMOS type solid-state imaging device (hereinafter referred to as a CMOS solid-state imaging device or a CMOS image sensor) has a manufacturing process similar to that of a general CMOS type integrated circuit produced all over the world. It can be used, can be driven by a single power supply, and can easily mix analog circuits and logic circuits using a CMOS process in the same chip, so the number of peripheral ICs can be reduced. It has a number of very significant merits. For this reason, in recent years, CMOS image sensors that can overcome the above-mentioned various problems of CCD image sensors have attracted attention as image sensors that can replace CCDs.

  By the way, in the solid-state imaging device, with the high integration, a charge generation unit such as a photodiode constituting the pixel unit, a transistor configuring a circuit (referred to as a peripheral circuit unit) arranged around the pixel unit, and the like There is a tendency to further reduce the size of the semiconductor element to further increase the mounting density. For this reason, various microfabrication techniques have been researched and developed. For example, in a CMOS image sensor, the design rule is already in the submicron order.

  Incidentally, in the case of a typical CMOS image sensor, a pixel signal detection circuit (also referred to as a lead-out circuit or the like) for sending a pixel signal to a peripheral circuit unit based on a signal charge detected by a charge generation unit such as a photodiode. Is also provided in the pixel portion. As this pixel signal detection circuit, for example, a transfer transistor, a reset transistor, and an amplifying transistor are constituted by three transistors, a transfer transistor, a reset transistor, an amplifying transistor, and a vertical selection transistor 4 for selecting a vertical address. Those composed of two transistors are well known.

  Here, in a CMOS logic such as a general semiconductor integrated circuit (for example, LSI), as described above, a silicide layer is formed in the gate electrode and the source / drain region in order to reduce the contact resistance as the integration becomes higher. Yes. On the other hand, in a CMOS image sensor, when a silicide layer is formed in the charge generation portion, sensitivity due to a decrease in light transmittance deteriorates, and noise such as white spots increases due to metal contamination. Therefore, a silicide layer is formed only on the gate electrode and source / drain region of the peripheral circuit portion, and the silicide layer is formed on the gate electrode and source / drain region of the transistor constituting the charge generation portion of the pixel portion and the pixel signal detection circuit. It can be considered not to form.

  Basically, a silicide layer is not formed in the charge generation portion of the pixel portion, but the pixel signal detection circuit other than the charge generation portion and the gate electrode and the source / drain region of the transistors constituting the peripheral circuit portion are formed. Although it is conceivable to form silicide, the gate electrode and the source / drain region of the transistor constituting the pixel signal detection circuit other than the charge generation unit without forming the silicide layer in the charge generation unit in the pixel unit. In the background, the formation of silicide is accompanied by manufacturing difficulties due to the dimensional accuracy of the mask itself and the alignment accuracy of the mask.

  However, if a silicide layer is not formed in the gate electrode or source / drain region of the pixel portion, a problem of increasing the resistance value of the gate electrode or source / drain region due to the progress of miniaturization will arise. When the resistance value increases, the charge of the pixel cannot be read out at a high speed due to signal delay.

  In addition, when a silicide prevention film (for example, a SiN film) for preventing silicide is left only in the charge generation portion, it is necessary to consider misalignment along with processing variations, and accordingly, the area of the charge generation portion is reduced and sensitivity is lowered.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a mechanism capable of reducing the resistance of the gate electrode when silicide is not formed in the transistor region of the pixel array portion.

  Preferably, as described above, it is an object to provide a mechanism that can avoid the difficulty of manufacturing when a mechanism that can reduce the resistance of the gate electrode of the transistor in the pixel array portion is employed.

  In one embodiment of the solid-state imaging device according to the present invention, first, similarly to a general solid-state imaging device, a charge generation unit that generates a signal charge and a pixel that includes a transistor and is based on the signal charge generated by the charge generation unit. A pixel array unit having a pixel signal generation unit that generates a signal and a pixel array unit disposed in the periphery of the pixel array unit, a transistor, and a pixel signal output from the unit pixel of the pixel array unit A drive control unit having a control circuit function for reading out the array unit and the outside of the apparatus, or a peripheral circuit unit provided with a signal processing unit for processing a pixel signal read out from the pixel signal generation unit.

  As a characteristic matter of the solid-state imaging device according to the present invention, silicide is formed in the region of the transistor constituting the peripheral circuit unit, but the entire pixel array unit, that is, the charge generation unit and the pixel signal generation unit Silicide is not formed in the region of the transistor that constitutes the transistor, and the gate electrode of the transistor that constitutes the pixel signal generation unit is formed of a metal material.

  A method for manufacturing a solid-state imaging device according to the present invention is a method for manufacturing the solid-state imaging device according to the present invention. First, as in a normal manufacturing method, the transistors constituting the charge generation unit and the pixel signal generation unit At the same time as forming the region, a region of a transistor constituting the peripheral circuit portion is formed. Thereafter, silicide is not formed in the regions of the transistors constituting the charge generation unit and the pixel signal generation unit of the pixel array unit (for example, the entire pixel array unit is covered with silicon nitride), and the peripheral circuit unit is Silicide is formed in the region of the transistor to be formed. In this way, silicide is formed in the transistor region constituting the peripheral circuit portion, but silicide is formed in the entire pixel array portion, that is, the transistor region constituting the charge generation portion and the pixel signal generation portion. It is in a state that has not been done.

  Then, after the step of forming the silicide, the electrode material existing in the gate electrode portion of the transistor constituting the pixel signal generation portion of the pixel array portion is replaced with a metal material. By doing so, the gate electrode of the transistor forming the pixel signal generation unit is formed of a metal material.

  Here, preferably, in the step of forming the transistor, a sidewall is formed on the side surface of the gate electrode, and source / drain regions that configure the transistor are formed on both sides of the gate electrode so as to be in contact with the side surface of the sidewall. By doing so, the source / drain regions can be formed in a self-aligning manner using the sidewalls.

  In addition, even when the electrode material existing in the gate electrode portion is replaced with a metal material, the resistance of the electrode material existing in the gate electrode portion is lower than that of silicide in a self-aligning manner using the sidewall. Can be replaced with metal material.

  According to one embodiment of the present invention, when the silicide is not formed in the transistor region of the pixel array portion, the gate electrode of the transistor in the pixel array portion is replaced with the metal material, so that the resistance of the gate electrode is reduced. The

  Silicide is formed in the peripheral circuit portion, but the entire pixel array portion does not form silicide. Therefore, it is only necessary to separate the peripheral circuit portion from the pixel array portion, and use a mask with rough dimensional accuracy and alignment accuracy. Since it can be manufactured, the manufacturing difficulty can be avoided. Further, if the source / drain regions and the gate replacement electrode are formed in a self-aligning manner using the sidewall, the gate electrode width can be limited more narrowly, and the gate electrode width of the pixel array portion can be limited while the metal is limited. It becomes easy to replace it with a material.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, a case where a CMOS solid-state imaging device, which is an example of an XY address type solid-state imaging device, is used as a device will be described as an example. The CMOS solid-state imaging device will be described on the assumption that all pixels are made of NMOS.

  However, this is an example, and the target device is not limited to the MOS type solid-state imaging device. All of the solid-state imaging devices for physical quantity distribution detection, in which a plurality of unit components that are sensitive to electromagnetic waves input from the outside, such as light and radiation, are arranged in a line or matrix, are described below. Embodiments are applicable as well.

<Outline of solid-state imaging device>
FIG. 1 is a schematic configuration diagram (planar chip image) of a CMOS solid-state imaging device (CMOS image sensor) which is an embodiment of the solid-state imaging device. As illustrated, the image forming apparatus 1 includes a pixel array unit 10 (pixel unit) and a peripheral circuit unit 11.

  Although not shown in detail, the pixel array unit 10 is provided with a light receiving element (an example of a charge generation unit) that outputs a signal corresponding to the amount of incident light and a pixel signal generation unit (see FIG. 2 described later). The peripheral circuit unit 11 processes a pixel signal So read from the drive control unit or the pixel array unit 10 having a control circuit function for sequentially reading out the signals of the pixel array unit 10 out of the pixel array unit 10 and further out of the chip. A signal processing unit is provided for which a transistor is used.

  As the drive control unit, for example, a horizontal scanning unit (column scanning circuit) having a function of a reading scanning unit that sequentially selects column addresses in synchronization with a clock and reads data obtained by digitally converting pixel signals, and a pixel array unit A vertical scanning unit (row scanning circuit) for selecting a row address and supplying a necessary pulse to the row, a communication / timing control unit having a function of generating an internal clock, and the like are provided.

  Examples of the signal processing unit include a differential processing unit that performs CDS (Correlated Double Sampling) processing on the signal output from each pixel, and a digital conversion unit (ADC; Analog Digital Converter) that converts an analog signal into a digital signal. In addition, a digital arithmetic unit that performs digital signal processing, an output circuit (S / A: sense amplifier) for reading out signals from the chip, and the like are provided.

  Each element of the drive control unit such as the horizontal scanning unit and the vertical scanning unit and each element of the signal processing unit such as the difference processing unit and the digital conversion unit use the same technology as the semiconductor integrated circuit manufacturing technology together with the pixel array unit 10. As a so-called one-chip device (provided on the same semiconductor substrate) integrally formed in a semiconductor region such as single-crystal silicon, a CMOS image sensor which is an example of a semiconductor system is used as the solid state of the present embodiment. It is configured to form part of the imaging device 1.

<Circuit configuration example of unit pixel>
FIG. 2 is a diagram illustrating a typical circuit configuration example (4TR configuration) of a unit pixel used in the solid-state imaging device 1 illustrated in FIG. 1.

  The configuration of the unit pixel 3 is the same as that of a normal CMOS image sensor. As the intra-pixel amplifier, for example, a floating diffusion amplifier configuration is used. As an example, with respect to the charge generation unit, a read selection transistor that is an example of a charge readout unit (transfer gate unit / read gate unit), a reset transistor that is an example of a reset gate unit, a vertical selection transistor, and a floating diffusion A CMOS sensor with a 4TR configuration consisting of four general-purpose transistors or a 3TR configuration consisting of three transistors is used, which has an amplification transistor with a source follower configuration, which is an example of a detection element that detects a potential change of can do. In the figure, a 4TR configuration is shown.

  A unit pixel 3 having a 4TR configuration includes a charge generation unit 32 mainly including a photodiode, a read selection transistor 34 (transfer transistor) to which a transfer pulse TRG is supplied, a reset transistor 36 to which a reset pulse RST is supplied, a floating transistor It has a diffusion 38, a vertical selection transistor 40 to which a vertical selection pulse VSEL is supplied, and an amplification transistor 42. The reset transistor 36, the floating diffusion 38, the vertical selection transistor 40, and the amplification transistor 42 constitute the pixel signal generation unit 5.

  In the charge generation unit 32, one end (anode side) of the light receiving element DET is connected to the reference potential Vss (negative potential) on the low potential side, and the other end (cathode side) is input to the read selection transistor 34 (typically). Is connected to the source). The read selection transistor 34 has an output terminal (typically a drain) connected to a connection node to which the reset transistor 36, the floating diffusion 38 and the amplification transistor 42 are connected, and a control input terminal (gate) having a transfer pulse. TRG is supplied.

  The reset transistor 36 has a source connected to the floating diffusion 38, a drain connected to a reset power supply Vrd (usually shared with the power supply Vdd), and a pixel reset pulse RST input to the gate (reset gate RG). For example, in the vertical selection transistor 40, the drain is connected to the source of the amplification transistor 42, the source is connected to the pixel line 51, and the gate (in particular, the vertical selection gate SELV) is connected to the vertical selection line 52. A vertical selection signal SEL is applied to the vertical selection line 52.

  The amplifying transistor 42 has a gate connected to the floating diffusion 38, a drain connected to the power supply Vdd, a source connected to the pixel line 51 via the vertical selection transistor 40, and further connected to the vertical signal line 19. ing. Further, one end of the vertical signal line 19 extends to the column processing unit 26 side, and a constant current source I is connected to the vertical signal line 19 in the path, and is substantially constant between the amplifying transistor 42 and the vertical signal line 19. A source follower configuration in which the operating current (readout current) is supplied is adopted.

<Cross-section structure>
FIG. 3 is a diagram showing an outline of a cross-sectional structure focusing on the boundary between the pixel array unit 10 and the peripheral circuit unit 11. Here, FIG. 3A shows the configuration of this embodiment, and FIG. 3B shows the configuration of the comparative example.

  As shown in FIGS. 3A and 3B, both the configuration of the present embodiment and the configuration of the comparative example generate charge in the pixel array unit 10 on the semiconductor substrate 100 (Si substrate in the drawing). Transistors forming the part 32 (indicated by photodiodes in the figure) and the pixel signal generating part 5 are formed, and transistors are formed in the peripheral circuit part 11. The semiconductor substrate 100 is provided with STI 110 (Shallow Trench Isolation) filled with an insulator for element isolation, and the STI 110 divides the charge generation unit 32 and the transistor region. In both the pixel array unit 10 and the peripheral circuit unit 11, an extension diffusion region 120 and a gate region serving as source / drain regions are provided in the transistor region. An insulating protective film 130 such as silicon nitride SiN is formed on the charge generator 32 and the upper layer side of the transistor, and an interlayer insulating film 132 of silicon oxide SiO 2 that functions as a planarizing film is formed on the upper layer. . The gate region has a structure in which sidewalls 124 (insulating film spacers) are formed on both sides of the gate electrode 122.

  Here, a silicide layer 140 formed by reacting a silicon layer and a metal film (for example, a film of Co, Ni, W, etc.) is formed in the gate electrode 122_11 and the extension diffusion region 120_11 of the transistor of the peripheral circuit section 11. However, a silicide layer is formed on the gate electrode 122_10 and the extension diffusion region 120_10 of the transistor of the charge generation unit 32 and the pixel signal generation unit 5 to prevent noise such as white spots due to a decrease in light transmittance and metal contamination. Not done.

  As shown in FIG. 3 (2), in the configuration of the comparative example, the gate electrode 122_10 of the transistor of the pixel signal generation unit 5 remains only polysilicon not forming a silicide layer, whereas FIG. As shown in (1), in the configuration of this embodiment, the gate electrode 122_10 of the transistor of the pixel signal generation unit 5 is formed of a replacement metal obtained by replacing polysilicon with a metal material (for example, tungsten W or aluminum Al). It has a feature in that. That is, the gate electrode 120_11 and the source / drain region (extension diffusion region 120_11) of the transistor in the peripheral circuit portion 11 are formed by silicidation reaction, and then the gate electrode 122_10 of the transistor in the pixel array portion 10 is replaced with a metal material. Thus, the gate electrode 122_10 made of a metal material is formed.

  As a concept, not only the gate electrode 122_10 of the transistor of the pixel signal generation unit 5 but also the gate electrode 122_11 of the transistor of the peripheral circuit unit 11 can be formed of a replacement metal. In this embodiment, such a structure is adopted. Is not adopted. This point will be described in relation to a manufacturing method described later.

  When the structure of the present embodiment as shown in FIG. 3A is adopted, the gate electrode 122_10 of the pixel array section 10 is replaced with a metal film (for example, tungsten W) by self-alignment (in a self-alignment manner). Since the contact resistance of the electrode 122_10 can be lowered and it is not necessary to reduce the area of the charge generation section 32 such as a photodiode, the pixel charge readout can be speeded up without lowering the sensitivity. The width of the gate electrode of the pixel array unit 10 can be limited to facilitate replacement of the metal film.

<Manufacturing method>
4 to 6 are views (sectional views) for explaining a procedure (manufacturing process) for manufacturing the solid-state imaging device 1 of the present embodiment. Here, FIG. 4 shows a procedure up to silicide formation that can be similarly applied to the manufacture of the structure of the comparative example, and FIGS. 5 and 6 are procedures unique to this embodiment performed after the silicide formation. (The whole is referred to as a gate electrode metal replacement step).

  First, as shown in FIG. 4A, an STI 110 for element isolation is formed on the surface of a semiconductor substrate 100 (Si substrate). For example, an active region and a field region are defined in the semiconductor substrate 100 of the pixel array unit 10 and the peripheral circuit unit 11, a trench is formed in the semiconductor substrate 100 in the field region, an insulating film is filled in the trench, and an STI structure field is formed. By forming the oxide film, the active region and the field region are separated.

  Next, as shown in FIG. 4B, a gate insulating film and a conductive layer such as polysilicon (polycrystalline silicon) are sequentially deposited on the entire surface of the semiconductor substrate 100 to form a lithography technique or an RIE technique (Reactive Ion Etching; The gate insulating film and the conductive layer are selectively removed by an etching process using a gate electrode pattern mask by a reactive ion etching technique), and the gate insulating film (see FIG. And a gate electrode 122 are formed. Here, the electrode width of the gate electrode 122_10 of the pixel array unit 10 is limited to 0.2 μm or less.

  Next, as shown in FIG. 4 (3), silicon nitride SiN is formed on the entire surface of the semiconductor substrate 100, and the silicon nitride film is etched back to the gate electrode 122 side by the RIE technique to form both sides of the gate electrode 122. Sidewalls 124 are formed.

  Next, as illustrated in FIG. 4D, the semiconductor substrate is formed by an ion implantation technique, a lithography technique, or the like using a mask that limits the charge generation unit 32 or the extension diffusion region 120 in the semiconductor substrate 100 of the pixel array unit 10. Impurity ions are implanted into the active region 100 to form photodiodes and extension diffusion regions 120 (source / drain regions). For example, when the semiconductor substrate 100 is a P-type semiconductor substrate, n-type impurity ions are implanted to form photodiodes and extension diffusion regions 120. At this time, since the gate electrode 122 functions as a mask, the extension diffusion region 120 is formed in a self-aligning manner.

  Next, as shown in FIG. 4 (5), a silicon nitride SiN film is formed on the entire surface of the semiconductor substrate 100, and a lithography technique or an RIE technique is performed using a mask that separates the pixel array section 10 and the peripheral circuit section 11. By removing the silicon nitride SiN on the peripheral circuit unit 11 side and leaving the silicon nitride SiN only in the pixel array unit 10, this silicon nitride SiN functions as a salicide prevention film. That is, silicon nitride SiN that functions as a salicide prevention film exists only on the pixel array unit 10.

  Next, as shown in FIG. 4 (6), a salicide process is performed to form a silicide layer 140 on the surface of the gate electrode 122_11 and the extension diffusion region 120_11 (source / drain region) of the peripheral circuit portion 11. That is, a metal film (for example, Co) is formed on the entire surface of the semiconductor substrate 100, heat treatment is performed, and only the metal film and the silicon layer are reacted so that the gate electrode 122_11 of the peripheral circuit portion 11 and the extension diffusion region 120_11 (source) Co silicide is formed only in the / drain region.

  In this salicide process, a high melting point metal film (Co, W, etc.) is deposited on the entire surface of the semiconductor substrate 100 containing silicon nitride SiN that functions as a salicide prevention film, and heat treatment is performed. The silicide layer 140 is formed at the interface between the metal film and the silicon layer so that silicon reacts. Since the semiconductor substrate 100, the gate electrode 122, and the like are silicon materials, the silicide layer 140 is formed on the extension diffusion region 120_11 on the peripheral circuit unit 11 side and the gate electrode 122_11, but the pixel array unit 10 side is used as a salicide prevention film. Since the masking is performed by the functioning silicon nitride SiN, the silicide layer 140 is not formed on the pixel array unit 10 side.

  Next, as shown in FIG. 4 (7), the unreacted metal film is removed by the WET etching technique.

  Thereafter, after forming silicon nitride SiN as an insulating protective film 130 on the entire surface of the semiconductor substrate 100, an interlayer insulating film 132 such as silicon oxide SiO2 is further formed, and the interlayer insulating film 132 is formed by a chemical mechanical polishing (CMP) technique. If the surface is flattened to such an extent that the surface irregularities are eliminated, the configuration of the comparative example shown in FIG. In the present embodiment, the degree of shaving in this planarization step is increased and the process proceeds to the gate electrode metal replacement step.

  In the gate electrode metal replacement step, first, as shown in FIG. 5A, silicon nitride SiN is formed as an insulating protective film 130 on the entire surface of the semiconductor substrate 100 in the state shown in FIG. An interlayer insulating film 132 such as silicon SiO2 is formed.

  Next, as shown in FIG. 5B, planarization is performed to such an extent that the upper portion of the gate electrode 122 is exposed by the CMP technique.

  Next, as shown in FIG. 5 (3), a resist film is formed on the entire surface of the semiconductor substrate 100, and the pixel array is subjected to an etching process using a mask that separates the pixel array portion 10 and the peripheral circuit portion 11 by lithography. The resist film on the portion 10 side is removed, leaving the resist only in the peripheral circuit portion 11.

  Next, as shown in FIG. 5D, the silicon nitride SiN is etched by the DRY etching technique until the polysilicon of the gate electrode 122_10 of the pixel array section 10 is exposed.

  Further, as shown in FIG. 5 (5), the polysilicon of the gate electrode 122_10 of the pixel array section 10 is etched by the DRY etching technique to remove the polysilicon, thereby forming a gate electrode groove.

  Next, as shown in FIG. 6 (1), titanium nitride TiN is deposited on the entire surface of the silicide layer 140 by a PVD (Physical Vapor Deposition) technique to a thickness of 10 nm, and CVD (Chemical Vapor Deposition: Chemical Vapor Deposition). A metal film such as tungsten W of 150 nm is formed by a growth method) technique. By so doing, a metal material is embedded in the gate electrode groove formed in the step shown in FIG. In other words, the gate electrode 122_10 existing up to the step shown in FIG. 5 (4) is a disposable gate.

  Next, as shown in FIG. 6B, the excess metal film is removed at a high selection ratio (insulating interlayer film / metal film selection ratio of 50 or more) by CMP technique, and the gate electrode 122_10 of the pixel array section 10 is obtained. Only leave the metal film. Since the electrode width of the gate electrode 122_10 of the pixel array section 10 is limited to 0.2 μm or less, erosion can be suppressed and processing can be performed with high accuracy. Polishing conditions: polishing apparatus: EPO222 (manufactured by Ebara Seisakusho), slurry: W2000 (manufactured by Cabot), 200 cc / min, polishing pressure: 3 psi, platen rotation speed: 90 rpm, head rotation speed: 91 rpm, polishing time: torque type EPD + 20% Over, cleaning chemical: oxalic acid-based chemical, 30 sec.

  Next, as shown in FIG. 6C, the interlayer insulating film 132 such as silicon oxide SiO2 is removed by a WET technique (using an HF reagent).

  Next, as shown in FIG. 6 (4), silicon nitride SiN is formed as an insulating protective film 130 on the entire surface of the semiconductor substrate 100, and silicon oxide SiO2 is formed as an interlayer insulating film 132 thereon. Then, the structure of the present embodiment shown in FIG. 3A is obtained by flattening the surface of the interlayer insulating film 132 to a level that eliminates unevenness by a chemical mechanical polishing (CMP) technique.

  In this manner, once the pixel array section 10 is also formed with the polysilicon gate electrode 122 in the same manner as the peripheral circuit section 11, and then the polysilicon gate electrode 122_10 is replaced with a metal material, For the transistor of the pixel array section 10, a metal gate electrode 122_10 that does not include the silicide layer 140 is formed. By adopting such a replacement process with a metal material, it is possible to selectively replace only the gate electrode 122_10 of the pixel array section 10 with a metal film without using a fine mask, so that the charge generation section 32 (photodiode). Therefore, the contact resistance of the gate electrode 122_10 can be lowered, and the signal delay can be improved without lowering the sensitivity.

  Here, in the present embodiment, only the gate electrode 122_10 of the transistor of the pixel signal generation unit 5 is replaced with a metal material, and the gate electrode 122_11 of the transistor of the peripheral circuit unit 11 is not replaced with a metal including the extension diffusion region 120_11. The reason why the configuration in which the layer 140 is formed, that is, the configuration in which only the gate electrode 122_10 of the pixel array portion 10 is replaced with a metal material will be described.

  First, the gate width of the pixel array section 10 can be strictly limited to 0.2 μm or less, for example, as the device becomes finer, but the peripheral circuit section 11 is difficult to design. This is because if the gate electrode 122_11 of the peripheral circuit portion 11 is also replaced with a metal material, erosion and dishing of the peripheral circuit portion 11 are likely to occur during CMP of the metal material, and the variation in gate height increases. By replacing the “only” gate electrode 122 — 10 “only” of the pixel array section 10 with a metal material, there is an advantage that a process can be constructed without severely restricting the peripheral circuit section 11.

  Here, there is a portion in the peripheral circuit portion 11 that has a large gate length and dishing at the time of CMP of a metal material. However, it can be said that such a portion does not need to be silicided in the first place. For example, even in a normal logic, it is conceivable that a fine portion is silicided and a rough portion of a peripheral circuit is put into a silicide block and not silicided.

  From this point of view, if the problem of substituting the gate electrode 122 with a metal material is only a problem at the time of CMP processing, both the pixel array unit 10 and the peripheral circuit unit 11 have fine portions (about the gate electrode 122). Is replaced with a metal material to form a metal gate, and the portion with a large gate length can be replaced with a polysilicon gate (poly gate: no silicidation) without replacing the metal material. It can be said that there is no need to make a separate gate. In other words, it can be said that the necessity of only the pixel array portion 10 being a metal gate is thin only by the problem of CMP processing of a metal material.

  On the other hand, the gate electrode 122 is formed of polysilicon for both the pixel array unit 10 and the peripheral circuit unit 11, and the silicide layer 140 is formed only in the transistor part on the peripheral circuit unit 11 side, and then the gate of the pixel array unit 10 is formed. If a mechanism is used to replace the polysilicon of the electrode 122_10 with a metal material, it can be created with a rough mask that separates the pixel array portion 10 side and the peripheral circuit portion 11 side, and there is no need to tighten the misalignment specifications. The advantage that the manufacturing cost can be reduced by reducing the mask cost and the number of times of reproduction can be obtained rather than replacing only the fine gate with a metal material.

  For example, both the pixel array unit 10 side and the peripheral circuit unit 11 side have the advantage that the extension diffusion region 120 can be formed in a self-aligned manner using the gate electrode 122 and the sidewall 124, and the pixel array unit 10 side There is also an advantage that when the polysilicon of the gate electrode 122_10 is replaced with a metal material, it can be formed in a self-aligned manner using the sidewall 124.

  It is also conceivable that the silicide layer 140 is not formed only in the charge generation unit 32 of the pixel array unit 10 and the silicide layer 140 is formed in the transistor portions of the pixel array unit 10 and the peripheral circuit unit 11. However, in this case, in the pixel array unit 10, it is necessary to create a portion where the silicide layer 140 is formed (the transistor portion of the pixel signal generation unit 5) and a portion where the silicide layer 140 is not formed (the charge generation unit 32 portion). There is a problem that masks and misalignment specs become severe. From this point of view, in the case of the present embodiment, the entire pixel array unit 10 is treated as a portion where the silicide layer 140 is not formed, and therefore, it can be created with a rough mask that separates the pixel array unit 10 side and the peripheral circuit unit 11 side, There is no need to tighten the misalignment specifications.

  As described above, the conditions required for the pixel array unit 10 (at least, the silicide layer 140 is not formed in the charge generation unit 32, but the resistance of the gate electrode 122_10 is desired to be reduced), and the conditions required for the peripheral circuit unit 11 are satisfied. As a mechanism to respond flexibly and in a well-balanced manner (the electrode width of the gate electrode 122_11 varies and the resistance of the gate electrode 122_11 and the extension diffusion region 120_11 is desired to be small), a silicide layer 140 is formed on the transistor of the peripheral circuit portion 11, It is effective to adopt a mechanism in which the gate electrode 122_10 is replaced with a replacement metal gate without forming the silicide layer 140 in the transistor on the pixel array portion 10 side.

<< Modification >>
The above manufacturing process is an example, and various modifications are possible. Hereinafter, some of the modified examples will be briefly described. Each modification can be freely combined. <Modification 1>
In the steps shown in FIGS. 5 (1) and 6 (4), SiOC or SiOF may be used instead of silicon oxide SiO2. Incidentally, SiOC and SiOF have a smaller dielectric constant and lower conversion efficiency than silicon oxide SiO2, and are difficult to process.

<Modification 2>
In the step shown in FIG. 5 (4), silicon nitride SiN may be etched by the WET technique instead of the DRY etching technique. The WET technique has an advantage that the semiconductor substrate 100 is not damaged compared to the DRY etching technique. However, there is a problem that the processing accuracy is affected by the chemical solution that can take the etching selectivity.

<Modification 3>
Depending on the specifications (for example, threshold voltage) required for the transistor, tantalum Ta, hafnium Hf, titanium Ti, ruthenium Ru and alloys thereof are used in place of tungsten W in the process shown in FIG. May be.

<Modification 4>
In the step shown in FIG. 6B, an excess metal film may be removed by the DRY etching technique instead of the CMP technique.

<Modification 5>
In the step shown in FIG. 5B, instead of the CMP technique, the SiO2 may be shaved by the DRY etching technique so that the upper portion of the gate electrode 122 is exposed. The DRY etching technique has an advantage that the processing is easier than the CMP technique. However, when the DRY etching technique is applied, in order to make the upper portion of the gate electrode 122 exposed, the other portions are actually cut more as shown by the dotted line in the drawing. This influence is dragged to the subsequent process. When the metal film is formed in the process shown in FIG. 6 (1), the metal film is formed to the extent that the metal film is excessively shaved. In the process shown, when removing the excess metal film, it becomes difficult to remove the metal film present in the excessively shaved portion.

<Modification 6>
In replacing the gate electrode 122_10 of the transistor constituting the pixel signal generation unit 5 with a metal material, a gate electrode groove is formed in the process shown in FIG. 5 (5), and then the metal material is used in the process shown in FIG. 6 (1). Although the gate electrode trench is buried, the manufacturing method of replacing the gate electrode 122_10 with a metal material is not limited to this. For example, as described in Patent Document 1, the gate electrode 122_11 of the peripheral circuit unit 11 is formed by a silicidation reaction, and the gate electrode 122_10 of the pixel signal generation unit 5 of the pixel array unit 10 is formed by a metal material replacement reaction. Also good.

It is a schematic block diagram of the CMOS solid-state imaging device which is one Embodiment of a solid-state imaging device. It is a figure which shows the typical circuit structural example (4TR structure) of the unit pixel used for the solid-state imaging device shown in FIG. It is the figure which showed the outline | summary of the cross-sectional structure which paid its attention to the boundary part of a pixel array part and a peripheral circuit part. It is sectional drawing explaining the manufacturing process of the solid-state imaging device of this embodiment (common with a comparative example). It is sectional drawing explaining the manufacturing process (gate electrode metal substitution process) of the solid-state imaging device of this embodiment. It is sectional drawing explaining the manufacturing process (gate electrode metal substitution process) of the solid-state imaging device of this embodiment (continuation of FIG. 5).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 10 ... Pixel array part, 100 ... Semiconductor substrate, 11 ... Peripheral circuit part, 120 ... Extension diffusion area, 122 ... Gate electrode, 124 ... Side wall, 130 ... Insulating protective film, 132 ... Interlayer insulating film , 140... Silicide layer, 3... Unit pixel, 32... Charge generation section, 34... Read selection transistor, 36... Reset transistor, 38 ... Floating diffusion, 40. Signal generator

Claims (4)

A charge generation unit that generates a signal charge, and a pixel array unit that includes a unit pixel including a pixel signal generation unit that includes a transistor and generates a pixel signal based on the signal charge generated by the charge generation unit;
A drive control unit that is disposed around the pixel array unit, includes a transistor, and has a control circuit function for reading out a pixel signal output from a unit pixel of the pixel array unit to the outside of the pixel array unit or the device; Or a peripheral circuit unit provided with a signal processing unit for processing a pixel signal read from the pixel signal generation unit,
Silicide is formed in the region of the transistor constituting the peripheral circuit portion,
A solid-state imaging device, wherein no silicide is formed in a region of a transistor constituting the charge generation unit and the pixel signal generation unit, and a gate electrode of the transistor is formed of a metal material. Side walls are formed on the side surfaces of the gate electrode,
Source / drain regions are formed on both sides of the gate electrode so as to be in contact with the side surface of the sidewall,
The metal constituting the gate electrode of the transistor constituting the pixel signal generation unit is a metal whose electrode material existing in the gate electrode portion is lower in resistance than the silicide in a self-aligning manner using the sidewall. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is a substitution metal formed by substitution with a material. A charge generation unit that generates a signal charge; and a pixel array unit that includes a transistor and includes a unit pixel including a pixel signal generation unit that generates a pixel signal based on the signal charge generated by the charge generation unit; A drive control unit that is disposed around the pixel array unit, includes a transistor, and has a control circuit function for reading out a pixel signal output from a unit pixel of the pixel array unit to the pixel array unit or the apparatus; or A manufacturing method of a solid-state imaging device including a peripheral circuit unit provided with a signal processing unit that processes a pixel signal read from the pixel signal generation unit,
Forming a transistor region constituting the peripheral circuit unit at the same time as forming a transistor region constituting the charge generation unit and the pixel signal generation unit;
Forming silicide in a region of a transistor constituting the peripheral circuit unit, so that no silicide is formed in a region of the transistor constituting the charge generation unit and the pixel signal generation unit of the pixel array unit;
And a step of replacing the electrode material existing in the gate electrode portion of the transistor constituting the pixel signal generation unit of the pixel array unit with a metal material after the step of forming the silicide. Device manufacturing method. The step of forming the transistor region includes a step of forming a sidewall on the side surface of the gate electrode and a step of forming source / drain regions constituting the transistor so as to be in contact with the side surface of the sidewall on both sides of the gate electrode. Including
The step of replacing the electrode material existing in the gate electrode portion with a metal material is performed by using the sidewall in a self-aligning manner so that the electrode material existing in the gate electrode portion is more resistant than the silicide. It replaces with a low metal material. The manufacturing method of Claim 3 characterized by the above-mentioned.

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