JP2009188290A - Power semiconductor device - Google Patents

Abstract

A power semiconductor device with low on-voltage is provided.
In a power semiconductor device that is an IEGT, a p-type collector layer, an n-type buffer layer, and an n-type base layer are provided in this order on a collector electrode, and an n-type base is formed on the n-type base layer. Main cells 21 and dummy cells 22 are alternately provided along a direction parallel to the upper surface of the layer 15. A trench gate electrode 18 is provided between the main cell 21 and the dummy cell 22. In the main cell 21, a p-type base layer 23 is provided, and an n-type emitter layer 24 is provided in a part of the upper layer portion. In the dummy cell 22, p-type dummy layers 26 and n-type dummy layers 27 are alternately provided along the direction in which the trench gate electrode 18 extends.
[Selection] Figure 1

Description

  The present invention relates to a power semiconductor device, and more particularly to an insulated gate bipolar power semiconductor device.

  Conventionally, IGBTs (Insulated Gate Bipolar Transistors) have been developed as power semiconductor devices. In the IGBT, a p-type collector layer and an n-type base layer are stacked in this order on a collector electrode, and a plurality of stripe-shaped trench gate electrodes are provided thereon. A p-type base layer is provided in a region between the trench gate electrodes, and an n-type emitter layer connected to the emitter electrode is provided in a part of the upper layer portion of the p-type base layer. In the IGBT, when a positive potential is applied to the trench gate electrode, the p-type base layer becomes conductive, electrons are introduced from the n-type emitter layer, and holes are introduced from the p-type collector layer. A bipolar current flows between the emitter electrode and the emitter electrode.

  However, such an IGBT has a problem that the on-voltage increases when the breakdown voltage is increased. In order to reduce the on-voltage of the IGBT, a technique has been proposed in which the n-type emitter layer is formed only in a part of the region between the trench gate electrodes (see, for example, Patent Document 1). Thereby, only a part of the region between the trench gate electrodes functions as a main cell through which a current flows, and the other region becomes a dummy cell that does not contribute to conduction. As a result, the holes in the n-type base layer are not easily discharged, and the amount of injected electrons is relatively increased. This effect is called an electron injection promotion (IE) effect. This effect improves the carrier concentration in the upper layer portion of the n-type base layer, that is, the portion on the p-type base layer side, lowers the on-resistance, and lowers the on-voltage. The semiconductor device having such a structure is called IEGT (Injection Enhanced Gate Transistor).

  In this IEGT, up to a certain critical point, the effect of promoting electron injection increases as the ratio of dummy cells increases and the ratio of main cells decreases. However, when the ratio of dummy cells is increased beyond the critical point, there is a problem that the on-voltage increases.

JP 2002-100770 A

  An object of the present invention is to provide a power semiconductor device having a low on-voltage.

  According to one aspect of the present invention, a collector electrode, an emitter electrode, a p-type collector layer connected to the collector electrode, an n-type base layer provided on the p-type collector layer, and the n-type base A main cell and a dummy cell arranged on a layer along a direction parallel to an upper surface of the n-type base layer, and a trench gate electrode provided between the main cell and the dummy cell. Comprises a p-type base layer and an n-type emitter layer formed in a part of an upper layer portion of the p-type base layer and connected to the emitter electrode, and the dummy cell includes a p-type dummy layer, There is provided a power semiconductor device comprising an n-type dummy layer.

  According to the present invention, a power semiconductor device having a low on-voltage can be realized.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a first embodiment of the present invention will be described.
FIG. 1 is a perspective view illustrating a semiconductor portion of the power semiconductor device according to this embodiment.
FIG. 2 is a cross-sectional view illustrating the power semiconductor device according to this embodiment.
FIG. 3 is a top view illustrating the power semiconductor device according to this embodiment.
4 is a cross-sectional view taken along line AA ′ shown in FIG.
FIG. 5 is a cross-sectional view taken along line BB ′ shown in FIG.
The power semiconductor device according to the present embodiment is IEGT.

  As shown in FIGS. 1 to 5, in the power semiconductor device 1 according to the present embodiment, a collector electrode 11 made of a metal or an alloy is provided, and a semiconductor portion 12 is provided on the collector electrode 11. ing. In other words, the collector electrode 11 is formed on the entire lower surface of the semiconductor portion 12. The semiconductor portion 12 is made of a semiconductor material, for example, silicon, and acceptors and donors are locally introduced, so that a p-type layer having a p-type conductivity and a conductive type will be described below. The n-type n-type layer is three-dimensionally arranged.

  A p-type collector layer 13 is provided in the lowermost layer portion of the semiconductor portion 12, that is, the portion in contact with the collector electrode 11. Thereby, the p-type collector layer 13 is connected to the collector electrode 11. An n-type buffer layer 14 is provided on a portion of the semiconductor portion 12 on the p-type collector layer 13, and an n-type base layer 15 is provided thereon. The donor concentration of the n-type base layer 15 is lower than the donor concentration of the n-type buffer layer 14.

  On the other hand, in the upper layer portion of the semiconductor portion 12, a plurality of groove-like trenches 16 are formed in parallel to each other from the upper surface side of the semiconductor portion 12. The lower end of the trench 16 reaches the n-type base layer 15. The width of the region between the trenches 16 is not constant, and relatively narrow regions and relatively wide regions are alternately arranged. A gate insulating film 17 made of, for example, a silicon oxide film is formed on the inner surface of each trench 16, and a trench gate electrode 18 made of, for example, polysilicon is embedded in each trench 16. Thereby, the trench gate electrode 18 is insulated from the semiconductor portion 12 by the gate insulating film 17. The trench gate electrode 18 is connected to a gate electrode (not shown) in a region (not shown) of the power semiconductor device 1.

  Of the regions between the trenches 16 in the semiconductor portion 12, the relatively narrow region is the main cell 21, and the relatively wide region is the dummy cell 22. That is, the shapes of the main cell 21 and the dummy cell 22 are each a stripe shape, and are alternately arranged on the n-type base layer 15 along a direction parallel to the upper surface of the n-type base layer 15. It is provided between the main cell 21 and the dummy cell 22. For example, the width of the dummy cell 22 is about 2 to 5 times the width of the main cell 21.

  In the main cell 21, a p-type base layer 23 is provided. The p-type base layer 23 is in contact with the n-type base layer 15, and in this embodiment, the interface between the p-type base layer 23 and the n-type base layer 15 is located at substantially the same height as the lower end of the trench 16. Yes. A plurality of n-type emitter layers 24 are intermittently formed in the upper layer portion of the p-type base layer 23 along the direction in which the trench 16 extends. That is, on the upper surface of the main cell 21, the p-type base layer 23 and the n-type emitter layer 24 are alternately arranged along the direction in which the trench 16 extends. For example, the length of the p-type base layer 23 in this arrangement direction is longer than the length of the n-type emitter layer 24.

  On the other hand, in the dummy cell 22, p-type dummy layers 26 and n-type dummy layers 27 are alternately arranged along the direction in which the trench 16 extends. That is, each of the p-type dummy layer 26 and the n-type dummy layer 27 crosses the dummy cell 22 in the width direction, and is in contact with both of the two gate insulating films 17 disposed on both sides of the dummy cell 22. Further, the interface between the p-type dummy layer 26 and the n-type dummy layer 27 is located at substantially the same height as the lower end of the trench 16. The p-type dummy layer 26 and the n-type dummy layer 27 are in contact with each other, and both are in contact with the n-type base layer 15. That is, the n-type dummy layer 27 is in contact with both the n-type base layer 15 and the p-type dummy layer 26.

  As will be described later, the main cell 21 functions as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Therefore, the impurity concentration and arrangement period of the p-type base layer 23 and the n-type emitter layer 24 in the main cell 21 are determined according to the performance required for this MOSFET. On the other hand, the impurity concentration of the p-type dummy layer 26 and the n-type dummy layer 27 in the dummy cell 22 is set to such a concentration that the depletion layer can sufficiently spread. Further, the lengths of the p-type dummy layer 26 and the n-type dummy layer 27 are determined in accordance with these impurity concentrations. For example, the acceptor amount included in each p-type dummy layer 26 and the donor amount included in each n-type dummy layer 27 are determined to be equal to each other.

  Thus, the impurity concentration and arrangement period of the p-type base layer 23 and the n-type emitter layer 24 in the main cell 21 and the impurity concentration and arrangement period of the p-type dummy layer 26 and the n-type dummy layer 27 in the dummy cell 22 are: Since they are determined based on mutually different ideas, in general, the two do not match. For example, the impurity concentration of the p-type base layer 23 and the n-type emitter layer 24 in the main cell 21 is higher than the impurity concentration of the p-type dummy layer 26 and the n-type dummy layer 27 in the dummy cell 22. The arrangement period of the type emitter layer 24 is shorter than the arrangement period of the p-type dummy layer 26 and the n-type dummy layer 27.

  The p-type dummy layer 26 and the n-type dummy layer 27 may be formed by implanting an acceptor and a donor into predetermined regions on the upper surface of the semiconductor portion 12, respectively. The p-type dummy layer 26 may be formed by implanting an acceptor into a part of the upper surface, and the region between the p-type dummy layers 26 where no acceptor is implanted may be used as the n-type dummy layer 27. .

  In addition, an insulating film 28 is provided on the semiconductor portion 12, and an emitter electrode 29 is provided on the insulating film 28. In the insulating film 28, a groove-like opening 28a extending in the direction in which the main cell 21 extends is formed immediately above the main cell 21. The emitter electrode 29 is connected to the p-type base layer 23 and the via via the opening 28a. The n-type emitter layer 24 is connected. On the other hand, the p-type dummy layer 26 and the n-type dummy layer 27 are insulated from the emitter electrode 29 by the insulating film 28.

Next, the operation of the power semiconductor device 1 according to this embodiment configured as described above will be described.
FIG. 6 is a cross-sectional view illustrating the operation of the power semiconductor device according to this embodiment.
In FIG. 6, the electron flow e is schematically shown by a solid line with an arrow, and the hole flow h is schematically shown by a broken line with an arrow.

  As shown in FIG. 6, for example, when a ground potential is applied to the emitter electrode 29 and a potential higher than the ground potential is applied to the collector electrode 11, a potential higher than the ground potential is applied to the trench gate electrode 18. An inversion layer (not shown) is formed in a region of the mold base layer 23 in contact with the gate insulating film 17. As a result, the MOSFET formed in the main cell 21 is turned on, and electrons flow from the n-type emitter layer 24 to the n-type base layer 15 through the inversion layer. Along with this, holes flow from the p-type collector layer 13 to the n-type base layer 15 via the n-type buffer layer 14. As a result, a bipolar current flows between the collector electrode 11 and the emitter electrode 29.

  At this time, since the emitter electrode 29 is connected only to the main cell 21 and not to the dummy cell 22, holes in the n-type base layer 15 are connected to the dummy cell 22 as shown by a broken line h in FIG. Is not discharged to the outside of the semiconductor portion 12 via the main body 21 but is discharged to the outside of the semiconductor portion 12 only via the main cell 21. As described above, in the power semiconductor device 1, the main cells 21 that contribute to conduction are thinned out, and the dummy cells 22 that do not contribute to conduction are provided between the main cells 21. Thus, the amount of holes flowing into the p-type base layer 23 is reduced. Thereby, the amount of electrons injected through the n-type emitter layer 24 is relatively increased, and the carrier concentration of the n-type base layer 15 on the p-type base layer 23 side is increased. As a result, the on-resistance is lowered and the on-voltage is lowered.

  In the power semiconductor device 1, since the n-type dummy layer 27 is provided in the dummy cell 22, electrons introduced from the n-type emitter layer 24 into the n-type base layer 15 through the p-type base layer 23. However, it conducts in the n-type dummy layer 27 and spreads toward the center in the width direction of the dummy cell 22. For this reason, in the power semiconductor device 1, the spreading resistance of electrons in the arrangement direction of the main cell 21 and the dummy cell 22 is low. As a result, a dead space in which electrons do not easily reach is not formed immediately below the central portion of the dummy cell 22 in the n-type base layer 15, and the entire n-type base layer 15 is effectively used as a conductive region. Can do. As a result, the on-resistance is lowered.

  On the other hand, when a ground potential is applied to the trench gate electrode 18, the inversion layer disappears from the p-type base layer 23, and the MOSFET formed in the main cell 21 is turned off. As a result, the voltage between the collector electrode 11 and the emitter electrode 29 rises, and the n-type dummy layer 27 passes from the collector electrode 11 through the p-type collector layer 13, the n-type buffer layer 14, and the n-type base layer 15. Positive potential is transmitted. On the other hand, since the p-type dummy layer 26 is coupled to the trench gate electrode 18 via the gate insulating film 17, the potential does not increase so much with respect to the ground potential applied to the trench gate electrode 18. .

  As a result, in the relationship between the n-type base layer 15 and the n-type dummy layer 27 and the p-type dummy layer 26, a relatively positive potential is applied to the n-type base layer 15 and the n-type dummy layer 27, and p A relatively negative potential is applied to the mold dummy layer 26. As a result, a reverse bias is applied to the pn junction surface between the n-type base layer 15 and the n-type dummy layer 27 and the p-type dummy layer 26, and the n-type base layer 15, the n-type dummy layer 27, and A depletion layer extends toward the inside of the p-type dummy layer 26. As a result, the breakdown voltage of the power semiconductor device 1 is improved.

Next, the effect of this embodiment will be described.
As described above, according to the present embodiment, since the n-type dummy layer 27 is provided in the dummy cell 22, electrons can be conducted in the n-type dummy layer 27, and the arrangement of the main cell 21 and the dummy cell 22. The spreading resistance of electrons in the direction is low, and the on-resistance is low.

  In this embodiment, the shape of the trench gate electrode 18 is a stripe shape, and the p-type dummy layer 26 and the n-type dummy layer 27 are alternately arranged along the direction in which the trench gate electrode 18 extends. Thereby, since the n-type dummy layer 27 crosses the dummy cell 22 in the width direction, the effect of conducting electrons in the arrangement direction of the main cell 21 and the dummy cell 22 is high. Further, since the arrangement direction of the main cell 21 and the dummy cell 22, the arrangement direction of the p-type dummy layer 26 and the n-type dummy layer 27, and the arrangement direction of the n-type emitter layer 24 are orthogonal to each other, Is easy to refine.

  Furthermore, since the n-type dummy layer 27 is in contact with both the n-type base layer 15 and the p-type dummy layer 26, the above-described effect of conducting electrons is high.

  Thus, according to the present embodiment, the on-voltage can be reduced by providing the n-type dummy layer 27 in the dummy cell 22. Thereby, the proportion of dummy cells can be increased, the electron injection promoting effect can be further increased, and the electron current can be further increased. As a result, the ON voltage is further reduced.

Next, a second embodiment of the present invention will be described.
FIG. 7 is a cross-sectional view illustrating a power semiconductor device according to this embodiment.
As shown in FIG. 7, in the power semiconductor device 2 according to the present embodiment, the trench 16 is formed deeper than the power semiconductor device 1 (see FIG. 1) according to the first embodiment described above. The trench gate electrode 18 extends to a lower position. Further, the p-type dummy layer 26 and the n-type dummy layer 27 (see FIG. 1) of the dummy cell 22 are also formed deeply to the position of the lower end of the trench gate electrode 18. On the other hand, the depth of the p-type base layer 23 in the main cell 21 is the same as that in the first embodiment. Therefore, the lower surfaces of the p-type dummy layer 26 and the n-type dummy layer 27 and the lower end of the trench gate electrode 18 are located below the interface between the n-type base layer 15 and the p-type base layer 23, and the p-type collector When viewed from the layer 13 side, the p-type base layer 23 is in a position recessed from the trench gate electrode 18. Other configurations in the present embodiment are the same as those in the first embodiment.

  According to the present embodiment, since the trench gate electrode 18 extends below the p-type base layer 23, a part of the n-type base layer 15 is located in a region between the trench gate electrodes 18. This part is a part through which holes flowing into the p-type base layer 23 always pass, but an electric field is not so much applied, and the force to move the holes toward the p-type base layer 23 is weak. For this reason, a barrier is formed against the movement of holes, and the effect of promoting electron injection is further increased. Operations and effects other than those described above in the present embodiment are the same as those in the first embodiment described above.

Next, a third embodiment of the present invention will be described.
FIG. 8 is a cross-sectional view illustrating a power semiconductor device according to this embodiment.
As shown in FIG. 8, the power semiconductor device 3 according to the present embodiment includes an n-type base layer 15 and a p-type semiconductor device 1 as compared with the power semiconductor device 1 according to the first embodiment described above (see FIG. 1). The difference is that an n-type carrier stop layer 31 is provided between the base layer 23 and the base layer 23. That is, the n-type carrier stop layer 31 is provided between the p-type collector layer 13 and the p-type base layer 23 and is provided so as to cover the p-type base layer 23 when viewed from the p-type collector layer 13 side. It has been. The donor concentration of the n-type carrier stop layer 31 is higher than the donor concentration of the n-type base layer 15. Other configurations in the present embodiment are the same as those in the first embodiment.

  According to the present embodiment, the n-type carrier stop layer 31 having a donor concentration higher than the donor concentration of the n-type base layer 15 is provided between the p-type collector layer 13 and the p-type base layer 23. A barrier when holes flow into the p-type base layer 23 is formed, and the electron injection promoting effect is further increased. Operations and effects other than those described above in the present embodiment are the same as those in the first embodiment described above.

Next, a fourth embodiment of the present invention will be described.
FIG. 9 is a cross-sectional view illustrating a power semiconductor device according to this embodiment.
As shown in FIG. 9, the power semiconductor device 4 according to the present embodiment has an n-type carrier stop layer 31 as compared with the power semiconductor device 3 according to the third embodiment described above (see FIG. 8). The difference is that it is provided on the entire surface of the n-type base layer 15. That is, when viewed from the p-type collector layer 13 side, the n-type carrier stop layer 31 covers both the main cell 21 and the dummy cell 22. Other configurations in the present embodiment are the same as those in the third embodiment described above.

  According to the present embodiment, the n-type carrier stop layer 31 functions as a hole barrier and also functions as a path for conducting electrons in the arrangement direction of the main cell 21 and the dummy cell 22. As a result, the electron injection promoting effect can be further improved, the electron spreading resistance can be reduced, and the on-voltage can be further reduced. Operations and effects other than those described above in the present embodiment are the same as those in the third embodiment described above.

Next, a fifth embodiment of the present invention will be described.
FIG. 10 is a cross-sectional view illustrating a power semiconductor device according to this embodiment.
As shown in FIG. 10, the present embodiment is an example in which the second embodiment and the third embodiment described above are combined. That is, in the power semiconductor device 5 according to the present embodiment, the lower end of the trench gate electrode 18 is located below the interface between the n-type base layer 15 and the p-type base layer 23, and the n-type base An n-type carrier stop layer 31 is provided between the layer 15 and the p-type base layer 23. Thereby, the electron injection promoting effect can be further improved. Other configurations, operations, and effects of the present embodiment are the same as those of the first embodiment.

Next, a sixth embodiment of the present invention will be described.
FIG. 11 is a cross-sectional view illustrating a power semiconductor device according to this embodiment.
As shown in FIG. 11, the present embodiment is an example in which the second embodiment and the fourth embodiment described above are combined. That is, in the power semiconductor device 6 according to this embodiment, the lower end of the trench gate electrode 18 is located below the interface between the n-type base layer 15 and the p-type base layer 23. An n-type carrier stop layer 31 is provided along a virtual plane connecting the lower ends of the trench gate electrodes 18. The n-type carrier stop layer 31 also enters a region between the trench gate electrodes 18 and immediately below the p-type base layer 23. That is, when viewed from the p-type collector layer 13 side, the n-type carrier stop layer 31 covers both the main cell 21 and the dummy cell 22. Other configurations in the present embodiment are the same as those in the first embodiment.

  Thereby, according to the present embodiment, the electron injection promoting effect is further improved, and electrons are easily moved in the arrangement direction of the main cell 21 and the dummy cell 22 via the n-type carrier stop layer 31. The entire base layer 15 can be effectively used as a conductive region, and the on-voltage is reduced. Operations and effects other than those described above in the present embodiment are the same as those in the first embodiment described above.

  While the present invention has been described with reference to the embodiments, the present invention is not limited to these embodiments. For example, those in which those skilled in the art appropriately added, deleted, and changed the design of the above-described embodiments are also included in the scope of the present invention as long as they have the gist of the present invention.

  For example, the arrangement position of the n-type emitter layer 24 in the main cell 21 is not limited to the above-described example, and is connected to the emitter electrode 29 and is configured to constitute a transistor together with the p-type base layer 23 and the trench gate electrode 18. It may be provided, for example, may be provided in stripes on both sides of the upper layer portion of the p-type base layer 23, that is, in a region in contact with the gate insulating film 17. Further, the positional relationship between the p-type dummy layer 26 and the n-type dummy layer 27 in the dummy cell 22 is not limited to the above example. Furthermore, a trench gate electrode may be provided not only between the main cell 21 and the dummy cell 22 but also inside the main cell 21 or inside the dummy cell 22. Furthermore, the formation position of the n-type carrier stop layer 31 is not limited to the above-described example, and may be provided at any position between the p-type collector layer 13 and the p-type base layer 23.

1 is a perspective view illustrating a semiconductor portion of a power semiconductor device according to a first embodiment of the present invention. 1 is a cross-sectional view illustrating a power semiconductor device according to a first embodiment. 1 is a top view illustrating a semiconductor portion of a power semiconductor device according to a first embodiment. It is sectional drawing by the A-A 'line shown in FIG. FIG. 4 is a cross-sectional view taken along line B-B ′ shown in FIG. 3. FIG. 5 is a cross-sectional view illustrating the operation of the power semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view illustrating a power semiconductor device according to a second embodiment of the invention. FIG. 6 is a cross-sectional view illustrating a power semiconductor device according to a third embodiment of the invention. FIG. 6 is a cross-sectional view illustrating a power semiconductor device according to a fourth embodiment of the invention. FIG. 10 is a cross-sectional view illustrating a power semiconductor device according to a fifth embodiment of the invention. It is sectional drawing which illustrates the power semiconductor device which concerns on the 6th Embodiment of this invention.

Explanation of symbols

1, 2, 3, 4, 5, 6 Power semiconductor device, 11 collector electrode, 12 semiconductor portion, 13 p-type collector layer, 14 n-type buffer layer, 15 n-type base layer, 16 trench, 17 gate insulating film, 18 trench gate electrode, 21 main cell, 22 dummy cell, 23 p-type base layer, 24 n-type emitter layer, 26 p-type dummy layer, 27 n-type dummy layer, 28 insulating film, 28a opening, 29 emitter electrode, 31 n Type carrier stop layer, e electron flow, h hole flow

Claims (5)

A collector electrode;
An emitter electrode;
A p-type collector layer connected to the collector electrode;
An n-type base layer provided on the p-type collector layer;
A main cell and a dummy cell arranged on the n-type base layer along a direction parallel to an upper surface of the n-type base layer;
A trench gate electrode provided between the main cell and the dummy cell;
With
The main cell is
a p-type base layer;
An n-type emitter layer formed in a part of an upper layer portion of the p-type base layer and connected to the emitter electrode;
Have
The dummy cell is
a p-type dummy layer;
an n-type dummy layer;
A power semiconductor device comprising:   The power semiconductor device according to claim 1, wherein the n-type dummy layer is in contact with both the n-type base layer and the p-type dummy layer. The trench gate electrode has a stripe shape,
3. The power semiconductor device according to claim 1, wherein the p-type dummy layer and the n-type dummy layer are alternately arranged along a direction in which the trench gate electrode extends.   The lower end of the trench gate electrode is located below the interface between the n-type base layer and the p-type base layer. Semiconductor device.   The n-type carrier stop layer further provided between the p-type collector layer and the p-type base layer and having a donor concentration higher than that of the n-type base layer. 5. The power semiconductor device according to claim 4.

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