JP2009188279A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device and a method of manufacturing the semiconductor device that further improve the reliability of the wiring without increasing the capacitance between the wirings.
A step (a) of forming a wiring trench 2 in an upper portion of an interlayer insulating film 1 formed on a substrate, and a barrier metal film in the wiring trench 2 and on the interlayer insulating film 1 after the step (a). After step (b) and step (b), copper 5 is buried in the wiring groove 2 to form wiring, and after step (c), Si and N are interlayer-insulated. A step (d) for injecting into the film 1 and the wiring and a step (e) for removing the barrier metal film 3 on the interlayer insulating film 1 after the step (d).
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device having a copper wiring having a groove filling structure with respect to an interlayer insulating film having a low dielectric constant formed on a substrate, and a manufacturing method thereof.

  In recent years, the wiring pitch inside a semiconductor device (device) has been reduced, and it has become increasingly important to ensure the reliability of the wiring. Therefore, studies have been made to improve the reliability of the wiring by forming a cap metal layer on the surface of the copper wiring.

Hereinafter, a conventional semiconductor device described in Patent Document 1 and a manufacturing method thereof will be described with reference to the drawings.
FIG. 4 is a flowchart showing a process in the semiconductor device and the manufacturing method thereof described in Patent Document 1.

First, a litho process and an etching process are performed to form a wiring groove 2 in the interlayer insulating film 1 which is a low dielectric constant film.
Second, as pretreatment, annealing is performed to reduce the surface oxide, and then tantalum nitride or tantalum is formed as the barrier metal film 3 (FIG. 4A). Here, the barrier metal film 3 is a metal film for preventing copper on the outer periphery from diffusing into the interlayer insulating film 1.

Third, a seed film 4 is formed on the barrier metal film 3 (FIG. 4B).
Fourth, after copper (Cu) is buried by plating, excess copper and the barrier metal film 3 are removed by Cu · Ta-CMP treatment, and copper is buried only in the wiring trench 2 to form the copper wiring 5. It forms (FIG.4 (c)).

Fifth, after Cu · Ta-CMP, copper oxide (CuO) 6 is formed on the copper wiring 5 to contact the atmosphere once (FIG. 4D).
Sixth, the copper oxide (CuO) 6 formed on the copper wiring 5 is removed by exposure to plasma (FIG. 4E).

  Seventh, subsequently, heat treatment at 350 ° C. or higher is performed in a mixed gas atmosphere of monosilane gas and nitrogen. Thereby, a silicide layer 47 is formed on the surface of the copper wiring 5 (FIG. 4F).

  Eighth, the liner film 10 is formed with a thickness of about 40 nm (FIG. 4G). Here, the liner film 10 is for preventing the copper in the copper wiring 5 from diffusing into an interlayer insulating film (not shown) formed in a later step on the liner film 10. A silicon nitride film or the like having a relatively high relative dielectric constant is used.

Non-Patent Document 1 describes that a CuSiN transition layer is formed on the surface of a copper wiring by GCIB doping.
JP 2000-150517 A S. Kondo, et. al, “Infusion Processing for Reliable Copper Interconnects”, AMC 2006 p. 75

  However, when the semiconductor device manufacturing methods described in Patent Document 1 and Non-Patent Document 1 are combined, the cause is the SiN transition layer 9 formed on the interlayer insulating film 1 between the copper wirings 5 due to GCIB doping. Thus, there is a problem that the capacitance (capacitance) between the copper wirings 5 increases.

FIG. 2B shows Si and N concentration distributions in the semiconductor substrate when the semiconductor device manufacturing methods described in Patent Document 1 and Non-Patent Document 1 are combined.
The surface of the semiconductor substrate has a large amount of collision between Si and N, and the amount of collision becomes lower as it goes into the substrate. Due to this collision energy, the temperature of the semiconductor substrate rises locally despite the ambient temperature, and in the copper wiring portion, a larger amount of CuSiN is formed near the substrate surface, and a smaller amount of CuSiN is formed as it goes into the substrate ( B1 in FIG. This is referred to as a CuSiN transition layer. Since the CuSiN transition layer functions to suppress the surface diffusion of the copper wiring, the EM life of the copper wiring can be improved. On the other hand, at this time, a SiN transition layer 9 of about 20 nm is formed on the surface 8 of the interlayer insulating film 1 which is a low dielectric constant film. The SiN transition layer 9 also has a reduced concentration of Si and N in the depth direction (B2 in FIG. 2B).

  The present invention solves the above-described conventional problems, and provides a semiconductor device and a manufacturing method thereof that can further improve the reliability of wiring without increasing the capacitance between the wirings.

  In order to solve the above problem, a semiconductor device according to claim 1 of the present invention has a wiring made of a conductive film in an upper part of an interlayer insulating film formed on a substrate, and the wiring upper surface has the above-mentioned wiring It has a transition layer of a conductive film and SiN, and the transition layer contains an alloy metal different from the conductive film.

A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the conductive film is made of copper.
Further, a semiconductor device according to claim 3 of the present invention is the semiconductor device according to claim 1 or 2, wherein the alloy metal includes a metal having a resistivity lower than that of Si. Features.

  According to a fourth aspect of the present invention, there is provided the semiconductor device according to the third aspect, wherein the alloy metal includes any one of Al, Ag, Ti, Co, and Ni. It is characterized by being.

  According to a fifth aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: a step (a) of forming a wiring trench in an upper portion of an interlayer insulating film formed on a substrate; and the step (a), A step (b) of forming a barrier metal film in the wiring trench and on the interlayer insulating film; and a step (c) of forming a wiring by embedding a conductive film in the wiring trench after the step (b); A step (d) of implanting Si and N into the interlayer insulating film and the wiring after the step (c); and a step of removing the barrier metal film on the interlayer insulating film after the step (d). (E).

  According to a sixth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the fifth aspect, wherein the step (d) includes performing a Si gas and N implantation process as a gas cluster. -It is performed by the ion beam method.

  According to a seventh aspect of the present invention, there is provided a semiconductor device manufacturing method according to the fifth or sixth aspect, wherein the step (c) includes seeding the wiring trench. The step of embedding the conductive film by forming a film is characterized in that the seed film contains a metal having a resistivity lower than that of the Si.

  Moreover, the manufacturing method of the semiconductor device according to claim 8 of the present invention is the manufacturing method of the semiconductor device according to claim 7, wherein the seed film is made of a metal having a resistivity lower than that of Si, Any one of Al, Ag, Ti, Co, and Ni is contained.

  A method for manufacturing a semiconductor device according to a ninth aspect of the present invention is the method for manufacturing a semiconductor device according to any one of the fifth to eighth aspects, wherein the step (d) and the step (e) ), A transition layer of the conductive film and SiN is formed on the upper surface of the wiring.

  A method for manufacturing a semiconductor device according to a tenth aspect of the present invention is the method for manufacturing a semiconductor device according to any one of the fifth to ninth aspects, wherein copper is used as the conductive film. Features.

As described above, according to the present invention, even if the CuSiN transition layer is formed on the upper surface of the wiring made of the conductive film, the formation of the SiN transition layer on the interlayer insulating film between the wirings can be prevented.
Therefore, the reliability of the wiring can be further improved without increasing the capacitance between the wirings.

Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be specifically described with reference to the drawings.
FIG. 1 is a flowchart showing a process in a semiconductor device and a manufacturing method thereof according to the present embodiment.

First, a litho process and an etching process are performed to form a wiring groove 2 in the interlayer insulating film 1 which is a low dielectric constant film (k3.0).
Second, as a pretreatment, annealing is performed in a hydrogen (H ₂ ) atmosphere at 280 ° C. for 60 seconds to reduce the surface oxide, and then 5 nm of tantalum nitride and 5 nm of tantalum are formed as the barrier metal film 3. (FIG. 1 (a)). Here, the barrier metal film 3 is a metal film for preventing copper from diffusing into the interlayer insulating film 1 on the outer periphery thereof.

  Third, a seed film 4 is formed to a thickness of 30 nm on the barrier metal film 3 (FIG. 1B). At this time, the seed Cu has about 5% Al. The reason why Al is contained in Cu is to improve the reliability of wiring such as EM and SM.

  Fourth, after copper (Cu) is buried by plating, annealing is performed at about 300 ° C., and then only excess copper is removed by Cu-CMP treatment (FIG. 1C). At this time, Al in the seed film spreads throughout the Cu wiring by annealing, and CuAl is formed.

  Conventionally, even the barrier metal film 3 on the interlayer insulating film 1 between the copper wirings 5 has been removed together, but in this embodiment, a slurry having a slower polishing rate of tantalum nitride and tantalum than copper (CuAl). By using the Cu-CMP process, the barrier metal film 3 is left without being removed.

Fifthly, after the Cu-CMP treatment, the oxide (CuO, AlO) 6 is formed on the copper wiring 5 because it is once brought into contact with the atmosphere (FIG. 1D).
Sixth, the oxide 6 formed on the copper wiring 5 is removed by exposure to hydrogen (H ₂ ) plasma at a temperature of about 250 ° C. (FIG. 1E). When the amount of AlO formed is large, another method such as He / H ₂ or NH ₃ plasma may be used.

  Seventh, doping (GCIB doping) with Si and N gas clusters and ion beams is continuously performed in the same apparatus in which the hydrogen plasma treatment is performed. Monosilane and nitrogen are clustered by adiabatic expansion and ionized by an ionizer, then accelerated by an accelerating tube and collided with the wafer substrate surface at room temperature.

Thus, a CuAlSiN transition layer 7 is formed on the upper surface of the copper wiring 5 by about 20 nm (FIG. 1F).
Compared to the conventional example, the CuAlSiN transition layer 7 is formed thicker by extending the processing time. Since the CuAlSiN transition layer 7 has a function of suppressing the surface diffusion of the copper wiring 5, the EM life of the copper wiring 5 can be improved. On the other hand, since the barrier metal film such as tantalum has a specific gravity nearly twice that of copper, the TaSiN transition layer 11 is formed in the barrier metal film 3 on the interlayer insulating film 1 between the copper wirings 5 by about 10 nm. . Here, the TaSiN transition layer 11 is formed by changing at least a part of the barrier metal film 3 (FIG. 1F).

Eighth, the TaSiN transition layer 11 on the interlayer insulating film 1 between the copper wirings 5 is removed by CMP (FIG. 1G).
At this time, the CuAlSiN transition layer 7 on the copper wiring 5 is also slightly removed by the CMP process. However, since it is formed thicker before the CMP process than before, a CuAlSiN film of about 10 nm is formed after the CMP process. be able to.

  Ninth, a liner film 10 is formed to a thickness of about 40 nm (FIG. 1H). Here, the liner film 10 is for preventing copper from diffusing into the interlayer insulating film 1 which is a low dielectric constant film formed in the upper layer on the liner film 10 and is compared with the interlayer insulating film 1 and the like. A silicon nitride film, a silicon carbide film, or the like having a relatively high relative dielectric constant is used.

With the above manufacturing method, the semiconductor device of the present embodiment is configured and manufactured.
Next, in the semiconductor device and the manufacturing method of the present embodiment, the CuAlSiN transition layer 7 is formed on the copper wiring 5, and the SiN transition layer is not formed on the interlayer insulating film 1 between the copper wirings 5. The reason will be explained.

  According to Patent Document 1 shown in FIG. 2A, it is known that reliability such as adhesion is improved by forming a Cu silicide layer (not including N) on the copper wiring 5. . However, since the Cu silicide layer is formed by thermal diffusion rather than by the GCIB doping method, the Cu silicide layer formed on the copper wiring 5 is a transition layer having a concentration gradient that is formed by GCIB doping. Instead, it was a silicide layer (CuSix) having a uniform concentration (A1 in FIG. 2A). Further, the interlayer dielectric film 1 between the copper wirings 5 was a low dielectric constant film, and no SiN transition layer was formed (A2 in FIG. 2A).

  Therefore, as a result of various investigations on improving the reliability of the copper wiring 5 by GCIB doping, the GCIB doping has an EM improving effect, but as a side effect, the capacitance (capacitance) between the copper wirings 5 increases. It turns out that a point occurs.

  In the semiconductor device shown in FIG. 2B, when the CuSiN transition layer 27 is formed on the surface of the copper wiring 5 after the removal of the barrier metal film formed on the interlayer insulating film between the copper wirings, Si is formed on the entire substrate surface. Since the GCIB doping of N is performed, the interlayer insulating film 1 between the copper wirings 5 is also doped with Si or N. In the interlayer insulating film 1 between the copper wirings 5 as well as the copper wiring 5, the collision energy is higher on the substrate surface, so that more SiN is formed, and the amount of SiN formed is smaller in the substrate (FIG. 2B). B2). This is referred to as a SiN transition layer 9. However, the SiN transition layer 9 generally has a relative dielectric constant of about 6.0 to 8.0 although it depends on the composition ratio of Si and N, and is an interlayer insulating film that is a low dielectric constant film. The relative dielectric constant of 1 (˜3.0) is very large.

FIG. 3 shows the result of trial calculation of keff of the interlayer insulating film 1 between the conventional example and the copper wiring 5 of the present embodiment.
In the conventional example shown in FIG. 3A, keff 3.8 is increased by about 27%, and it is considered that when the GCIB doping process is executed, the capacitance (capacitance) between the copper wirings 5 is increased. . For this reason, as shown in FIG. 3B, in this embodiment, even if the CuAlSiN transition layer 7 is formed on the copper wiring 5, the SiN transition layer is formed on the surface of the interlayer insulating film 1 between the copper wirings 5. Was prevented from forming.

  In this embodiment, when the CuAlSiN transition layer 7 is formed on the upper surface of the copper wiring 5, the interlayer insulating film 1 between the copper wirings 5 is protected by a barrier metal film 3 such as tantalum nitride or tantalum. (FIG. 1 (e) to FIG. 1 (f)). Since the barrier metal film such as tantalum has a specific gravity nearly twice that of copper, even if GCIB doping is performed on the entire surface of the substrate, the barrier metal film can stop doping of Si and N, and the lower interlayer Intrusion to the insulating film 1 can be prevented. Even if the CuAlSiN transition layer 7 is formed to have a thickness of 20 nm (FIG. 1F), if the barrier metal film 3 has a thickness of 10 nm, entry into the interlayer insulating film 1 can be prevented.

  Next, by performing the CMP process on the barrier metal film 3, Si and N can be completely removed from the interlayer insulating film 1 between the copper wirings 5 (FIG. 1 (g)). As shown in FIG. 2, the TaSiN transition layer 11 that causes an increase in capacitance between the copper wirings 5 does not remain (C2 in FIG. 2C). For this reason, an increase in wiring capacitance can be prevented (FIG. 3).

  Further, when the barrier metal film 3 is subjected to the CMP process, the CuAlSiN transition layer 7 on the wiring surface is also scraped to reduce the film thickness. However, by increasing the initial film thickness to 20 nm, the film finally becomes 10 nm. It has been confirmed that a thick CuAlSiN transition layer 7 can be formed and has an effect of improving reliability such as improvement of EM life.

  In the above-described embodiment, an example in which the seed film 4 contains Al has been described. However, even if a metal having a lower resistivity than Si, such as Ag, Ti, Co, or Ni, is contained. good.

In this embodiment, a low dielectric constant film having k of 3.0 is used as the interlayer insulating film 1. However, the same effect can be obtained with other low dielectric constant films having a k value.
Further, in the present embodiment, the case where the interlayer insulating film 1 in which the copper wiring 5 is formed is configured by only one layer has been described as an example, but a multilayer in which two or more interlayer insulating films 1 are stacked is described. It is also possible to apply to other wiring layers such as wiring.

  INDUSTRIAL APPLICABILITY The semiconductor device and the manufacturing method thereof according to the present invention can further improve the reliability of the wiring without increasing the capacitance between the wirings, and are useful for the semiconductor device and the manufacturing method thereof. Is useful for realizing a copper wiring having high electromigration resistance and low resistance.

Flowchart showing a process in a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention Explanatory drawing of Si and N concentration distribution in the semiconductor substrate in the semiconductor device of the embodiment Comparison explanatory drawing with the conventional example of keff trial calculation in the semiconductor device of the same embodiment, and its manufacturing method A flowchart showing a process in a conventional semiconductor device and a manufacturing method thereof.

Explanation of symbols

1 Interlayer insulation film (low dielectric constant film)
2 wiring trench 3 barrier metal film 4 seed film 5 copper wiring 6 copper oxide 7 CuAlSiN transition layer 8 surface of interlayer insulating film 9 SiN transition layer 10 liner film 11 TaSiN transition layer

Claims (10)

A wiring made of a conductive film is formed in the upper part of the interlayer insulating film formed on the substrate,
The upper surface of the wiring has a transition layer of the conductive film and SiN,
The semiconductor device, wherein the transition layer includes an alloy metal different from the conductive film. The semiconductor device according to claim 1, wherein the conductive film is made of copper. The semiconductor device according to claim 1, wherein the alloy metal includes a metal having a resistivity lower than that of Si. 4. The semiconductor device according to claim 3, wherein the alloy metal includes one of Al, Ag, Ti, Co, and Ni. A step (a) of forming a wiring trench in the upper part of the interlayer insulating film formed on the substrate;
After the step (a), a step (b) of forming a barrier metal film in the wiring trench and on the interlayer insulating film;
A step (c) of forming a wiring by embedding a conductive film in the wiring trench after the step (b);
A step (d) of injecting Si and N into the interlayer insulating film and the wiring after the step (c);
A method of manufacturing a semiconductor device, comprising: a step (e) of removing the barrier metal film on the interlayer insulating film after the step (d). The step (d)
6. The method of manufacturing a semiconductor device according to claim 5, wherein the Si and N implantation processes are performed by a gas cluster ion beam method. The step (c)
A step of embedding the conductive film by forming a seed film in the wiring trench;
The method of manufacturing a semiconductor device according to claim 5, wherein the seed film contains a metal having a lower resistivity than the Si. The semiconductor device according to claim 7, wherein the seed film contains any one of Al, Ag, Ti, Co, and Ni as a metal having a lower resistivity than that of the Si. Method. 9. The semiconductor according to claim 5, wherein a transition layer of the conductive film and SiN is formed on the upper surface of the wiring between the step (d) and the step (e). Device manufacturing method. The method for manufacturing a semiconductor device according to claim 5, wherein copper is used as the conductive film.

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