JP2009188101A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent damage to a surface of a low dielectric constant film exposed after a CMP process of a trench constituting a copper multilayer wiring having a damascene structure and to ensure wiring reliability and to provide a series resistance of a semiconductor device and a manufacturing method thereof. Suppress the increase.
At least a top surface of a first metal film embedded in a recess provided in a porous insulating film is covered with a second metal film containing Zr and B to a height matching the top surface of the porous insulating film. .
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular, avoids damage to a porous silica-based coating film when forming a single damascene or dual damascene type buried via and / or buried wiring layer. In addition, the present invention relates to a configuration for ensuring wiring reliability.

Conventionally, aluminum has been widely used as an electrode material and wiring material for semiconductor devices. However, in response to recent demands for miniaturization of semiconductor devices and higher processing speeds, the formation of electrodes and wiring should be handled with aluminum. Is getting harder.
Therefore, an attempt is being made to use copper, which is resistant to electromigration and has a specific resistance smaller than that of aluminum, as a next-generation material for aluminum.

  When copper is used as the electrode material or wiring material, copper is a material that is difficult to selectively etch, so the electrodes and wiring are formed as embedded electrodes or embedded wiring by the damascene method. By increasing the aspect ratio of the electrodes and wirings to be formed, it becomes possible to realize miniaturization and higher speed of the semiconductor device.

  On the other hand, in order to increase the speed of semiconductor devices, it is necessary to reduce the dielectric constant of the interlayer insulating film in order to reduce the parasitic capacitance as well as the resistance of the wiring and electrodes. Attempts have been made to employ low dielectric constant organic insulating materials such as ether (for example, Dow Chemical Company registered trademark SiLK) and porous silica (for example, see Patent Document 1).

When forming a multilayer wiring structure by the damascene method, a wiring groove is formed in the insulating film, a conductive barrier film and a copper main conductor film are formed on the insulating film including the bottom and side surfaces of the wiring groove, Unnecessary portions are removed by CMP to form embedded Cu wiring.
By repeating such steps, a multilayer wiring structure is formed.

With the recent miniaturization of wiring, so-called low-k materials having a low k value are applied as interlayer insulating films in order to avoid signal delay.
Low-k materials generally have k holes to reduce the k value, but because of the holes, the bulk strength is low and the resistance to plasma is weak.

  Therefore, in such a damascene process, an interlayer insulating film made of a porous low-k film as the next layer is deposited with the top surface of the embedded Cu wiring exposed, so that Cu diffusion is prevented. For this purpose, first, after forming a high-density barrier insulating film having a k value of 3 or more, a low dielectric constant film is formed.

However, when a high-density barrier insulating film is formed on the porous Low-k film, the surface of the porous Low-k film is damaged or densified by the plasma during film formation, and the k value increases.
In addition, the number of steps is increased by forming the barrier insulating film, and the dielectric constant of the barrier insulating film hinders the reduction of the dielectric constant. Therefore, the buried low-k film is buried using the inherent low k value. There is a problem that the merit of forming the embedded Cu multilayer wiring cannot be exhibited.

In recent years, since it has been required to lower the k value of the entire wiring, so-called k _eff , when forming embedded Cu wiring, a structure in which a porous Low-k material having pores is exposed to the surface after Cu polishing is formed. It has come to take.

Therefore, in order to prevent Cu from diffusing from the top surface of the embedded Cu wiring, it has been proposed to cover the top surface of the embedded Cu wiring with a metal cap layer made of dangsten or the like having a barrier property (for example, Patent Document 2 or Patent Document 3).
For example, in Patent Document 2, after planarizing an embedded Cu wiring by a CMP method, a part of the embedded Cu wiring is recessed, and a metal cap layer is formed in the recessed portion.
In this case, since the surface of the interlayer insulating film made of the low dielectric constant film is exposed to the etching atmosphere in the recessed process of the embedded Cu wiring, there is a problem that the low dielectric constant film is damaged.

In the case of Patent Document 3, a recess portion is formed by overpolishing by a CMP method under the condition that a barrier metal layer remains on the surface of an interlayer insulating film made of a low dielectric constant film, and a metal cap is formed on the recess portion. Forming a layer.
In this case, since the surface of the low dielectric constant film is covered with the barrier metal layer in the recessing process, the low dielectric constant film is not damaged.

On the other hand, it has also been proposed to use ZrB ₂ as a barrier metal layer instead of conventional Ta, TaN, TiN, etc. For example, Zr (BH ₄ ) ₄ gas is used on the surface of the insulating film in which the trench is formed. After Zr (BH ₄ ) ₄ is adsorbed, excited H ₂ gas and / or NH ₃ gas is introduced and reacted with the adsorbed Zr (BH ₄ ) ₄ to form a ZrB ₂ film or a ZrBN film. It is formed by a low temperature process (see, for example, Patent Document 4).
JP 2004-071705 A JP 2007-042662 A JP 2007-035734 A JP 2006-057162 A

  However, in the above-mentioned Patent Document 3, since the recess is formed by excessive polishing, high accuracy is required for time management, and there is a possibility that a difference in density between patterns may occur, resulting in poor controllability. There is a problem.

  Further, in the case of the conventional method of providing a metal cap layer, the specific resistance of the barrier metal used for the metal cap is large. Therefore, when the metal cap layer is thickened to increase the diffusion resistance, the portion connected to the via of the next layer There is a problem that the series resistance increases, which hinders speeding up.

  Accordingly, an object of the present invention is to prevent damage to the surface of a low dielectric constant film exposed after CMP of a trench in a copper multilayer wiring having a damascene structure, thereby ensuring wiring reliability and suppressing an increase in series resistance. And

  According to one aspect of the present invention, the second metal layer containing Zr and B to a height matching at least the top surface of the first metal film embedded in the recess provided in the porous insulating film with the top surface of the porous insulating film. A semiconductor device covered with a metal film is provided.

  From another viewpoint of the present invention, a step of forming a transistor on a semiconductor substrate, a step of forming a porous insulating film above the semiconductor substrate, a step of forming a recess in the porous insulating film, A step of forming a barrier film on the upper surface of the porous insulating film and the inner wall of the concave portion, a step of filling the concave portion with a first metal film, and the first metal film being lower than the height of the upper surface of the porous insulating film. A recessing step, a step of forming a second metal film containing Zr and B on the surface of the recessed part and the barrier film, and leaving the second metal film on the upper part in the recess. There is provided a method of manufacturing a semiconductor device including a planarization step.

In the present invention, since the surface of the Cu buried layer is covered with a metal cap layer, Cu diffuses into the porous insulating film even if the porous insulating layer is directly formed on the porous insulating film without using a barrier insulating film. There is nothing to do.
Further, by using a metal containing Zr and B as the metal cap layer, both low resistance and Cu barrier resistance can be achieved.

Here, with reference to FIG.1 and FIG.2, embodiment of this invention is described.
As shown in FIG. 1A, first, an interlayer insulating film 14 made of a porous Low-k film is provided on an underlying insulating film 11 on which a plug 12 is formed via an etching stopper film 13.
In this case, the interlayer insulating film 14 is coated with MSQ (methyl silsesquioxane), porous HSQ (hydrogen silsesquioxane), porous MHSQ (methylated hydrogen silsesquioxane), or the like, and has a k value. Is composed of a porous Low-k film of 2.4 or less.
The porous Low-k film is not limited to the coating type, and may be a CVD growth film.

Next, as shown in FIG. 1B, after the wiring trench 15 is formed, the barrier metal film 16 is deposited, and then the Cu film 17 is completely formed by electrolytic plating through the Cu seed layer. Deposit to fill.
The thickness of the barrier metal film 16 is about 1 to 20 nm.
As the barrier metal film 16, CoWP, CoWB, WN, CoW, Ta, TaN, TiN, NiW, or ZrB ₂ or ZrBN is used.
Next, as shown in FIG. 1C, planarization is performed using a CMP method, and the Cu film 17 is embedded in the wiring trench 15.

Next, as shown in FIG. 1D, with the barrier metal film 16 remaining, the Cu film 17 is selectively etched back by wet etching to form a recess 18.
At this time, the depth of the recess 18, that is, the recess depth is preferably about 0.05 to 30% of the depth of the wiring trench 15.

In addition, with respect to the controllability of the recess, wet etching of the recess under conditions controlled by a mixed solution of hydrogen peroxide and hydrochloric acid or hydrofluoric acid overwater, etc., compared with the case where the recess is formed by excessive polishing by CMP. A recess can be formed with good in-plane uniformity.
Further, since the surface of the interlayer insulating film 14 is covered with the barrier metal film 16 in the etching process, the surface of the interlayer insulating film 14 is not damaged.

Next, as shown in FIG. 2E, a conductive film 19 containing Zr and B is deposited so as to completely fill the recess 18.
The conductive film 19 is typically a ZrB ₂ film, but a ZrB _x or ZrBN film having a composition shifted from the stoichiometric ratio may be used.

The present inventor has found that ZrB ₂ (zirconium diboride) is a material having low resistance and excellent Cu cap barrier properties.
For example, the specific resistance of bulk TaN is 135 μΩcm, while the specific resistance of ZrB ₂ is 10 μΩcm.
ZrB ₂ is formed by various methods as described in Patent Document 4 described above, and is formed using a CVD method, a PVD method, a sputtering method, or the like.

Next, as shown in FIG. 2F, the conductive film 19 buried in the recess 18 is polished and planarized again by the CMP method so as to have a thickness of 5 to 15 nm to obtain a barrier cap film 20.
At this time, the surface of the interlayer insulating film 14 is exposed.

Next, as shown in FIG. 2G, a second interlayer insulating film 21 made of a porous Low-k film is grown on the entire surface.
At this time, since the barrier cap film 20 is provided on the surface of the Cu film 17, the diffusion of Cu into the second interlayer insulating film 21 is suppressed.
In this case, the second interlayer insulating film 21 is also coated with MSQ (methyl silsesquioxane), porous HSQ (hydrogen silsesquioxane), porous MHSQ (methylated hydrogen silsesquioxane), or the like. , A porous low-k film having a k value of 2.4 or less.

  Since such MSQ is a coating type SOG film, the plasma damage caused by the film formation of the barrier insulating film of plasma SiC or SiCN which has been conventionally formed in order to prevent the leakage of the Cu surface is prevented. The lower interlayer insulating film 14 made of is not received.

It is also possible to select a CVD method film as the porous film constituting the interlayer insulating film 14 and the second interlayer insulating film 21.
Also in this case, since the same porous film as the underlying interlayer insulating film 14 is formed when the second interlayer insulating film 21 is formed, no damage is caused on the interlayer insulating film 14.

Thereafter, in the case of the single damascene method, a plug whose surface is capped with the conductive film 19 made of Zr and B is formed on the second interlayer insulating film through the above-described steps.
Alternatively, in the case of the dual damascene method, a middle stopper film and a third interlayer insulating film are sequentially deposited on the second interlayer insulating film, a via hole is formed in the second interlayer insulating film, and the third interlayer insulating film is formed. A wiring trench is formed in the interlayer insulating film, and a Cu embedded wiring and a plug whose surfaces are capped with a conductive film 19 made of Zr and B are simultaneously formed.

At this time, the plug is connected to the Cu film 17 through the barrier cap film 20, but in the present invention, since the barrier cap film 20 is made of a conductive material made of Zr and B, the series resistance is undesirable. There is no increase.
If the via diameter is further reduced as the wiring is further miniaturized, the resistance of the ZrB ₂ cap is affected even if the resistance is low. Therefore, the barrier metal film formation in the via in the second wiring is affected. At this time, the ZrB ₂ cap may be removed to directly connect the Cu film 17 of the lower wiring to the plug.
The ZrB ₂ cap at the bottom of the via can be easily removed by Ar sputtering or the like.

  Furthermore, after forming a barrier metal film on the upper layer wiring, a Cu seed necessary for depositing Cu by plating is formed. At this time, the barrier metal may be formed in a state where the barrier metal exists at the bottom of the via, In order to reduce the via connection resistance, the Cu seed may be formed after removing the barrier metal at the bottom of the via before forming the Cu seed.

  Further, when the conductive film 19 is formed in the recess 18, if the trench side wall has an inversely tapered shape, a gap may be generated between the side wall and the conductive film 19. Is preferably a forward tapered shape.

That is, when the conductive film 19 deposited on unnecessary portions such as on the insulating film is removed by CMP, a second recess may be formed in the barrier cap film 20 above the trench.
In this case, the porous Low-k film constituting the second interlayer insulating film 21 is formed on the second recess. However, when the porous Low-k film is a coating type, the trench side wall is reversely tapered. However, the coating liquid is filled in the second recess due to the influence of the surface tension and the like, and the upper Cu wiring can be formed in the second recess without any gap.

However, when the porous low-k film is a CVD film, if the trench sidewall of the second recess portion has an inversely tapered shape, conformal film formation cannot be performed. When forming the Low-k film, a gap is generated in the reverse tapered portion.
Therefore, since the wiring is formed in a state where there is a gap above the lower wiring, the reliability is lowered due to the occurrence of leakage between the wirings. Therefore, it is desirable that the upper side wall of the trench has a tapered shape. .

Based on the above, next, the manufacturing process of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIG.
FIG. 3 is a schematic cross-sectional view of a semiconductor device manufactured by the method according to Example 1 of the present invention. First, for example, element isolation by shallow trench isolation (STI) is performed on the surface of a silicon substrate 31 having a diameter of 300 mm. An insulating film 32 is formed, and a MOSFET 33 is formed in the active region surrounded by the element isolation insulating film 32.

  The MOSFET 33 includes a gate insulating film 34, a gate electrode 35, a source region 36, and a drain region 37, and sidewalls 38 are provided on both sides of the gate electrode 35. An extension region is formed near the gate electrode.

  Next, after depositing an interlayer insulating film 39 having a thickness of, for example, 1.5 μm on the entire surface, the two that penetrate the interlayer insulating film 39 and reach the source region 36 and the drain region 37 are formed. Via holes are formed, and the via holes are filled with conductive plugs 40 and 41 made of tungsten (W) by CMP.

Next, for example, an etching stopper film having a thickness of, for example, 30 nm made of a silicon oxycarbide film having a relative dielectric constant of 3.6 on the interlayer insulating film 39 is formed by CVD using tetramethylsilane and carbon dioxide as source gases. 42 is formed.
The film formation conditions at this time are, for example,
Tetramethylsilane flow rate: 500 sccm
Carbon dioxide gas flow rate: 150sccm
Pressure: about 600 Pa (4.5 Torr)
13.56 MHz RF power: 600 W
400 kHz RF power: 10 W
Substrate temperature: 400 ° C
And
In addition, the area of the parallel plate electrode for supplying RF power is substantially equal to the area of the silicon substrate 31.

  Next, on the etching stopper film 42, a liquid silica-based composition containing water, for example, NCS (trade name, manufactured by Catalyst Kasei Kogyo Co., Ltd.) is applied by a coating method. As a result, the trench formation layer 43 made of porous silica whose main component is MSQ and whose k value is 2.4 or less is formed.

Next, after forming a plurality of wiring trenches in the trench formation layer 43 and the etching stopper film 42, the barrier metal layer 44 is filled with, for example, a 15 nm thick barrier metal layer 44 and a Cu film. The Cu wirings 45 and 46 are formed by polishing to the extent that remains.
The Cu film is composed of an electroless Cu plating film and an electrolytic Cu plating film.

Next, in order to selectively etch the surface side of the Cu wirings 45 and 46 embedded in the wiring trench, a recess of 30 nm is formed in the trench by immersing in a mixed solution of diluted hydrogen peroxide and diluted hydrochloric acid for a certain period of time. To do.
At this time, since the trench forming layer 43 made of porous silica is covered with the barrier metal layer 44, it is not etched.

Next, after forming a ZrB ₂ film so as to completely embed the recess portion, it is polished again by the CMP method and left as a barrier cap layer 47 so as to have a thickness of 5 to 15 nm of the ZrB ₂ film.
At this time, the barrier metal layer 44 formed on the upper surface of the trench formation layer 43 is removed, and the surface of the trench formation layer 43 is exposed.
When the thickness of the barrier cap layer 44 is less than 5 nm, film defects such as pinholes become a problem, and when it exceeds 15 nm, an increase in series resistance becomes a problem.

As conditions for forming the ZrB ₂ film, for example, the substrate temperature is set to 150 ° C., the atmosphere is set to 3 × 10 ⁻¹ Torr, and the source gas Zr (BH ₄ ) ₄ gas is introduced to form the barrier metal layer 44 and It is adsorbed on the exposed surfaces of the Cu wirings 45 and 46.

Next, the substrate temperature is set to 450 ° C., the atmosphere is set to 2 × 10 ⁻⁵ Torr, and the excited H radical is introduced to react with Zr (BH ₄ ) ₄ adsorbed on the surface, thereby forming the ZrB ₂ film. Form.
By repeating this adsorption and reaction process a predetermined number of times, a ZrB ₂ film having a desired film thickness is formed.

In the polishing step, a polishing slurry containing abrasive grains having high mechanical polishing performance was used so that the barrier metal composed of ZrB ₂ and Ta could be polished with the same slurry.
For example, alumina, colloidal silica, cerium, fumed silica or the like can be selected as the abrasive grains. Here, polishing was performed using a slurry to which alumina abrasive grains were added.
Polishing was performed using an endpoint detector, and polishing was further performed for about 20 nm from the time when the polishing reached the interface between the barrier metal and the trench formation layer 43 for a time for cutting the trench formation layer.

Next, a liquid silica-based composition containing water, for example, NCS (trade name, manufactured by Catalyst Chemical Industry Co., Ltd.) is applied to the entire surface including the surface of the trench formation layer 43 by an application method. By performing a minute cure, a via forming layer 48 having a thickness of, for example, 150 nm made of porous silica whose main component is MSQ and whose k value is 2.4 or less is formed.
At this time, since the surfaces of the Cu wirings 45 and 46 are covered with the barrier cap layer 47, Cu does not diffuse into the via formation layer 48.
In addition, since the via formation layer 48 and the trench formation layer 43 are made of the same material, adhesion is improved.

Next, a middle stopper film 49 having a thickness of, for example, 30 nm made of silicon oxycarbide having a relative dielectric constant of 3.6 is formed on the via formation layer 48, and then NH ₃ plasma treatment is performed to improve adhesion. Next, the trench formation layer 50 having a thickness of, for example, 150 nm made of porous silica containing the same MSQ as a main component is formed.

Next, a wiring trench is formed in the trench formation layer 50, and via holes are formed in the middle stopper film 49 and the via formation layer 48, and then a barrier metal layer 51 having a thickness of, for example, 15 nm and Cu are formed. After embedding with a film, the Cu wiring 52 and the via plug 53 are simultaneously formed by polishing to about the barrier metal layer 51.
The Cu film is composed of an electroless Cu plating film and an electrolytic Cu plating film.

Next, again, in order to selectively etch the surface side of the Cu wiring 52 embedded in the wiring trench, a recess of 30 nm is formed in the trench by immersing in a mixed solution of diluted hydrogen peroxide and diluted hydrochloric acid for a certain period of time. To do.
Also at this time, since the trench forming layer 50 made of porous silica is covered with the barrier metal layer 51, it is not etched.

Next, after forming a ZrB ₂ film again so as to completely embed the recess portion, it is polished again by the CMP method and left to have a thickness of 5 to 15 nm of the ZrB ₂ film. To do.
Also here, a polishing slurry containing abrasive grains having high mechanical polishing performance was used so that the barrier metal composed of ZrB ₂ and Ta could be polished with the same slurry.

Next, after the dual damascene process is repeated according to the number of multilayer wiring structures required, a thickness of silicon oxycarbide having a relative dielectric constant of 3.6 is formed on the wiring layer including the uppermost embedded wiring 55. However, for example, after forming an etching stopper film 56 of 30 nm, NH ₃ plasma treatment is performed, and then an interlayer insulating film 57 to be a via formation layer made of porous silica mainly composed of the same MSQ is formed. .

  Next, a via hole that penetrates the interlayer insulating film 57 and the etching stopper film 56 and reaches the buried wiring 55 in the lower layer is formed, and a conductive plug 58 made of tungsten is filled therein.

  Next, after a pad 59 made of aluminum connected to the conductive plug 58 is formed on the interlayer insulating film 57, the pad 59 and the interlayer insulating film 57 are covered with a protective film 60 made of SiN. By forming an opening that exposes the surface of the pad 59 in the film 60, the basic configuration of the semiconductor device according to the first embodiment of the present invention is completed.

In Example 1 of the present invention, the barrier cap layer is excellent in Cu diffusion resistance, and low resistance ZrB ₂ is used. Therefore, an increase in series resistance with the via can be suppressed.
In addition, since the recessing process is a wet etching process with the barrier metal layer left, the wafer surface can be uniformly processed compared to the excessive polishing by CMP, and the trench forming layer made of porous silica is etched. There is no damage.

  Further, when forming the via formation layer on the trench formation layer, since the Cu wiring is covered with the barrier cap layer, there is no need to form a barrier insulation film that also serves as an etching stopper. The film is not damaged by the plasma deposition, and the adhesion between the trench formation layer and the via formation layer is improved.

Next, referring to FIG. 4, a semiconductor device according to a second embodiment of the present invention will be described. In the second embodiment, the barrier metal is also formed of ZrB ₂ , and the basic manufacturing process is the same as the above-described embodiment. Since 1 is exactly the same, only the structure will be described.
FIG. 4 is a schematic cross-sectional view of the semiconductor device according to the second embodiment of the present invention. The barrier metal layer 61 covers the Cu wires 45 and 46, the via plug 53, the Cu wire 52, and the embedded wire 55. , 62, and 63 use ZrB ₂ films.
The process for forming the ZrB ₂ film to be the barrier metal layers 61 to 63 is also exactly the same as the process for forming the ZrB ₂ film constituting the barrier cap layer 54.

In Example 2 of the present invention, the resistance to Cu diffusion is excellent as a barrier metal, and low resistance ZrB ₂ is used. Therefore, the series resistance can be further reduced, and Zr (BH ₄ ) Just make ₄ gas easier.

The embodiment and each example of the present invention have been described above, but the present invention is not limited to the configurations and conditions described in the embodiment and each example, and various modifications are possible. For example, a silicon oxycarbide film having a non-dielectric constant of 3.6 is used as an etching stopper film and a middle stopper film. However, the film is not limited to such a non-dielectric constant. The relative flow rate of the gas may be changed as appropriate so that the relative dielectric constant may be 3.6 to 4.6, and any silicon oxycarbide containing 10 to 90% by weight of the Si—CH ₂ —Si structure may be used.

In each of the above examples, NCS (trade name, manufactured by Catalytic Chemical Industry Co., Ltd.) is used as a liquid silica-based composition for forming a porous SiO ₂ film. The product is not limited to the product name), and any porous silica having a relative dielectric constant of 2.7 or less can be obtained. For example, other MQS (methyl silsesquioxane), HSQ (hydrogen silsesquioxane). Sun) or MHSQ (methylated hydrogen silsesquioxane), and a composition comprising a mixture of MQS and HSQ may also be used.

  In each of the above embodiments, the via and the embedded wiring are formed of Cu. However, the present invention is not limited to Cu, and is not limited to Cu, but also alloys such as Cu-Al and Cu-Si. Further, it is applied to metals other than Cu such as Al and Ag, or metal nitrides such as TiN and TaN.

  In the above embodiment, the middle stopper film is used in the dual damascene process. However, the middle stopper film is not essential, and a trench and a via may be formed in a single porous silica film.

The following additional notes are disclosed with respect to the embodiments of the present invention including the first and second embodiments.
(Supplementary Note 1) At least the top surface of the first metal film embedded in the recess provided in the porous insulating film is covered with a second metal film containing Zr and B to a height matching the top surface of the porous insulating film. Semiconductor device.
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the second metal film covers both side surfaces and a bottom surface of the first metal film.
(Supplementary note 3) The semiconductor device according to supplementary note 1 or supplementary note 2, wherein the first metal film is made of Cu.
(Supplementary Note 4) The second metal film, a semiconductor device according to any one of Supplementary Notes 1 to Supplementary Note 4 made of ZrB _2.
(Supplementary Note 5) The first metal film is provided at a plurality of locations in the stacking direction to form a multilayer wiring structure, and the porous insulating films embedded in the first metal films are in direct contact with each other in the stacking direction. The semiconductor device according to any one of appendices 1 to 4.
(Appendix 6) A step of forming a transistor on a semiconductor substrate;
Forming a porous insulating film above the semiconductor substrate;
Forming a recess in the porous insulating film;
Forming a barrier film on the upper surface of the porous insulating film and the inner wall of the recess;
Filling the recess with a first metal film;
Recessing the first metal film to be lower than the height of the upper surface of the porous insulating film;
Forming a second metal film containing Zr and B on the recessed portion and the surface of the barrier film;
Flattening to leave the second metal film in the upper part of the recess;
A method of manufacturing a semiconductor device including:
(Additional remark 7) Furthermore, it has the process of forming directly the porous insulating film which comprises the next layer after the said flattening process, The manufacturing method of the semiconductor device of Additional remark 6 characterized by the above-mentioned.
(Additional remark 8) The said barrier film is a manufacturing method of the semiconductor device as described in additional remark 6 or 7 which consists of a said 2nd metal film.
(Supplementary note 9) The method for manufacturing a semiconductor device according to any one of supplementary notes 6 to 8, wherein the first metal film is made of Cu.
(Supplementary Note 10) The method for manufacturing a semiconductor device according to any one of supplementary notes 6 to 9, wherein the second metal film is made of ZrB ₂ .
(Additional remark 11) The manufacturing method of the semiconductor device of any one of Additional remark 6 thru | or 10 whose said planarization process is a chemical mechanical polishing process, and the slurry used at the said chemical mechanical polishing process is an abrasive slurry.
(Additional remark 12) The manufacturing method of the semiconductor device of any one of Additional remark 6 thru | or 11 in which the said abrasive grain type slurry contains either colloidal silica or an alumina.
(Additional remark 13) The said porous insulating film is a manufacturing method of the semiconductor device of any one of Additional remark 6 thru | or 12 formed by apply | coating methyl silsesquioxane.

It is explanatory drawing of the manufacturing process to the middle of embodiment of this invention. It is explanatory drawing of the manufacturing process after FIG. 1 of embodiment of this invention. It is a schematic sectional drawing of the semiconductor device produced by the method by Example 1 of this invention. It is a schematic sectional drawing of the semiconductor device of Example 2 of this invention.

Explanation of symbols

11 Base insulating film 12 Plug 13 Etching stopper film 14 Interlayer insulating film 15 Trench for wiring 16 Barrier metal film 17 Cu film 18 Recess 19 Conductive film 20 Barrier cap film 21 Second interlayer insulating film 31 Silicon substrate 32 Element isolation insulating film 33 MOSFET
34 Gate insulating film 35 Gate electrode 36 Source region 37 Drain region 38 Side wall 39 Interlayer insulating films 40 and 41 Conductive plug 42 Etching stopper film 43 Trench formation layer 44 Barrier metal layers 45 and 46 Cu wiring 47 Barrier cap layer 48 Via formation Layer 49 Middle stopper film 50 Trench formation layer 51 Barrier metal layer 52 Cu wiring 53 Via plug 54 Barrier cap layer 55 Embedded wiring 56 Etching stopper film 57 Interlayer insulating film 58 Conductive plug 59 Pad 60 Protective films 61 to 63 Barrier metal layer

Claims (6)

A semiconductor device in which at least a top surface of a first metal film embedded in a recess provided in a porous insulating film is covered with a second metal film containing Zr and B to a height matching the top surface of the porous insulating film. The semiconductor device according to claim 1, wherein the second metal film covers both side surfaces and a bottom surface of the first metal film. A multilayer wiring structure is provided by providing the first metal film at a plurality of locations in the stacking direction, and the porous insulating films filling the adjacent first metal films are in direct contact with each other in the stacking direction. Item 3. The semiconductor device according to Item 1 or 2. Forming a transistor on a semiconductor substrate;
Forming a porous insulating film above the semiconductor substrate;
Forming a recess in the porous insulating film;
Forming a barrier film on the upper surface of the porous insulating film and the inner wall of the recess;
Filling the recess with a first metal film;
Recessing the first metal film to be lower than the height of the upper surface of the porous insulating film;
Forming a second metal film containing Zr and B on the recessed portion and the upper surface of the barrier film;
Flattening to leave the second metal film in the upper part of the recess;
A method of manufacturing a semiconductor device including: 5. The method of manufacturing a semiconductor device according to claim 4, wherein a porous insulating film constituting a next layer is directly formed after the planarizing step. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the planarization step is a chemical mechanical polishing step, and the slurry used in the chemical mechanical polishing step is an abrasive slurry.

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