JP2009188041A - Transistor made of group III nitride semiconductor - Google Patents

Abstract

Provided is a punch-through transistor that realizes low resistance by maximizing the characteristics of a group III nitride semiconductor and has excellent productivity.
The nitride semiconductor device includes a substrate 1 and a nitride semiconductor multilayer structure 2 formed on one side of the substrate 1 to form a punch-through transistor. The nitride semiconductor multilayer structure portion 2 is formed by laminating an n ⁺ -type GaN drain layer 6, an n ⁻ -type GaN drift layer 7, a p-type GaN channel layer 4, and an n ⁺ -type GaN source layer 5. Yes. For example, the operating voltage is 400 V, the donor concentration of the n ⁻ -type GaN drift layer 7 is 2 × 10 ¹⁶ cm ⁻³ , the acceptor concentration of the p-type GaN channel layer 4 is 3 × 10 ¹⁷ cm ⁻³ , and the n ⁻ -type. The layer thickness of the GaN drift layer 7 is 1 μm.
[Selection] Figure 1

Description

The present invention relates to a transistor using a group III nitride semiconductor. The group III nitride semiconductor refers to a semiconductor represented by the general formula Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).

Conventionally, power devices using silicon semiconductors have been used for power amplifier circuits, power supply circuits, motor drive circuits, and the like.
However, due to the theoretical limits of silicon semiconductors, the increase in breakdown voltage, reduction in resistance, and increase in speed of silicon devices are reaching their limits, and it is becoming difficult to meet market demands.
Therefore, development of nitride semiconductor devices having characteristics such as high breakdown voltage, high temperature operation, large current density, high-speed switching, and low on-resistance has been studied.

In the case of manufacturing a transistor using a silicon semiconductor, it is necessary to increase the thickness of the drift layer in order to ensure a necessary breakdown voltage. For example, in order to design a high breakdown voltage transistor having a breakdown voltage of 400 V, the impurity concentration of the drift layer needs to be about 7.5 × 10 ¹⁴ cm ⁻³ and the thickness of the drift layer needs to be about 26 μm. However, in this case, the on-resistance contributed by the drift layer is extremely large.

On the other hand, when using a group III nitride semiconductor, the impurity concentration of the drift layer needs to be about 8.5 × 10 ¹⁶ cm ⁻³ and the thickness of the drift layer needs to be about 1.9 μm. In this case, the generally used on-resistance calculated from only the drift layer resistance is about 0.25 mΩ · cm ² . However, in the process of manufacturing the device structure, the time and cost required for crystal growth of the drift layer are large.
JP 2003-163354 A

By using a group III nitride semiconductor to form a punch-through transistor (a transistor in which a depletion layer extending to the drift layer contacts the n ⁺ layer on the drain side when off), the thickness of the drift layer is suppressed, and Thus, it is considered that an element having a high breakdown voltage and a low on-resistance can be realized.
However, no proposal has yet been made on the design of a drift layer that can bring out the characteristics of a group III nitride semiconductor.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a transistor having a low resistance and excellent productivity by making the most of the characteristics of a group III nitride semiconductor.

  In order to achieve the above object, an invention according to claim 1 is a transistor made of a group III nitride semiconductor, comprising a first layer (drain layer) made of an n-type group III nitride semiconductor, and the first layer. A second layer (called a drift layer) made of an n-type group III nitride semiconductor having an impurity concentration different from that of the first layer, and a p-type group III nitride semiconductor on the second layer Straddling the third layer (channel layer) made of, a fourth layer (source layer) made of an n-type group III nitride semiconductor on the third layer, and the second layer, the third layer, and the fourth layer. A gate insulating film formed on the wall surface, and a gate electrode disposed opposite to the third layer through the gate insulating film, and the first layer and the fourth layer are in an off state of the transistor. Due to the operating voltage applied between them, a depletion layer extending in the second layer is formed in the first layer. It is a transistor to reach.

  According to this configuration, a punch-through transistor having a vertical npn structure is configured using a group III nitride semiconductor. When the drain layer and the gate electrode are short-circuited or when an operating voltage with the source layer side being positive is applied between the drain layer and the source layer when the gate voltage is lower than the threshold voltage (referred to as an off state) A depletion layer spreads in the drift layer from the interface between the layer and the drift layer. At this time, the depletion layer is designed to reach the drain layer located on the drain electrode side.

  The breakdown voltage that can be applied to the transistor is mainly determined by the thickness of the drift layer. When off, a maximum electric field is generated between the drift layer and the channel layer in the depletion layer to be formed. When this electric field exceeds the limit electric field strength of the material, breakdown occurs, leading to destruction. In order to design with a higher withstand voltage, the impurity concentration of the drift layer is lowered and the drift layer thickness is increased as much as necessary. It is necessary to. However, if it does so, the resistance value which arises in a drift layer will become large.

According to the present invention, the impurity concentration of the drift layer is set to a value smaller than the required value. On the other hand, the thickness of the drift layer can be set to a thickness that can ensure a necessary breakdown voltage. By doing so, it is possible to provide a transistor capable of maintaining a necessary breakdown voltage with a thinner drift layer thickness.
The invention according to claim 2 is the transistor according to claim 1, wherein the thickness of the second layer is 1 μm or less, and the n-type impurity concentration of the second layer is 1 × 10 ¹⁷ cm ⁻³ or less. . In this configuration, it is assumed that a breakdown voltage of up to 400V is guaranteed. When the n-type impurity concentration is 2 × 10 ¹⁶ cm ⁻³ , a breakdown voltage of about 1400 V can be secured, but the depletion layer reaches 8 μm. When the drift layer (second layer) is made thick, the resistance becomes extremely high. Thus, by setting the thickness of the drift layer to 1 μm or less, the electrical resistance of the drift layer can be kept low, and a low on-resistance transistor with a thin device structure can be realized.

More specifically, as described in claim 3, by setting the n-type impurity concentration (donor concentration) of the second layer (drift layer) to 2 × 10 ¹⁶ cm ⁻³ or less, the drift layer A transistor with a withstand voltage of 350 V or more can be realized with a thickness of 1 μm or less.
Usually, when MOCVD (Metal Organic Chemical Vapor Deposition) is used, the growth of GaN takes time on the order of 1 μm / hour. Therefore, by reducing the thickness of the device structure, it is possible to reduce manufacturing time, reduce costs and save materials.

  The n-type impurity concentration is controlled, for example, by controlling the doping amount of Si. In the present invention, different withstand voltage designs can be made possible by fixing the Si doping concentration to a constant value and changing the film thickness (crystal growth time) of the drift layer (second layer). Therefore, it is excellent in productivity.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view for explaining the structure of a nitride semiconductor device that is a punch-through transistor according to an embodiment of the present invention.
This nitride semiconductor device includes a substrate 1 and a nitride semiconductor multilayer structure portion 2 formed on one main surface of the substrate 1, and constitutes a punch-through transistor having an operating voltage of 400V (withstand voltage of 400V), for example. Yes.

As the substrate 1, for example, a substrate made of a group III nitride semiconductor represented by Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) (for example, GaN Substrate, AlN substrate, etc.), SiC substrate, and conductive substrate such as Si substrate are preferably used. That is, the substrate 1 may be the same type of substrate as the nitride semiconductor multilayer structure portion 2 or a different type of substrate. Moreover, not only a conductive substrate but also an insulating substrate such as sapphire can be used.

The nitride semiconductor multilayer structure portion 2 is made of a group III nitride semiconductor, and is formed on the n-type layer 3, the p-type GaN channel layer 4 formed on the n-type layer 3, and the p-type GaN channel layer 4. And an n ⁺ -type GaN source layer 5.
The n-type layer 3 includes an n ⁺ -type GaN drain layer 6 formed on one surface (upper surface) of the substrate 1 and an n ⁻ -type GaN drift layer 7 stacked on the n ⁺ -type GaN drain layer 6. ing.

The n ⁺ -type GaN drain layer 6 has an n-type impurity concentration (donor concentration) higher than that of the n ⁻ -type GaN drift layer 7, and the concentration is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (for example, 3 × 10 ¹⁸ cm ⁻³ ). On the other hand, the n-type impurity concentration of the n ⁻ -type GaN drift layer 7 is 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ (for example, 1 × 10 ¹⁷ cm ⁻³ ). When the substrate 1 is a conductive substrate, the substrate 1 also functions as a part of the drain layer. The layer thickness of the n ⁺ -type GaN drain layer 6 is 0.1 μm to 0.5 μm (for example, 0.2 μm), and the layer thickness of the n ⁻ -type GaN drift layer 7 is 1.45 μm to 1.5 μm (for example, 1.45 μm).

The p-type GaN channel layer 4 has a p-type impurity concentration (acceptor concentration) of 1 × 10 ¹⁸ cm ⁻³ to 4 × 10 ¹⁹ cm ⁻³ (more specifically, 4 × 10 ¹⁹ cm ⁻³ ). is there. The layer thickness of the p-type GaN channel layer 4 is 0.8 μm to 1.0 μm (more specifically, 0.9 μm).
The n ⁺ -type GaN source layer 5 has an n-type impurity concentration of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (more specifically, 3 × 10 ¹⁸ cm ⁻³ ). . The layer thickness of the n ⁺ -type GaN source layer 5 is 0.2 μm to 1 μm (more specifically, 0.5 μm).

The nitride semiconductor multilayer structure portion 2 is formed in a strip shape extending in a direction perpendicular to the paper surface of FIG. 1, and the n ⁺ -type GaN source layer 5 to the n ⁺ -type GaN drain layer 6 have a substantially trapezoidal cross section. Etching is performed across the stack interface to the exposed depth. The n ⁺ -type GaN drain layer 6 is drawn out from both sides of the nitride semiconductor multilayer structure portion 2 in the lateral direction along the upper surface of the substrate 1 (hereinafter, this direction is referred to as “width direction”). 9. That is, the lead-out portion 9 is constituted by an extension of the n ⁺ -type GaN drain layer 6 in this embodiment.

On the other hand, near the middle in the width direction of the nitride semiconductor multilayer structure portion 2, there is a depth from the n ⁺ -type GaN source layer 5 to the middle portion of the n ⁻ -type GaN drift layer 7 through the p-type GaN channel layer 4. Trench 10 is formed along the longitudinal direction of nitride semiconductor multilayer structure 2. In this embodiment, the trench 10 is formed in a substantially V-shaped cross section, and the inclined side surface extends over the n ⁻ -type GaN drift layer 7, the p-type GaN channel layer 4 and the n ⁺ -type GaN source layer 5. The wall surface 11 is formed. The gate insulating film covers the entire surface of the wall surface 11 and further covers the surfaces of the n ⁺ -type GaN drain layer 6, the n ⁻ -type GaN drift layer 7, the p-type GaN channel layer 4 and the n ⁺ -type GaN source layer 5. 12 is formed.

The n ⁺ -type GaN drain layer 6, n ⁻ -type GaN drift layer 7, p-type GaN channel layer 4 and n ⁺ -type GaN source layer 5 are formed on the substrate 1 by, for example, MOCVD (Metal Organic Chemical Vapor Deposition: organic). It is epitaxially grown by metal vapor phase epitaxy.
For example, when a substrate 1 having a c-plane (0001) as the main surface is used, an n ⁺ -type GaN drain layer 6, an n ⁻ -type GaN drift layer 7, and a p-type GaN channel layer 4 grown on the substrate 1 by epitaxial growth. The n ⁺ -type GaN source layer 5 is also laminated with the c-plane (0001) as the main surface. Moreover, the plane orientation of the wall surface 11 of the nitride semiconductor multilayer structure portion 2 is, for example, a plane (a plane other than the c plane) inclined in a range of 15 ° to 90 ° with respect to the c plane (0001). More specifically, for example, non-polar surfaces (non-polar surfaces) such as m-plane (10-10) or a-plane (11-20), (10-13), (10-11), (11-22) ) And other semipolar surfaces (semipolar surfaces).

The gate insulating film 12 can be made of, for example, nitride or oxide. More specifically, the gate insulating film 12 can be composed of SiN (silicon nitride), SiO ₂ (silicon oxide), or a combination thereof. A gate electrode 13 is formed on the gate insulating film 12.
The gate electrode 13 faces the wall surface 11, that is, the n ⁻ -type GaN drift layer 7, the p-type GaN channel layer 4 and the n ⁺ -type GaN source layer 5 via the gate insulating film 12, and further, n ⁺ -type GaN. The upper surface of the source layer 5 is formed to extend to the vicinity of the edge of the trench 10. For example, the gate electrode 13 is made of Ni and Au laminated on the Ni / Au alloy, Pd / Au alloy, Pd / Ti / Au alloy and Pd / Pt / Au alloy, Pt, Al, poly It can be made of a conductive material such as silicon.

A region near the wall surface 11 in the p-type GaN channel layer 4 is a channel region 14 facing the gate electrode 13. In the channel region 14, an inversion layer (channel) that electrically conducts between the n-type layer 3 and the n ⁺ -type GaN layer 5 is formed by applying an appropriate bias to the gate electrode 13.
The gate insulating film 12 is formed with an opening 15 exposing the upper surface of the n ⁺ -type GaN source layer 5. A source electrode 16 is formed on the n ⁺ -type GaN source layer 5 exposed from the opening 15.

The source electrode 16 is in ohmic contact with the n ⁺ -type GaN source layer 5, and can be configured using, for example, a metal such as Ti and a Ti / Al alloy made of Al laminated on the Ti. it can. By configuring the source electrode 16 with a metal containing Al, the source electrode 16 can be in good ohmic contact with the n ⁺ -type GaN source layer 5. In addition, the source electrode 16 may be made of Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide), or W or W compound (for example, tungsten silicide).

  A drain electrode 17 is formed in contact with the other surface (lower surface) of the substrate 1. The drain electrode 17 is in ohmic contact with the substrate 1 and can be configured using, for example, the same type of metal as the source electrode 16, that is, a metal such as a Ti / Al alloy. In addition, the drain electrode 17 may be made of Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide), or W or W compound (for example, tungsten silicide).

When an insulating substrate such as sapphire is used as the substrate 1, for example, an opening is formed in the insulating film 12 in the lead portion 9. A drain electrode is formed so as to make ohmic contact with the n ⁺ GaN drain layer 6 through this opening.
Next, the operation of the nitride semiconductor device will be described.
An operating voltage (for example, 200 V) is applied between the source electrode 16 and the drain electrode 17 so that the drain electrode 17 side is positive. Thus, a reverse voltage is applied to the pn junction at the interface between the n ⁻ -type GaN drift layer 7 and the p-type GaN channel layer 4, and as a result, a depletion layer is directed from this interface toward the n ⁺ -type GaN drain layer 6. 20 spreads. As a result, the gap between the n ⁺ -type GaN source layer 5 and the n ⁺ -type GaN drain layer 6, that is, between the source electrode 16 and the drain electrode 17 (between the source and drain) is cut off. In this state, when a bias equal to or higher than the gate threshold voltage that is positive with the source electrode 16 as a reference potential is applied to the gate electrode 13, electrons are induced near the interface with the gate insulating film 12 in the channel region 14. Thus, an inversion layer (channel) is formed. The n-type layer 3 and the n ⁺ -type GaN source layer 5 are electrically connected via the inversion layer. Thus, conduction between the source and the drain is established. That is, when a predetermined bias is applied to the gate electrode 13, the source and the drain are conducted, and when no bias is applied to the gate electrode 13, the source and the drain are cut off. In this way, normally-off transistor operation is realized.

FIG. 2 is a diagram showing the results of examining the relationship between the acceptor concentration of the p-type GaN channel layer 4 and the width of the depletion layer 20 extending in the n ⁻ -type GaN drift layer 7. However, the n-type impurity (donor) concentration of the n ⁻ -type GaN drift layer 7 was 1 × 10 ¹⁷ cm ^−3, and 200 V was applied as an operating voltage between the source and drain. The “width of the depletion layer 20” is a width of the depletion layer 20 extending from the pn junction interface between the p-type GaN channel layer 4 and the n ⁻ -type GaN drift layer 7 to the drain layer 6 side.

As can be understood from FIG. 2, the width of the depletion layer 20 increases as the acceptor concentration of the p-type GaN channel layer 4 is increased. However, the width of the depletion layer 20 is saturated at an acceptor concentration of a certain level or more. You can see that In other words, there is a certain upper limit on the width of the depletion layer 20 regardless of the acceptor concentration of the p-type GaN channel layer 4. From this, when the n type impurity concentration of the n ⁻ type drift layer 7 is 1 × 10 ¹⁷ cm ⁻³ , a value of 1.5 μm or less is presented as a condition for not forming a region where the depletion layer does not fully spread. Then, a value of 1 μm is presented as the film thickness that guarantees a withstand voltage of 400V. In this way, by fabricating a punch-through transistor in which the n ⁻ -type GaN drift layer 7 is completely depleted when the transistor is turned off and the depletion layer is in contact with the n ⁺ -type GaN drain layer 6, the required breakdown voltage is reduced. Thus, a transistor with lower on-resistance can be realized.

3A to 3H are schematic cross-sectional views for explaining a method for manufacturing the nitride semiconductor device of FIG.
In manufacturing the nitride semiconductor element, a substrate 1 is prepared, and the nitride semiconductor multilayer structure portion 2 is formed on the substrate 1 by, for example, MOCVD (Metal Organic Chemical Vapor Deposition). Each layer is crystal grown.

More specifically, first, by growing GaN under the growth conditions of growth temperature: 1000 ° C. to 1100 ° C. and growth time: 20 minutes to 30 minutes, as shown in FIG. 3A, the n ⁺ -type GaN drain layer 6 Then, an n ⁻ -type GaN drift layer 7 is formed. Thus, the n-type layer 3 composed of the n ⁺ -type GaN drain layer 6 and the n ⁻ -type GaN drift layer 7 is formed. For example, Si can be used as an n-type impurity doped in the grown GaN. When the n ⁺ -type GaN drain layer 6 is grown, the flow rate of the silicon source gas (silane) is relatively increased, and when the n ⁻ -type GaN drift layer 7 is grown, the flow rate of the silicon source gas is relatively reduced.

the n ^- Following the formation of the type GaN drift layer 7, n ^- on type GaN drift layer 7, for example, growth temperature: 950 ° C. to 1050 ° C., growth time: growing a GaN growth condition for 30 minutes to 50 minutes By doing so, the p-type GaN channel layer 4 is formed as shown in FIG. 3B. Note that, for example, Mg or Zn can be used as the p-type impurity to be doped in the grown GaN.

p-type GaN channel layer 4 after formation, for example, growth temperature: 1000 ° C. C. to 1100 ° C., growth time: by growing GaN in the growth conditions of 5 to 15 minutes, as shown in FIG. 3C, n ⁺ A type GaN source layer 5 is formed. Note that, for example, Si can be used as an n-type impurity to be doped in the grown GaN. In this way, the nitride semiconductor multilayer structure portion 2 including the n ⁺ -type GaN drain layer 6, the n ⁻ -type GaN drift layer 7, the p-type GaN channel layer 4 and the n ⁺ -type GaN source layer 5 is formed on one side of the substrate 1. Is done.

After the nitride semiconductor multilayer structure portion 2 is thus formed, the nitride semiconductor multilayer structure portion 2 is etched in a stripe shape. That is, a striped trench 18 having a substantially inverted trapezoidal cross section extending from the n ⁺ -type GaN layer source 5 to the middle layer thickness of the n ⁻ -type GaN drain layer 6 is formed by etching. Thereby, as shown in FIG. 3D, a plurality of nitride semiconductor multilayer structures 2 (three appear in FIG. 3D, etc.) are striped (stripes extending in a direction perpendicular to the paper surface of FIG. 3D, etc.). And a lead portion 9 made of an extension of the n ⁻ -type GaN drain layer 6 is formed at the same time. The trench 18 can be formed, for example, by dry etching (anisotropic etching) using a chlorine-based gas.

  A trench 10 having a substantially V-shaped cross section is formed in the vicinity of the intermediate portion in the width direction of each nitride semiconductor multilayer structure portion 2 along the longitudinal direction of the nitride semiconductor multilayer structure portion 2. The trench 10 can be formed by dry etching (anisotropic etching) using a chlorine-based gas, similarly to the trench 18. In addition, after the dry etching, a wet etching process for improving the wall surface 11 of the trench 10 damaged by the dry etching may be performed as necessary. For wet etching, it is preferable to improve the damaged wall surface 11 by wet etching with KOH (potassium hydroxide), NaOH (sodium hydroxide), or the like. Further, HF (hydrofluoric acid), HCl (hydrochloric acid), or the like can be used. As a result, Si-based oxide, Ga oxide, and the like are removed, and the wall surface 11 can be leveled. By reducing the damage to the wall surface 11, the crystal state of the channel region 14 (see FIG. 1) can be kept good, and the interface between the wall surface 11 and the gate insulating film 12 should be a good interface. Therefore, the interface state can be reduced. Thereby, the channel resistance can be reduced and the leakage current can be suppressed. Note that a low-damage dry etching process can be applied instead of the wet etching process.

Next, as shown in FIG. 3E, the n ⁺ type GaN drain layer 6, the n ⁻ type GaN drift layer 7, the p type GaN channel layer 4 and the n ⁺ type GaN are covered while covering the wall surface 11 of the substantially V-shaped trench 10. A gate insulating film 12 covering the surface of the source layer 5 is formed. For the formation of the gate insulating film 12, it is preferable to apply an ECR (Electron Cyclotron Resonance) sputtering method.

Thereafter, the gate insulating film 12 is dry-etched in stripes by a known photolithography technique through a photoresist (not shown) having an opening in a region where the opening 15 is to be formed. Thereby, as shown in FIG. 3F, an opening 15 is formed, and the n ⁺ -type GaN layer 5 is partially exposed.
Next, a metal (for example, Ti and Al) used as a material of the source electrode 16 is formed by a known photolithography technique through a photoresist (not shown) having an opening in a region where the source electrode 16 is to be formed. Then, sputtering is performed in the order of Ti / Al by sputtering. Thereafter, by removing the photoresist, unnecessary portions of metal (portions other than the source electrode 16) are lifted off together with the photoresist. Through these steps, the source electrode 16 is formed as shown in FIG. 3G. After the source electrode 16 is formed, a thermal alloy (annealing process) is performed so that the contact between the source electrode 16 and the n ⁺ -type GaN layer 5 becomes an ohmic contact.

Thereafter, in the same manner as in the case of the source electrode 16, as shown in FIG. 3G, the gate facing the edge of the trench 10 on the wall surface 11 and the upper surface of the n ⁺ -type GaN source layer 5 with the gate insulating film 12 interposed therebetween. Electrode 13 is formed.
Then, the drain electrode 17 is formed on the other surface (lower surface) of the substrate 1 by the same method as that for the source electrode 16 as shown in FIG. 3H. Thus, the nitride semiconductor device shown in FIG. 1 can be obtained.

The plurality of nitride semiconductor multilayer structures 2 formed in a stripe form each form a unit cell. The gate electrode 13 and the source electrode 16 of the nitride semiconductor multilayer structure portion 2 are commonly connected at positions not shown. The drain electrode 17 is formed in contact with the substrate 1 and is a common electrode for all cells.
As mentioned above, although one Embodiment of this invention was described, this invention can also be implemented with another form. For example, in the above-described embodiment, an example in which GaN is used as the group III nitride semiconductor has been described. However, a similar punch-through transistor may be configured using another group III nitride semiconductor such as AlGaN. In this case, it is not necessary to use a single group III nitride semiconductor. For example, the nitride semiconductor multilayer structure 2 may be formed by combining a GaN layer and an AlGaN layer. In the above-described embodiment, a transistor having an operating voltage of 200 V (withstand voltage of 200 V) is taken as an example, but the operating voltage value may be another value. Furthermore, the impurity concentration of the n ⁻ -type GaN drift layer 7 may be a value higher than 1 × 10 ¹⁷ cm ⁻³ , and in this case, the upper limit width of the depletion layer 20 is smaller than the example of FIG. Become. Therefore, the layer thickness of the n ⁻ -type GaN drift layer 7 can be set small accordingly. In addition, various design changes can be made within the scope of matters described in the claims.

Example 1
In the structure of FIG. 1, the impurity concentration and layer thickness of each layer are as follows.
GaN source layer 5: n-type impurity concentration = 2 × 10 ¹⁸ cm ⁻³ , layer thickness = 0.5 μm
GaN channel layer 4: p-type impurity concentration = 3 × 10 ¹⁷ cm ⁻³ , layer thickness = 0.6 μm
GaN drift layer 7: n-type impurity concentration = 2 × 10 ¹⁶ cm ⁻³ , layer thickness = 0.96 μm
GaN drain layer 6: n-type impurity concentration = 2 × 10 ¹⁸ cm ⁻³ , layer thickness = 0.5 μm
GaN substrate 1: n-type impurity concentration = 2 × 10 ¹⁸ cm ⁻³
In this structure, when a voltage of 396 V is applied between the source electrode 16 and the drain electrode 17 in the transistor off state, breakdown between the drain and the source occurs, and at that time, drift occurs from the interface between the drift layer 7 and the channel layer 4. The width of the depletion layer extending to the layer 7 side is 0.96 μm, and this depletion layer reaches the drain layer 6. Further, a depletion layer having a width of 0.072 μm is generated in the drain layer 6. At this time, the width of the depletion layer extending from the interface between the drift layer 7 and the channel layer 4 to the channel layer 4 side is 0.55 μm.

Example 2
In the structure of FIG. 1, the impurity concentration and layer thickness of each layer are as follows.
GaN source layer 5: n-type impurity concentration = 2 × 10 ¹⁸ cm ⁻³ , layer thickness = 0.5 μm
GaN channel layer 4: p-type impurity concentration = 3 × 10 ¹⁷ cm ⁻³ , layer thickness = 0.6 μm
GaN drift layer 7: n-type impurity concentration = 8.7 × 10 ¹⁶ cm ⁻³ , layer thickness = 1.9 μm
GaN drain layer 6: n-type impurity concentration = 2 × 10 ¹⁸ cm ⁻³ , layer thickness = 0.5 μm
GaN substrate 1: n-type impurity concentration = 2 × 10 ¹⁸ cm ⁻³
In this structure, when a voltage of 402 V is applied between the source electrode 16 and the drain electrode 17 in the transistor off state, breakdown between the drain and the source occurs, and at that time, drift occurs from the interface between the drift layer 7 and the channel layer 4. The width of the depletion layer extending to the layer 7 side is 1.9 μm, and this depletion layer reaches the drain layer 6. At this time, the width of the depletion layer extending from the interface between the drift layer 7 and the channel layer 4 to the channel layer 4 side is 0.55 μm.

  Comparing Examples 1 and 2, in Example 1 in which the impurity concentration of the drift layer 7 was set low, the thickness of the drift layer 2 was 0.96 μm (approximately 1 μm, approximately 1/2 μm of Example 2), which is 1 μm or less. However, sufficient withstand voltage is secured. That is, in Example 1, the thickness of the drift layer 2 is reduced while ensuring a sufficient breakdown voltage, thereby achieving a low on-resistance. Of course, since the layer thickness of the entire group III nitride semiconductor multilayer structure is reduced, the GaN growth time can be shortened, and the productivity can be improved.

Example 3
In the structure of FIG. 1, the impurity concentration and layer thickness of each layer are as follows.
GaN source layer 5: n-type impurity concentration = 2 × 10 ¹⁸ cm ⁻³ , layer thickness = 0.5 μm
GaN channel layer 4: p-type impurity concentration = 3 × 10 ¹⁷ cm ⁻³ , layer thickness = 0.6 μm
GaN drift layer 7: n-type impurity concentration = 2 × 10 ¹⁶ cm ⁻³ , layer thickness = 0.3 μm
GaN drain layer 6: n-type impurity concentration = 2 × 10 ¹⁸ cm ⁻³ , layer thickness = 0.5 μm
GaN substrate 1: n-type impurity concentration = 2 × 10 ¹⁸ cm ⁻³
In this structure, when a voltage of 200 V is applied between the source electrode 16 and the drain electrode 17 in the transistor off state, breakdown between the drain and the source occurs, and at that time, drift occurs from the interface between the drift layer 7 and the channel layer 4. The width of the depletion layer extending to the layer 7 side is 0.3 μm, and this depletion layer reaches the drain layer 6. Further, a depletion layer having a width of 0.079 μm is generated in the drain layer 6. At this time, the width of the depletion layer extending from the interface between the drift layer 7 and the channel layer 4 to the channel layer 4 side is 0.55 μm.

Example 4
In the structure of FIG. 1, the impurity concentration and layer thickness of each layer are as follows.
GaN source layer 5: n-type impurity concentration = 2 × 10 ¹⁸ cm ⁻³ , layer thickness = 0.5 μm
GaN channel layer 4: p-type impurity concentration = 3 × 10 ¹⁷ cm ⁻³ , layer thickness = 0.6 μm
GaN drift layer 7: n-type impurity concentration = 2.4 × 10 ¹⁷ cm ⁻³ , layer thickness = 0.68 μm
GaN drain layer 6: n-type impurity concentration = 2 × 10 ¹⁸ cm ⁻³ , layer thickness = 0.5 μm
GaN substrate 1: n-type impurity concentration = 2 × 10 ¹⁸ cm ⁻³
In this structure, when a voltage of 203 V is applied between the source electrode 16 and the drain electrode 17 in the transistor off state, breakdown between the drain and the source occurs, and at that time, drift occurs from the interface between the drift layer 7 and the channel layer 4. The width of the depletion layer extending to the layer 7 side is 0.68 μm, and this depletion layer reaches the drain layer 6. At this time, the width of the depletion layer extending from the interface between the drift layer 7 and the channel layer 4 to the channel layer 4 side is 0.55 μm.

In contrast to Examples 3 and 4, in Example 3 in which the impurity concentration of the drift layer 7 was set to be lower than 1 × 10 ¹⁷ cm ⁻³ , the thickness of the drift layer 2 was less than 0.5 μm (1 in Example 4). / 2 or less), a sufficient breakdown voltage is secured. That is, in Example 3, the drift layer 2 has a small thickness while ensuring a sufficient breakdown voltage, thereby achieving a low on-resistance. Of course, since the layer thickness of the entire group III nitride semiconductor multilayer structure is reduced, the GaN growth time can be shortened, and the productivity can be improved.

Comparative Example A structure similar to that shown in FIG. 1 was formed using silicon, and the impurity concentration and layer thickness of each layer were as follows.
Si source layer: n-type impurity concentration = 2 × 10 ¹⁸ cm ⁻³ , layer thickness = 0.5 μm
Si channel layer: p-type impurity concentration = 3 × 10 ¹⁷ cm ⁻³ , layer thickness = 0.6 μm
Si drift layer: n-type impurity concentration = 1.1 × 10 ¹⁵ cm ⁻³ , layer thickness = 13.56 μm
Si drain layer: n-type impurity concentration = 2 × 10 ¹⁸ cm ⁻³ , layer thickness = 0.5 μm
Si substrate: n-type impurity concentration = 2 × 10 ¹⁸ cm ⁻³
In this structure, when a voltage of 204 V is applied between the source and the drain in the transistor off state, breakdown between the drain and the source occurs, and the width of the depletion layer spreading from the interface between the drift layer and the channel layer toward the drift layer at that time point Is 13.56 μm, and this depletion layer reaches the drain layer. At this time, the width of the depletion layer extending from the interface between the drift layer and the channel layer to the channel layer side is 0.05 μm.

In the case of Si, the dielectric breakdown electric field is 0.3 MV / cm, which is about 1/10 of GaN. Therefore, the locally applied electric field must be sufficiently low. Therefore, the impurity concentration of the drift layer must be suppressed to the order of 10 ¹⁵ cm ⁻³ or less, and the film thickness exceeds 10 μm. Therefore, the problem of high on-resistance is inevitable.

It is typical sectional drawing for demonstrating the structure of the nitride semiconductor element which forms the punch through type transistor which concerns on one Embodiment of this invention. It is a figure which shows the result of having investigated the relationship between the acceptor density | concentration of a channel layer, and the width | variety of the depletion layer extended to a drift layer. FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the nitride semiconductor device of FIG. 1. It is typical sectional drawing which shows the next process of FIG. 3A. It is typical sectional drawing which shows the next process of FIG. 3B. FIG. 3D is a schematic cross-sectional view showing the next step of FIG. 3C. FIG. 3D is a schematic cross-sectional view showing a step subsequent to FIG. 3D. It is typical sectional drawing which shows the next process of FIG. 3E. It is typical sectional drawing which shows the next process of FIG. 3F. It is typical sectional drawing which shows the next process of FIG. 3G.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Board | substrate 2 Nitride semiconductor laminated structure part 3 n-type layer 4 p-type GaN channel layer (3rd layer)
5 n ⁺ -type GaN source layer (fourth layer)
6 n ⁺ -type GaN drain layer (first layer)
7 n ^- type GaN drift layer (second layer)
DESCRIPTION OF SYMBOLS 9 Lead part 10 Trench 11 Wall surface 12 Gate insulating film 13 Gate electrode 14 Channel area | region 15 Opening 16 Source electrode 17 Drain electrode 18 Trench 20 Depletion layer

Claims (3)

A transistor comprising a group III nitride semiconductor,
a first layer made of an n-type group III nitride semiconductor;
A second layer formed on the first layer and made of an n-type group III nitride semiconductor having an impurity concentration different from that of the first layer;
A third layer made of a p-type group III nitride semiconductor on the second layer;
A fourth layer made of an n-type group III nitride semiconductor on the third layer;
A gate insulating film formed on a wall surface straddling the second layer, the third layer, and the fourth layer;
A gate electrode disposed opposite to the third layer via the gate insulating film,
A transistor in which a depletion layer extending in the second layer reaches the first layer by an operating voltage applied between the first layer and the fourth layer in an off state of the transistor. 2. The transistor according to claim 1, wherein the thickness of the second layer is 1 μm or less, and the n-type impurity concentration of the second layer is 1 × 10 ¹⁷ cm ⁻³ or less. 3. The transistor according to claim 1, wherein the operating voltage is 350 V or more, and the n-type impurity concentration of the second layer is 2 × 10 ¹⁶ cm ⁻³ or less.

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