JP2009182609A - Signal level conversion circuit - Google Patents

Abstract

A control signal for switching a signal direction of a bidirectional type signal level conversion circuit is made unnecessary.
A bidirectional type signal level conversion circuit is provided with a VCCA circuit unit, a VCCB circuit unit, a level shifter circuit, and a level shifter circuit. The VCCA system circuit section 1 is provided with an input / output terminal PadA, an inverter INV1, an inverter INV4, a latch circuit LATCH1, an output buffer circuit SBUFF2, a delay circuit DIN3, a delay circuit DIN4, a two-input NAND circuit NAND2, and a two-input NOR circuit NOR2. . The VCCB system circuit section 2 includes an input / output terminal PadB, an inverter INV2, an inverter INV3, a latch circuit LATCH2, an output buffer circuit SBUFF1, a delay circuit DIN1, a delay circuit DIN2, a two-input NAND circuit NAND1, and a two-input NOR circuit NOR1. . The signal level conversion circuit 70 does not require a direction switching control signal.
[Selection] Figure 1

Description

  The present invention relates to a bidirectional signal level conversion circuit.

  In a semiconductor integrated circuit (LSI) composed of a CMOS (Complementary Metal Oxide Semiconductor) or the like and having a logic circuit and a sequential circuit, a signal level conversion circuit (level shift circuit) that shifts the signal level between different high-potential side power supplies Also called). The signal level conversion circuit includes a one-way type that allows a signal to flow only in one direction, and a bidirectional type that allows a signal to flow in both directions based on a direction switching control signal that controls the signal processing direction (for example, , See Patent Document 1).

The bidirectional signal level conversion circuit described in Patent Document 1 has a problem that it cannot be used for a system in which a direction switching control signal is not provided. In addition, when the direction switching control signal is supplied from the outside, a dedicated terminal is required, which increases the number of external terminals. Further, when a boost circuit or the like is incorporated as a bidirectional type signal level conversion circuit that does not use a direction switching control signal, there is a problem that high-speed full swing operation becomes difficult.
Japanese Patent Laying-Open No. 2005-176172 (page 20, FIG. 22)

  The present invention provides a bidirectional type signal level conversion circuit that does not require a direction switching control signal.

  A signal level conversion circuit of one embodiment of the present invention includes a first output buffer circuit that includes a first input / output terminal, first and second insulated gate field effect transistors, and outputs a first output signal. And a first latch circuit provided between the first input / output terminal and the first output buffer circuit, and first and second delay means, wherein the first high-potential-side power supply is A first level shift circuit unit to be supplied; a first level shifter circuit that receives a signal output from the first level shift circuit unit and outputs a first signal obtained by level shifting the signal; A second output buffer circuit that outputs a second output signal, the second input / output terminal, and the second input / output terminal, the third and fourth insulated gate field effect transistors, Second latch provided between output buffer circuits A second level shift circuit section having a path and third and fourth delay means, to which a second high potential side power source having a voltage higher than that of the first high potential side power source is supplied, A second level shifter circuit that receives a signal output from the second level shift circuit unit and outputs a second signal obtained by level-shifting this signal to the first level shifter circuit; When a signal is input to the input / output terminal, when the second signal rises, the first high-potential-side power supply side is provided for the first delay time of the first delay means. When the insulated gate field effect transistor is turned on, the first output signal latched at the high level by the first latch circuit is output from the first input / output terminal, and the second signal falls. A second delay time of the second delay means; The second insulated gate field effect transistor provided on the low potential side power supply side is turned on, and the first output signal latched at the low level by the first latch circuit is the first input / output terminal When the first signal rises, the second high-potential-side power supply is output during the third delay time of the third delay means when the signal is input to the first input / output terminal. The third insulated gate field effect transistor provided on the side is turned on, and the second output signal latched at the high level by the second latch circuit is output from the second input / output terminal, When the first signal falls, the fourth insulated gate field effect transistor provided on the low potential side power supply side is turned on during the fourth delay time of the fourth delay means, and the second latch circuit To latch low The second output signal is output from the second input / output terminal.

  According to the present invention, it is possible to provide a bidirectional type signal level conversion circuit that does not require a direction switching control signal.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a signal level conversion circuit according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a bidirectional type signal level conversion circuit. In this embodiment, the direction switching control signal of the bidirectional type signal level conversion circuit is not required.

  As shown in FIG. 1, the bidirectional signal level conversion circuit 70 is provided with a VCCA system circuit unit 1, a VCCB system circuit unit 2, a level shifter circuit LS1, and a level shifter circuit LS2. The signal level conversion circuit 70 is used in a mobile terminal device such as a PDA (Personal Digital Assistant).

  The VCCA circuit section 1 as the first level shift circuit section includes an input / output terminal PadA, an inverter INV1, an inverter INV4, a latch circuit LATCH1, an output buffer circuit SBUFF2, a delay circuit DIN3, a delay circuit DIN4, and a two-input NAND circuit NAND2. , And a two-input NOR circuit NOR2. The VCCA system circuit unit 1 is supplied with the high potential side power supply VCCA of the first power supply system. The high potential side power supply VCCA voltage is set to, for example, 1.8 V in the range of 1.1 to 2.7 V.

  The first input / output terminal PadA receives an external signal, outputs the signal to the VCCA system circuit unit 1, outputs the signal from the output buffer circuit SBUFF2, and outputs the signal latched by the latch circuit LATCH1.

  The latch circuit LATCH1 is provided between the input / output terminal PadA and the node N1, and latches data on the node N1 side. The latch circuit LATCH1 is provided with an inverter INV11 and an inverter INV12. The input side of the inverter INV11 and the output side of the inverter INV12 are connected to the node N1 side, and the output side of the inverter INV11 is connected to the input side of the inverter INV12.

  The inverter INV1 is provided between the node N1 and the node N2, receives the signal of the node N1, and outputs a signal obtained by inverting the signal from the node N2. The inverter INV1 functions as an inverting buffer.

  The inverter INV4 is provided between the node N13 and the node N14, receives the signal of the node N13, and outputs a signal obtained by inverting the signal from the node N14. The inverter INV4 functions as an inverting buffer.

  The third delay circuit DIN3 is provided between the node N14 and the node N15, delays the signal of the node N14, and outputs the delayed signal from the node N15. The fourth delay circuit DIN4 is provided between the node N14 and the node N16, delays the signal of the node N14, and outputs the delayed signal from the node N16.

  The 2-input NAND circuit NAND2 is provided between the nodes N14 and N15 and the node N17, and outputs a logically operated signal from the node N17. When both of the signals at the nodes N14 and N15 are at “High” level, a “Low” level signal is output from the node N17, and at other times, a “High” level signal is output from the node N17.

  The 2-input NOR circuit NOR2 is provided between the nodes N14 and N16 and the node N18, and outputs a logically operated signal from the node N18. When both of the signals at the nodes N14 and N16 are at the “Low” level, a “High” level signal is output from the node N18, and at other times, a “Low” level signal is output from the node N18.

  The output buffer circuit SBUFF2 is provided between the nodes N17 and N18 and the node N19. The output buffer circuit SBUFF2 is provided with a Pch MOS transistor PT2 and an Nch MOS transistor NT2, and outputs an output signal from the node N19. The MOS transistor has a gate insulating film made of a silicon oxide film, and is also referred to as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In the MIS transistor, the gate insulating film is made of an insulating film other than a silicon oxide film such as a NO film or a high K gate insulating film, and is also called a MISFET (Metal Insulator Semiconductor Field Effect Transistor). The MOS transistor and the MIS transistor are also called insulated gate field effect transistors.

  The Pch MOS transistor PT2 has a source (second terminal) connected to the high potential side power supply VCCA, a gate (control terminal) connected to the node N17, a drain (first terminal) connected to the node N19, When the signal at N17 is at "Low" level, the signal is turned "ON" and the output side node N19 is set to "High" level (VCCA level).

  The Nch MOS transistor NT2 has a drain (first terminal) connected to the node N19, a gate (control terminal) connected to the node N18, and a source (second terminal) connected to the low potential side power supply (ground potential) VSS. When the signal of the node N18 is “High” level, it is “ON” and the output side node N19 is set to “Low” level (VSS level).

  The VCCB system circuit section 2 as the second level shift circuit section includes an input / output terminal PadB, an inverter INV2, an inverter INV3, a latch circuit LATCH2, an output buffer circuit SBUFF1, a delay circuit DIN1, a delay circuit DIN2, and a two-input NAND circuit NAND1. , And a two-input NOR circuit NOR1. The VCCB system circuit unit 1 is supplied with the high potential side power supply VCCB of the second power supply system having a higher voltage than the high potential side power supply VCCA of the first power supply system. The high potential side power supply VCCB voltage is set to, for example, 3.3 V in the range of 2.3 to 3.6 V.

  A signal is input from the outside to the second input / output terminal PadB, the signal is output to the VCCB system circuit unit 2, output from the output buffer circuit SBUFF1, and a signal latched by the latch circuit LATCH2 is output.

  The latch circuit LATCH2 is provided between the input / output terminal PadB and the node N9, and latches data on the node N9 side. The latch circuit LATCH2 is provided with an inverter INV13 and an inverter INV14. The input side of the inverter INV13 and the output side of the inverter INV14 are connected to the node N9 side, and the output side of the inverter INV13 is connected to the input side of the inverter INV14.

  The inverter INV3 is provided between the node N9 and the node N12, receives the signal of the node N9, and outputs a signal obtained by inverting the signal from the node N12. The inverter INV3 functions as an inverting buffer.

  The inverter INV2 is provided between the node N3 and the node N4, receives the signal of the node N3, and outputs a signal obtained by inverting the signal from the node N4. The inverter INV2 functions as an inverting buffer.

  The first delay circuit DIN1 is provided between the node N4 and the node N5, delays the signal of the node N4, and outputs the delayed signal from the node N5. The second delay circuit DIN2 is provided between the node N4 and the node N6, delays the signal of the node N4, and outputs the delayed signal from the node N6.

  The 2-input NAND circuit NAND1 is provided between the nodes N4 and N5 and the node N7, and outputs a logically operated signal from the node N7. When both of the signals at the nodes N4 and N5 are at “High” level, a “Low” level signal is output from the node N7, and at other times, a “High” level signal is output from the node N7.

  The 2-input NOR circuit NOR1 is provided between the nodes N4 and N6 and the node N8, and outputs a logically operated signal from the node N8. When the signals at the nodes N4 and N6 are both at the “Low” level, a “High” level signal is output from the node N8, and at other times, the “Low” level signal is output from the node N8.

  The output buffer circuit SBUFF1 is provided between the nodes N7 and N8 and the node N9. The output buffer circuit SBUFF1 is provided with a Pch MOS transistor PT1 and an Nch MOS transistor NT1, and outputs an output signal from the node N9.

  The Pch MOS transistor PT1 has a source (second terminal) connected to the high potential side power supply VCCB, a gate (control terminal) connected to the node N7, a drain (first terminal) connected to the node N9, and a node When the signal of N7 is at “Low” level, it is turned “ON” and the output side node N9 is set to “High” level (VCCB level).

  The Nch MOS transistor NT1 has a drain (first terminal) connected to the node N9, a gate (control terminal) connected to the node N8, and a source (second terminal) connected to the low potential side power supply (ground potential) VSS. When the signal of the node N8 is “High” level, it is “ON” and the output side node N9 is set to “Low” level (VSS level).

  The first level shifter circuit LS1 is provided between the VCCA system circuit unit 1 and the VCCB system circuit unit 2, receives a signal of the node N2, and receives a signal obtained by level-shifting (increasing the amplitude level) the signal level of the node N2. Output from node N3. The second level shifter circuit LS2 is provided between the VCCB system circuit unit 2 and the VCCA system circuit unit 1, receives a signal of the node N12, and receives a signal obtained by level-shifting (reducing the amplitude level) the signal level of the node N12. Output from node N13.

  Here, it is preferable that the inverters INV to INV 4 functioning as inverting buffers have a larger driving capability than the inverters INV11 and IN12 constituting the latch circuit LATCH1 and the inverters INV13 and IN14 constituting the latch circuit LATCH2.

  Note that although the inverter INV1 is provided between the node N1 and the node N2 and the inverter INV2 is provided between the node N3 and the node N4, the number of inverters is not necessarily one, and the signals of the nodes N1 and N4 The number of inverters may be changed as appropriate so that they have the same phase. The inverter INV3 is provided between the node N9 and the node N12, and the inverter INV4 is provided between the node N13 and the node N14. However, the number of inverters is not necessarily one, and the nodes N9 and N14 are in the same phase. The number of inverters may be changed as appropriate. Further, a buffer may be provided instead of the inverter.

  Next, the configuration of the level shifter circuit and the delay circuit will be described with reference to FIGS. 2 is a circuit diagram showing a level shifter circuit, FIG. 2A is a circuit diagram showing a first level shifter circuit, and FIG. 2B is a circuit diagram showing a second level shifter circuit. 3 is a circuit diagram showing a delay circuit, FIG. 3A is a circuit diagram showing a first delay circuit, FIG. 3B is a circuit diagram showing a second delay circuit, and FIG. 3C is a third circuit diagram. FIG. 3D is a circuit diagram showing a fourth delay circuit.

  As shown in FIG. 2A, the first level shifter circuit LS1 is provided with an inverter INV21, an Nch MOS transistor NT11, an Nch MOS transistor NT12, a Pch MOS transistor PT11, and a Pch MOS transistor PT12.

  The Pch MOS transistor PT11 has a source connected to the high potential side power supply VCCB, a gate connected to the node N3, and a drain connected to the node N21. In the Pch MOS transistor PT12, the source is connected to the high potential side power supply VCCB, the gate is connected to the node N21, and the drain is connected to the node N3.

  The Nch MOS transistor NT11 has a drain connected to the node N21, a gate connected to the node N2, and a source connected to the low potential side power supply (ground potential) VSS. The Nch MOS transistor NT12 has a drain connected to the node N3 and a source connected to the low potential side power supply (ground potential) VSS.

  Inverter INV21 is provided between high potential side power supply VCCA and low potential side power supply (ground potential) VSS, and has an input side connected to node N2 and an output side connected to the gate of Nch MOS transistor NT12.

  As shown in FIG. 2B, the second level shifter circuit LS2 is provided with an inverter INV22, an Nch MOS transistor NT21, an Nch MOS transistor NT22, a Pch MOS transistor PT21, and a Pch MOS transistor PT22.

  Pch MOS transistor PT21 has a source connected to high potential side power supply VCCA, a gate connected to node N22, and a drain connected to node N13. The P-channel MOS transistor PT22 has a source connected to the high potential side power supply VCCA, a gate connected to the node N13, and a drain connected to the node N22.

  The Nch MOS transistor NT21 has a drain connected to the node N13 and a source connected to the low potential side power supply (ground potential) VSS. N-channel MOS transistor NT22 has a drain connected to node N22, a gate connected to node N12, and a source connected to low-potential-side power supply (ground potential) VSS.

  Inverter INV22 is provided between high potential side power supply VCCB and low potential side power supply (ground potential) VSS, and has an input side connected to node N12 and an output side connected to the gate of Nch MOS transistor NT21.

  As shown in FIG. 3A, the first delay circuit DIN1 is provided with g inverters (where g is an odd number) connected in cascade. The first delay circuit DIN1 receives the signal of the node N4, inverts the signal of the node N4, and outputs a signal delayed by the delay time td11 from the node N5.

  As shown in FIG. 3B, the second delay circuit DIN2 is provided with k cascaded inverters (where k is an odd number). The second delay circuit DIN2 receives the signal of the node N4, inverts the signal of the node N4, and outputs a signal delayed by the delay time td12 from the node N6.

  As shown in FIG. 3C, the third delay circuit DIN3 is provided with m cascaded inverters (where m is an odd number). The third delay circuit DIN3 receives the signal of the node N14, inverts the signal of the node N14, and outputs a signal delayed by the delay time td13 from the node N15.

  As shown in FIG. 3D, the fourth delay circuit DIN4 is provided with n cascaded inverters (where n is an odd number). The fourth delay circuit DIN4 receives the signal of the node N14, inverts the signal of the node N14, and outputs a signal delayed by the delay time td14 from the node N16.

  Next, the operation of the bidirectional type signal level conversion circuit will be described with reference to FIGS. FIG. 4 is a timing chart showing the operation of the bidirectional type signal level conversion circuit when a signal is transmitted from the first input / output terminal to the second input / output terminal, and FIG. 6 is a timing chart showing an operation of a bidirectional type signal level conversion circuit when a signal is transmitted to one input / output terminal.

  As shown in FIG. 4, when a signal is transmitted from the first input / output terminal to the second input / output terminal, the signal levels of the first input terminal PadA and the second input terminal PadB are set to the low potential side power supply ( When the ground potential is at the VSS level, the nodes N4 and N9 are at the VSS level.

  Since the node N7 is at the high potential side power supply VCCB level, the node N8 is at the VSS level, and the Pch MOS transistor PT1 and the Nch MOS transistor NT1 of the output buffer circuit SBUFF1 are both “OFF”, the latch circuit LATCH2 latches them to the VSS level. The signal at node N9 is at the VSS level.

Next, when the signal at the node N1 rises (from the VSS level to the high-potential-side power supply VCCA level), the signal at the node N4 rises after a delay time td1 (from the VSS level to the high-potential-side power supply VCCB level). The delay time td1 is
td1 ＝ tdINV1 ＋ tdLS1 ＋ tdINV2 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Formula (1)
It is expressed as Note that tdINV1 is the delay time of the fall of the inverter INV1, tdLS1 is the delay time of the fall of the first level shifter circuit LS1, and tdINV2 is the delay time of the rise of the inverter INV2.

  Subsequently, the signal at the node N5 is delayed by the delay time td11 of the delay circuit DIN1, and inverted to change from the VCCB level to the VSS level. Since the node N4 and node N5 signals input to the two-input NAND circuit NAND1 are substantially at the VCCB level during the delay time td11, the node N7 is at the VSS level. As a result, the Pch MOS transistor PT1 of the output buffer circuit SBUFF1 is turned “ON” during the substantially delay time td11, and the signal at the node N9 becomes the VCCB level which is the “High” level. The VCCB level data is latched by the latch circuit LATCH2 and output from the second input / output terminal PadB.

  The data is latched by the latch circuit LATCH2 until the Nch MOS transistor NT1 of the output buffer circuit SBUFF1 is turned “ON”. Since the signal of the node N8 maintains the VSS level, the Nch MOS transistor NT1 of the output buffer circuit SBUFF1 is not “ON”.

When the signal at the node N1 falls (from the high potential side power supply VCCCA level to the VSS level), the signal at the node N4 falls after a delay time td2 (from the high potential side power supply VCCA level to the VSS level). The delay time td2 is
td2 = tdINV1a + tdLS1a + tdINV2a ··· Equation (2)
It is expressed as Note that tdINV1a is the delay time of the rise of the inverter INV1, tdLS1a is the delay time of the rise of the first level shifter circuit LS1, and tdINV2a is the delay time of the fall of the inverter INV2.

  Subsequently, the signal at the node N6 is delayed by the delay time td12 of the delay circuit DIN2, and inverted to change from the VSS level to the VCCB level. Since the signals of the node N4 and the node N6 input to the 2-input NOR circuit NOR1 are at the VSS level during the delay time td12, the node N8 is at the VCCB level. As a result, the Nch MOS transistor NT1 of the output buffer circuit SBUFF1 is turned “ON” during the substantially delay time td12, and the signal at the node N9 becomes the VSS level, which is the “Low” level. The VSS level data is latched by the latch circuit LATCH2 and output from the second input / output terminal PadB.

  This data is latched by the latch circuit LATCH2 until the Pch MOS transistor PT1 of the output buffer circuit SBUFF1 is turned “ON”. Since the signal at the node N7 maintains the VCCB level, the Pch MOS transistor PT1 of the output buffer circuit SBUFF1 is not “ON”.

  As shown in FIG. 5, when a signal is transmitted from the second input / output terminal to the first input / output terminal, the signal level of the second input terminal PadB and the signal level of the first input terminal PadA are “High”. At the “level”, the node N14 and the node N19 (node N1) are at the VCCA level.

  Since the node N17 is at the high potential side power supply VCCCA level, the node N18 is at the VSS level, and the Pch MOS transistor PT2 and the Nch MOS transistor NT2 of the output buffer circuit SBUFF2 are both “OFF”, the latch circuit LATCH1 latches the VCCA level. The signal at node N19 (node N1) is at VCCA level.

Next, when the signal at the node N9 falls (from the VCCB level to the VSS level), the signal at the node N14 falls (from the VCCB level to the VSS level) with a delay of the delay time td3. The delay time td3 is
td3 = tdINV3 + tdLS2 + tdINV4 ... Equation (3)
It is expressed as Note that tdINV1 is the delay time of the rise of the inverter INV3, tdLS2 is the delay time of the rise of the second level shifter circuit LS2, and tdINV4 is the delay time of the fall of the inverter INV4.

  Subsequently, the signal at the node N16 is delayed by the delay time td14 of the delay circuit DIN4, and inverted to change from the VSS level to the VCCA level. Since the signals of the node N14 and the node N16 input to the two-input NOR circuit NOR2 are at the VSS level for substantially the delay time td14, the node N18 is at the VCCA level. As a result, the Nch MOS transistor NT2 of the output buffer circuit SBUFF2 is turned “ON” during the substantially delay time td14, and the signal at the node N19 becomes the VSS level which is the “Low” level. The VSS level data is latched by the latch circuit LATCH1 and output from the first input / output terminal PadA.

  This data is latched by the latch circuit LATCH1 until the Pch MOS transistor PT2 of the output buffer circuit SBUFF2 is turned “ON”. Since the signal at the node N17 maintains the VCCA level, the Pch MOS transistor PT2 of the output buffer circuit SBUFF2 is not "ON".

When the signal at the node N9 rises (from the VSS level to the VCCB level), the signal at the node N14 rises with a delay of the delay time td4 (from the VSS level to the VCCB level). The delay time td4 is
td4 = tdINV3a + tdLS2a + tdINV4a Equation (4)
It is expressed as Note that tdINV3a is the delay time of the fall of the inverter INV3, tdLS2a is the delay time of the fall of the second level shifter circuit LS2, and tdINV4a is the delay time of the rise of the inverter INV4.

  Subsequently, the signal at the node N15 is delayed by the delay time td13 of the delay circuit DIN3 and inverted to change from the VCCA level to the VSS level. Since the signals of the node N14 and the node N15 input to the 2-input NAND circuit NAND2 are at the VCCA level during the delay time td13, the node N17 is at the VSS level. As a result, the Pch MOS transistor PT2 of the output buffer circuit SBUFF2 is turned “ON” during the substantially delay time td13, and the signal at the node N19 becomes the VCCA level which is the “High” level. The VCCA level data is latched by the latch circuit LATCH1 and output from the first input / output terminal PadA.

  This data is latched by the latch circuit LATCH1 until the Nch MOS transistor NT2 of the output buffer circuit SBUFF2 is turned “ON”. Since the signal of the node N18 maintains the VSS level, the Nch MOS transistor NT2 of the output buffer circuit SBUFF2 is not “ON”.

  As described above, in the signal level conversion circuit of this embodiment, the VCCA system circuit unit 1, the VCCB system circuit unit 2, the level shifter circuit LS1, and the level shifter circuit LS2 are provided. The VCCA system circuit section 1 is provided with an input / output terminal PadA, an inverter INV1, an inverter INV4, a latch circuit LATCH1, an output buffer circuit SBUFF2, a delay circuit DIN3, a delay circuit DIN4, a two-input NAND circuit NAND2, and a two-input NOR circuit NOR2. . The VCCB system circuit section 2 is provided with an input / output terminal PadB, an inverter INV2, an inverter INV3, a latch circuit LATCH2, an output buffer circuit SBUFF1, a delay circuit DIN1, a delay circuit DIN2, a two-input NAND circuit NAND1, and a two-input NOR circuit NOR1. . When an input signal is input from the input / output terminal PadA and a level-shifted signal is transmitted to the input / output terminal PadB, when the input signal rises, the delay circuit DIN1 and the 2-input NAND circuit NAND1 cause the Pch MOS of the output buffer circuit SBUFF1. The transistor PT1 is turned on, high level data is latched by the latch circuit LATCH2, and the latched high level data is output from the input / output terminal PadB. When the input signal falls, the delay circuit DIN2 and the two-input NOR circuit NOR1 turn on the Nch MOS transistor NT1 of the output buffer circuit SBUFF1, the low level data is latched by the latch circuit LATCH2, and the latched low level data is Output from the input / output terminal PadB. On the other hand, when an input signal is input from the input / output terminal PadB and a level-shifted signal is transmitted to the input / output terminal PadA, when the input signal rises, the delay circuit DIN3 and the 2-input NAND circuit NAND2 cause the output buffer circuit SBUFF2. The Pch MOS transistor PT2 is turned on, high level data is latched by the latch circuit LATCH1, and the latched high level data is output from the input / output terminal PadA. When the input signal falls, the Nch MOS transistor NT2 of the output buffer circuit SBUFF2 is turned on by the delay circuit DIN4 and the 2-input NOR circuit NOR2, the low level data is latched by the latch circuit LATCH1, and the latched low level data is Output from the input / output terminal PadA.

  For this reason, the bidirectional signal level conversion circuit 70 does not require a direction switching control signal. Further, a dedicated terminal for transmitting the direction switching control signal is not required. Further, when a boost circuit or the like is incorporated in a bidirectional signal level conversion circuit that does not use a direction switching control signal, high-speed full swing operation is difficult. Operation can be achieved.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, the present invention is applied to a mobile terminal device, but can be applied to a system including a CPU (Central Processing Unit) and a processor.

1 is a circuit diagram illustrating a bidirectional type signal level conversion circuit according to a first embodiment of the invention. FIG. 2A is a circuit diagram showing a first level shifter circuit, and FIG. 2B is a circuit diagram showing a second level shifter circuit according to the first embodiment of the present invention. FIG. 3A is a circuit diagram illustrating a first delay circuit, FIG. 3B is a circuit diagram illustrating a second delay circuit, and FIG. FIG. 3C is a circuit diagram showing a third delay circuit, and FIG. 3D is a circuit diagram showing a fourth delay circuit. 3 is a timing chart showing an operation of the bidirectional type signal level conversion circuit when a signal is transmitted from the first input / output terminal to the second input / output terminal according to the first embodiment of the present invention. 3 is a timing chart showing the operation of the bidirectional signal level conversion circuit when a signal is transmitted from the second input / output terminal to the first input / output terminal according to the first embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 VCCA system circuit part 2 VCCB system circuit part 70 Signal level conversion circuit DIN1-4 Delay circuit INV1-4, INV11-14, INV21, INV22 Inverter LATCH1, LATCH2 Latch circuit LS1, LS2 Level shifter circuits N1-9, N12-19 N21, N22 Node NAND1, NAND2 2-input NAND circuit NOR1, NOR2 2-input NOR circuit NT1, NT2 Nch, NT11, NT12, NT21, NT22 MOS transistor PadA, PadB Input / output terminals PT1, PT2, PT11, PT12, PT21, PT22 Pch MOS transistors SBUFF1, SBUFF2 Output buffer circuits td1-4, td11-14 Delay time VCCA, VCCB High potential side power supply VSS Low potential side power supply (ground potential)

Claims (5)

A first output buffer circuit including a first input / output terminal, first and second insulated gate field effect transistors and outputting a first output signal; the first input / output terminal; A first level shift circuit section having a first latch circuit provided between the output buffer circuits and first and second delay means, to which a first high potential side power supply is supplied,
A first level shifter circuit that receives a signal output from the first level shift circuit unit and outputs a first signal obtained by level shifting the signal;
A second output buffer circuit including a second input / output terminal; third and fourth insulated gate field effect transistors for outputting a second output signal; the second input / output terminal; A second latch circuit provided between the output buffer circuits, and a third and fourth delay means, and a second high potential power source having a voltage higher than that of the first high potential power source A second level shift circuit unit to which is supplied,
A second level shifter circuit that receives a signal output from the second level shift circuit unit and outputs a second signal obtained by level-shifting the signal to the first level shifter circuit;
Comprising
When a signal is input to the second input / output terminal, when the second signal rises, it is provided on the first high potential side power supply side during the first delay time of the first delay means. The first insulated gate field effect transistor is turned on, a first output signal latched at a high level by the first latch circuit is output from the first input / output terminal, and the second signal is At the time of falling, the second insulated gate field effect transistor provided on the low potential side power supply side is turned on during the second delay time of the second delay means, and the first latch circuit turns low level. Is output from the first input / output terminal,
When a signal is input to the first input / output terminal, when the first signal rises, it is provided on the second high potential side power supply side during a third delay time of the third delay means. The third insulated gate field effect transistor is turned on, a second output signal latched at a high level by the second latch circuit is output from the second input / output terminal, and the first signal is At the time of falling, the fourth insulated gate field effect transistor provided on the low potential side power supply side is turned on during the fourth delay time of the fourth delay means, and is turned to the low level by the second latch circuit. A signal level conversion circuit, wherein the latched second output signal is output from the second input / output terminal.   The first input / output terminal and the first level shifter circuit; the output side of the first level shifter circuit; the second input / output terminal and the second level shifter circuit; and the second level shifter circuit. 2. The signal level conversion circuit according to claim 1, wherein a buffer or an inverter is provided on each output side, and the buffer or the inverter has a drive capability larger than that of the inverter constituting the latch circuit.   The first and second delay means delay the second signal, the third and fourth delay means delay the first signal, and the first to fourth delay means are odd-numbered stages. The signal level conversion circuit according to claim 1, comprising an inverter.   A first NAND circuit that receives the signal output from the third delay means and the first signal and outputs a logically operated signal to a control terminal of the third insulated gate field effect transistor; A first NOR circuit that receives a signal output from a fourth delay means and the first signal and outputs a logically operated signal to a control terminal of the fourth insulated gate field effect transistor; A second NAND circuit that receives the signal output from the first delay means and the second signal and outputs a logically calculated signal to the control terminal of the first insulated gate field effect transistor; A second NOR circuit that receives the signal output from the delay means and the second signal, and outputs a logically operated signal to the control terminal of the second insulated gate field effect transistor; Signal level converting circuit according to claim 3, characterized in that it comprises. The first and third insulated gate field effect transistors are Pch MOS transistors or Pch MIS transistors, and the second and fourth insulated gate field effect transistors are Nch MOS transistors or Nch MIS transistors. The signal level conversion circuit according to any one of claims 1 to 4.

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