JP2009175764A - Alternating phase shift masking for multi-level masking resolution - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide alternating phase shift masks for multiple phase shift mask resolution levels for multiple feature classes. <P>SOLUTION: The process includes stages of: processing a pattern that defines features of first and second feature classes in a layer for a photolithography mask defining the layer; defining a first layout dimension relating to a phase shift window pair for a first feature resolution level and a second layout dimension relating to a phase shift window pair for a second feature resolution level; performing layout of a plurality of phase shift window pairs, including stages of using the first layout dimension relating to the phase shift window pair to the first feature class and of using the second layout dimension relating to the phase shift window pair to the second feature class; and assigning first and second phase shift values to phase shift windows in the plurality of phase shift window pairs. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to manufacturing small dimensional features of objects such as integrated circuits using a photolithographic mask. More precisely, the invention relates to the use of phase shift masking for complex layouts for integrated circuits and similar objects.

  Phase shift masking has been used to create small dimension features in integrated circuits, as described in US Pat. No. 5,858,580. Typically, these features have been limited to selected elements of the design that have small and critical dimensions. Although producing small dimension features in integrated circuits has resulted in improved speed and performance, it is desirable to apply phase shift masking more extensively in the manufacture of such devices. However, extending phase shift masking to more complex designs has resulted in a significant increase in the complexity of mask layout problems. For example, phase competition will occur when laying out phase shift areas in a high density design. One type of phase competition is that two phase shift regions having the same phase will be exposed by the mask, for example, overlapping phase shift regions to draw adjacent lines in the exposure pattern. It is position selection in the layout that is laid out in the vicinity of the modeling. If the phase shift regions have the same phase, they will not cause the optical interference necessary to create the desired effect. Therefore, it is necessary to prevent inadvertent layout of the phase shift regions that compete for phase. See "Alternate PSM design and its flow from design to manufacture", SAME, October 26, 2000, by Wu et al.

  Another problem with complex design layouts that rely on small dimensional build-up arises because of the isolated exposed space having narrow dimensions between unexposed areas or lines.

  One factor that adds difficulty to the process of laying out complex patterns using phase shift masking results in the direction where the width of the phase shift region is orthogonal to the edges between opposite phase regions Occurs because it has a significant effect on the image. If the width is too narrow, the line width of the resulting image may be widened. If it is too wide, the size of the phase shifter for a feature will begin to interfere with adjacent features in the layout. Furthermore, if adjacent features also use phase shift regions, undesirable phase competition may occur along the sides of the phase shift regions.

  Because of these and other complexities, applying phase shift masking techniques to complex designs requires improved approaches to designing phase shift masks and establishing new phase shift layout techniques.

US Pat. No. 5,858,580

"Alternative PSM design and flow from design to manufacturing" Wu et al., SAME, October 26, 2000

The present invention provides a method and system for manufacturing an alternating phase shift mask that uses multiple phase shift mask resolution levels for multiple build classes. In an embodiment, a method for processing a pattern defining a feature of a first and second feature class in a layer for a photolithographic mask defining the layer;
Defining a first layout dimension for a phase shift window pair for a first modeling resolution level and a second layout dimension for a phase shift window pair for a second modeling resolution level;
Using a first layout dimension for a phase shift window pair for the first modeling class, and using a second layout dimension for a phase shift window pair for the second modeling class. Laying out a plurality of phase shift window pairs;
Assigning first and second phase shift values to the phase shift windows in the plurality of phase shift window pairs.

  In some embodiments, the processing includes reading a layout file that identifies the dimensions of a feature in the pattern, and processing the layout file to identify features in the first and second build classes. , Including. The modeling in the first modeling class has a line segment having a first line width, for example, corresponding to a transistor gate, and the modeling in the second modeling class has a line segment having a second line width. For example, it corresponds to a narrow interconnection line for connecting to a small transistor gate, and the first line width is smaller than the second line width. Another example is both transistor gates to form two classes of transistors characterized by slightly different channel widths.

  In one embodiment of the invention, an apparatus is provided comprising means for performing the above process.

  The process of an embodiment results in fabricating a set of masks for defining layers of material in an integrated circuit or other workpiece. The set of masks comprises a first mask having a plurality of phase shift window pairs in the opaque field for defining the structure in the layer defined by the respective phase shift window. The first mask has a plurality of phase shift windows in the opaque field for defining the structure in the layer defined by the respective phase shift windows. The phase shift windows in the plurality of phase shift windows include first and second class windows, respectively, and the first class has a width dimension based on a first layout width; The second class has a width dimension based on a second layout width, and the first layout width is larger than the second layout width.

  The phase shift window has a width dimension based on the layout width when the phase shift window is laid out using other shapes after overlay, and the phase shift area overlaps with the other phase shift area. In some cases, the width of at least one segment of the phase shift area has a width equal to the layout width.

  The set of masks includes a second mask having a second opaque area and a transparent area, the second opaque area defining an interconnect structure within the layer and a plurality of phase shifts. The structure defined by the shift window is interconnected to prevent erasure of the structure defined by the phase shift window.

  In this way, the image exposed by the first class phase shift window pair has a smaller dimension than the image exposed by the second class phase shift window pair. The present invention can be extended to any number of phase shift window classes characterized by different widths or other characteristics, resulting in multiple resolutions having different resolutions. Provide an image of the modeling class.

  In some embodiments, the present invention is a method that includes processing a pattern defining exposed and unexposed areas for a lithographic mask defining a layer. Exposed areas in the pattern having dimensions smaller than the size of the first feature are identified as first class features. An exposed area in the pattern having a dimension that is smaller than the size of the second modeling and larger than the size of the first modeling is identified as a second class of modeling. A plurality of phase shift window pairs are laid out as described above for the first mask. A phase shift value is assigned to each of the first and second phase shift windows of the plurality of phase shift window pairs.

  According to another embodiment, the present invention provides instructions for performing a process for laying out a phase shift mask with multiple phase shift mask resolution levels associated with a plurality of modeling classes, as described above, and A data processing system that includes other resources is provided. In yet another embodiment, the present invention stores instructions for performing the process of laying out a phase shift mask with multiple phase shift mask resolution levels associated with a plurality of build classes as described above. An article of manufacture comprising a machine-readable storage medium is provided. In yet another embodiment, the invention includes a machine including instructions for performing a process of laying out a phase shift mask with multiple phase shift mask resolution levels involving multiple modeling classes, as described above. Has readable communication.

  The present invention provides a designer's feature of using phase shift masking with multiple phase shift resolution levels to produce integrated circuits or other workpieces with very fine features. Provide methods and tools for increased flexibility. Other aspects and advantages of the invention will be understood by reference to the drawings, detailed description, and claims.

4 is a flowchart of a layout process involving multiple phase shift mask resolution levels according to the present invention. FIG. 6 illustrates a conventional process for laying out phase shift window pairs for transistor gates or other build classes. FIG. 6 illustrates a conventional process for laying out phase shift window pairs for transistor gates or other build classes. FIG. 6 illustrates a conventional process for laying out phase shift window pairs for transistor gates or other build classes. FIG. 6 illustrates a conventional process for laying out phase shift window pairs for transistor gates or other build classes. FIG. 3 shows a process for laying out phase shift window pairs for modeling of modeling classes other than those shown in FIG. FIG. 3 shows a process for laying out phase shift window pairs for modeling of modeling classes other than those shown in FIG. FIG. 3 shows a process for laying out phase shift window pairs for modeling of modeling classes other than those shown in FIG. FIG. 3 shows a process for laying out phase shift window pairs for modeling of modeling classes other than those shown in FIG. FIG. 4 illustrates steps performed in laying out a plurality of modeling classes in a pattern according to an embodiment of the present invention. FIG. FIG. 4 illustrates steps performed in laying out a plurality of modeling classes in a pattern according to an embodiment of the present invention. FIG. FIG. 4 illustrates steps performed in laying out a plurality of modeling classes in a pattern according to an embodiment of the present invention. FIG. FIG. 4 illustrates steps performed in laying out a plurality of modeling classes in a pattern according to an embodiment of the present invention. FIG. FIG. 4 shows steps performed when laying out a plurality of modeling classes in one pattern according to another embodiment of the present invention. FIG. FIG. 4 shows steps performed when laying out a plurality of modeling classes in one pattern according to another embodiment of the present invention. FIG. FIG. 4 shows steps performed when laying out a plurality of modeling classes in one pattern according to another embodiment of the present invention. FIG. FIG. 4 shows steps performed when laying out a plurality of modeling classes in one pattern according to another embodiment of the present invention. FIG. 1 illustrates a data processing system for performing a process of laying out a plurality of build classes in a pattern, such as a pattern for a photolithographic mask used for a layer in an integrated circuit or other workpiece.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows the layout of a phase shift mask using an alternating phase shift mask with multiple phase shift resolution levels involving multiple modeling classes, producing a complementary mask, such a mask. Fig. 3 illustrates a process performed by a computer system and a manufacturing system for printing and manufacturing an integrated circuit.

  This process begins in this example by reading a layout file that defines the complex layers of the integrated circuit (step 10). For example, one such complex layer may comprise a polysilicon interconnect layer that includes a transistor gate structure. Next, the process identifies a first set of features that are members of the first feature class. For example, a feature having a dimension smaller than the first specific value is identified as a member of a first feature class, such as a transistor gate (step 11). A second set of features to be exposed in the second feature class is then identified. For example, a feature having a dimension smaller than a second specific value that is greater than a first specific value that characterizes the first modeling class is identified (step 12). A first and second set of shift window pairs composed of phase shift windows having first and second layout dimensions are laid out for the first and second sets of features (step 13). The first and second sets of shift window dimensions are characterized by varying the layout width of the dimensions orthogonal to the edges of the phase transition. Other phase shift window layout dimensions to provide multiple resolution levels for various build classes, such as the width of the opaque area along the phase transition between the paired phase shift windows Can be changed. Next, phase shift values for the phase shift window pairs are assigned or “colored” (step 14), the first window of each pair having a phase shift of θ degrees, and the second of each pair The window will have a phase shift of (180 + θ) degrees, where θ is nominally zero degrees in some embodiments. Other optical proximity correction techniques or other mask layout processes are performed to complete the phase shift mask layout process, as is known in the art (step 15). At this point, a machine-readable layout file is created that includes a phase shift structure for the multiple modeling class. A complementary binary mask is laid out, whereby the features exposed using the opaque field shift mask are interconnected within the layer (step 16). In a subsequent step, a mask is printed or otherwise manufactured (step 17) for use in exposing a layer of material during the manufacture of a workpiece such as a large circuit. Finally, in a preferred system, an integrated circuit is fabricated using a phase shift mask (step 18).

  FIGS. 2A through 2D show the layout of a phase shift mask for a first class build, and in this example, a first such as a width defining a channel length for a transistor of 0.12 microns or less. For transistor gates having dimensions smaller than one specific value. FIG. 2A is an appearance of a layout file that defines modeling. In this way, the layers on the integrated circuit are defined within box 100. The transistor gate is defined by polysilicon line 101. Implanted region 102 provides the source and drain of the transistor and creates the active region of the transistor under the transistor gate defined by line 101. In accordance with the present invention, the phase shift window will be laid out to expose the area that will define line 101 within the active area. Thus, in FIG. 2B, the region 105 defining the transistor gate is identified on the active region of the transistor. FIG. 2C shows phase shift windows 106 and 107 laid out adjacent to region 105. The phase shift windows 106 and 107 have a length L parallel to the shaping 105 to be defined. In this class of features, the phase shift windows 106 and 107 have a layout width W1, which is the edge of the phase shift windows 106 and 107 where phase competition may cause exposure of the region 105. It is orthogonal to. FIG. 2D shows the phase shift windows 106 and 107 after the phase shift windows 106 and 107 have been “colored”, that is, after being assigned phase shift characters of 0 and 180 degrees, respectively. Phase shift windows 106 and 107 are laid out in opaque field 108 to define a phase shift mask. Although not shown, complementary binary masks are made to provide interconnects and other necessary structures in the device layers.

  FIGS. 3A to 3D show the layout of a phase shift mask for a second class of shaping, in this example a first specific value characterizing the width of the transistor gate described with reference to FIGS. 2A to 2D. A narrow interconnect having dimensions smaller than a larger second specific value. For example, when the first specific value is 0.12 microns or less, the second specific value is 0.16 microns or less. Thus, FIG. 3A shows an integrated circuit layer 120 having interconnect features 121. Interconnect modeling 121 is defined to have a width less than the second specific value. Therefore, this is a limit shaping for the layout of the phase shift mask for this second class shaping. Thus, the limit shaping 122 is defined in FIG. 3B. FIG. 3C shows the layout of the phase shift windows 123 and 124 on opposite sides of the build 122. In this example, the phase shift windows 123 and 124 have a layout width W2 that is narrower than the layout width used in the sequence shown in FIG. 2C. FIG. 3D shows the phase shift regions 123 and 124 after the relative phase shift values 0 and 180 degrees have been assigned to the phase shift regions 123 and 124, respectively. The phase shift areas 123 and 124 are laid out in the opaque field 125. Complementary binary masks (not shown) are used for interconnects in layers and other features that are independent of phase shift.

  Thus, as can be seen in FIGS. 2A to 2D and FIGS. 3A to 3D, multiple classes of phase shift modeling are defined. As a result, the width of the exposed pattern is based on the layout widths W1 and W2 of the phase shift window. According to the present invention, a single phase shift mask in which a plurality of modeling classes are accommodated using phase shift window pairs having different layout widths is realized. In this way, a shape with a wide dimension that can be realized with a narrow phase shift window, and a single shape with a shape that must be realized with a narrow phase shift window with a wide phase shift window. Can be combined on one mask. Furthermore, the coloration of the combined shift areas is simplified on systems that rely on single wide or single class phase shift shaping.

  4A to 4D show the layout of a pattern having a plurality of modeling classes on a single mask. FIG. 4A shows an integrated circuit layer 150 having a polysilicon gate feature 140 and a polysilicon interconnect feature that includes segments 141 and 142. Implant 151 is shown in a shape representing the source and drain regions of a transistor having an active channel region under gate shape 140. In the first step of the process shown in FIG. 4B, the gate cells of the layout are identified and the phase shift cells 153 and 154 are laid out in a manner that defines the gate region 152 using the layout width defined for the first build class. Is done. In the next step shown in FIG. 4C, a critical shaped cell is identified that is defined as an interconnect structure having a width that is less than a specific value but greater than the gate width. Phase shift cells 156 and 157 overlay the phase shift cells 153 and 154 using the layout width defined for the second build class and are laid out along the sides of build 155. In this example, the layout width for the first modeling class is larger than the layout width for the second modeling class. The completed phase shift window has a segment having a width based on the layout width for both modeling classes in the final window shape.

  In FIG. 4D, phase shift windows 160 and 162 are colored with phase shift angles of 0 degrees and 180 degrees, respectively, as shown. A phase shift window colored in this way is realized in the opaque field 161. The phase shift windows achieve phase transitions with opaque materials such as chrome that are adjacent to each other and that define a spacing along the phase transition between the windows. Usually, the transition from the 0 degree phase window to the 180 degree phase window is in the middle of the opaque band between the windows. However, opaque bands between windows allow other layouts.

  A complementary binary mask (not shown) is added for use to implement the workpiece layer, as discussed above. In this way, phase shift cells 156 and 157 are implemented in a manner that does not prevent region 142 from taking the width required for layout. Similarly, the use of narrow phase shift windows 156-157 simplifies the overall integrated circuit layout by reducing the opportunity for phase contention with adjacent phase shift cells.

  FIGS. 5A-5D show the layout of a pattern having multiple build classes on a single mask, according to an alternative process flow. FIG. 5A shows a layer 150 as in FIG. 4A of an integrated circuit having a polysilicon gate feature 140 and a polysilicon interconnect feature that includes segments 141 and 142. Implant 151 is shown in a shape representing the source and drain regions of a transistor having an active channel region under gate shape 140. In the first step of the alternative process shown in FIG. 5B, layout gate cells 152 and layout limit interconnect cells 155 are identified. In the next step shown in FIG. 5C, the combined phase shift cells 158 and 159 for both the first class of fabrication (gate) and the second class of fabrication (limit width interconnect lines) are laid out. As a result, the layout is basically the same as that of the combination type cell shown in FIG. 4C. In the final step shown in FIG. 5D, as shown, phase shift windows 160 and 162 are colored with respective phase shift angles of 0 degrees and 180 degrees. A phase shift cell colored in this way is realized in the opaque field 161. A complementary binary mask (not shown) is added for use to implement the workpiece layer, as discussed above.

  In the opaque field 161 shown in FIGS. 4D and 5D, opaque features are laid out between the phase shift regions. The width of the opaque feature between the phase shift regions can be adjusted in addition to adjusting the width of the phase shift window itself. In this way, the width of the phase shift window and the width of the opaque feature between the phase shift windows can be manipulated to define a plurality of build classes for the shift mask layout.

  Laying out phase shift areas on complex masks can be done by using overlapping phase shift areas and layers such as lines cut at an angle to overlay the layout dimensions of the phase shift areas. Resolving other shaped shapes. The resulting mask will have a phase shift window with a complex polygonal shape rather than a simple rectangle. However, in an embodiment of the invention, the phase shift windows for the first and second modeling classes have width dimensions based on different layout widths. The phase shift window has a width dimension based on the layout width when the phase shift window is laid out using other shapes after overlay, and the phase shift area overlaps with the other phase shift area. In some cases, the width of at least one segment of the phase shift area has a width equal to the layout width.

  Generating a phase shift mask for a complex structure is not a trivial processing issue. FIG. 6 shows a data processing system for such a task. The machine 250 of FIG. 6 includes a processor 252 connected to receive data representing a user signal from a user input circuit 254 and to provide data defining an image to a display 256. The processor 252 is further connected to access mask and layer layout data 258 that defines the mask layout being created and the layout for the layer of material to be exposed using the mask. The processor 252 is further connected to receive instruction data 260 for displaying instructions through the instruction input circuit 262, which is shown in the figure as a memory 264, storage medium access device 266 or network 268 as shown. The command received from the connection to can be provided.

  In executing the command displayed by the instruction data 260, the processor 252 uses the layout data 258 to provide the display 256 with data defining the mask layout and, optionally, the mask layout image. , Display a sample of the layout.

  As described above, FIG. 6 illustrates three possible sources from which the instruction input circuit 262 can receive data representing instructions: a memory 264, a storage medium access device 266, and a network 268.

  The memory 264 may be any conventional memory in the machine 250, including random access memory (RAM) or read only memory (ROM), and any type of peripheral or remote memory device.

  The storage media access device 266 may be a drive or other suitable device or circuit for accessing the storage media 270, such as a set of one or more tapes, diskettes, or flexible disks. Such as a magnetic medium, an optical medium such as a set of one or more CD-ROMs, or any suitable medium for storing data. The storage medium 270 may be part of the machine 250, part of a server or other peripheral or remote memory device, or a software product. In any case, storage medium 270 is an article of manufacture that can be used with machine 250. The data units can be located on the storage medium 270 so that the storage medium access device 266 can access the data units and supply them sequentially to the processor 252 through the instruction input circuit 262. When supplied in sequence, the data units form instruction data 260 and display the instructions as shown.

  The network 268 can supply the instruction data 260 received as a communication from the machine 280. The processor 282 of the machine 280 can establish a connection with the processor 252 via the network connection circuit 284 and the command input circuit 262 over the network 268. Either processor can initiate a connection and the connection may be established with any suitable protocol. Then, the processor 282 can access the instruction data stored in the memory 286 and transmit the instruction data to the processor 252 via the network 268, so that the processor 252 receives the instruction data 260 from the network 268. be able to. The processor 252 can then store the instruction data 260 somewhere in the memory 264 and execute it.

  The resulting layout data is stored in a machine readable form or displayed in communication with a remote system.

  In this example, automatic assignment of phase shift regions and the addition of optical proximity correction shaping as described above are provided to facilitate processing. For example, in a data processing system as shown in FIG. 6, generation of a phase shift mask layout by this process executed using a design rule check programming language (for example, a Vampier design rule checker provided by Cadence Design Systems). The three stages in include the definition of the input layer, the generation of the output layer, and the coloring of the phase shift region.

  Utilizing the design rule checker, all exposed features (i.e., lines) of the input layout that have a size smaller than the minimum feature size, or that have features of a feature class that is implemented according to the present invention using multiple phase shift resolution levels. ) Can be identified. In some embodiments, different minimum build dimensions are applied to multiple build classes. In this way, the minimum shaped structure can be identified by subtracting a little more than 1/2 of the smallest shaped dimension for the line from the original size input structure. As a result, all structures having dimensions smaller than the minimum dimension are removed. The remaining structure can then be reconstructed by adding back a little more than half of the smallest dimension. The smallest dimension structure can then be identified by taking the original input structure and subtracting all the structures obtained in the reconstruction step. This process can be characterized as performing a size down operation to remove small dimensional features and then performing a size up operation on the remaining edges to produce a calculated layout. Next, small dimension features are identified by performing an “AND NOT” operation between the AND NOT of the original layout and the calculated layout.

  The phase shift area, if simple, copies the input structure of each build class, adjusts the resulting polygon width to the desired layout width for each build class, and corresponds to the phase shift window pair It is formed by arranging a polygon at a modeling position. Phase “coloring” can be applied automatically or manually to the resulting phase shift window pairs so that the 0 and 180 degree regions are laid out correctly.

  The above simple example provides an alternative process flow for laying out phase shift windows for multiple resolution levels based on the layout width of the phase shift window. This process can be easily extended to complex layouts with more than three resolution levels to meet the needs of specific layout problems. A very fine grade in resolution can be achieved by fine tuning the width of the phase shift window and the spacing between them.

  In summary, using the multi-resolution class of the present invention to define alternating phase shift masks used to fabricate integrated circuits and other finely shaped workpieces, the layout features can be crossed over. Excellent control and almost no problems due to phase competition.

  The foregoing descriptions of various embodiments of the present invention have been presented for purposes of illustration and description. The above description is not intended to limit the invention to the precise form disclosed. Many modifications can be made and equivalent structures can be derived, as will be apparent to those skilled in the art.

Claims (7)

In a set of masks for defining a layer of material in an integrated circuit,
A first mask having a plurality of phase shift window pairs in an opaque field for defining a structure in a layer defined by each phase shift window, the phase shift in the plurality of phase shift windows being The transfer window includes respective first and second class windows, wherein the first class has a width dimension based on a first layout width, and the second class has a second layout width. A first mask having a width dimension based on, wherein the first layout width is greater than the second layout width;
A second mask having a second opaque area and a transparent area for interconnecting structures defined by the plurality of phase shift windows and preventing erasure of the structures defined by the phase shift windows And a second mask defining an interconnect structure in the layer.   The set of masks according to claim 1, wherein the layer comprises polysilicon.   Assigning a phase shift value to a pair of windows in the first and second class windows, wherein one of the pair of windows has a phase shift of θ degrees, 2. The set of masks according to claim 1, wherein the other of the windows has a phase shift of (180 + θ) degrees.   4. The set of masks of claim 3, wherein the pair of windows further includes an opaque area disposed between the one window and the other window.   The opaque area has a first width between a pair of windows of the first class window and a second width between a pair of windows of the second class window. The set of masks according to claim 3.   The modeling in the first modeling class is a line segment corresponding to an interconnect line having a first width, and the modeling in the second modeling class is a line segment corresponding to a gate having a second width. The set of masks according to claim 1.   The set of masks according to claim 1, wherein the second mask comprises a binary mask.

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