JP2009170839A - Method for forming mask pattern data and method for manufacturing semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for forming mask pattern data for easily and quickly executing mask data processing for flare compensation without losing pattern dimension precision, and to provide a method for manufacturing a semiconductor apparatus. <P>SOLUTION: A pattern to be corrected is a gate pattern including a wiring section and an active gate section formed on a diffusion layer. The method for forming a mask pattern data includes: extracting a diffusion pattern from design mask pattern data; widening the width of the extracted diffusion layer pattern only by predetermined width Δw to generate a second diffusion layer pattern; extracting a gate pattern existing on the second diffusion layer pattern to generate an extended second active gate section; and performing uniform quantity correction to individual second active gate section. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing process, and in particular, mask pattern data for correcting a flare effect with a mask pattern and forming a fine and highly accurate pattern during wafer exposure such as EUV (Extreme Ultraviolet) lithography. The present invention relates to a manufacturing method and a manufacturing method of a semiconductor device.

  Conventionally, optical lithography such as i-line lithography with a wavelength of 365 nm, KrF lithography with 248 nm, ArF lithography with 193 nm has been used as a lithography technique used in the manufacturing process of a semiconductor device. Recently, since ArF lithography can no longer satisfy the resolution requirement, immersion lithography with higher resolution has been actively studied. However, even with this immersion lithography, resolution of 45 nm at a half pitch is the limit. Therefore, EUV having a wavelength of 13.5 nm has been actively studied as a lithography technique with a half pitch of 32 nm.

  As one of the problems of EUV lithography, there is a problem of lens flare. In EUV lithography, the exposure wavelength is as short as 13.5 nm. Due to the relationship between light absorption and refractive index, projection exposure is performed using a reflective lens system instead of a refractive lens system. The exposure light is scattered by the influence of the very fine surface roughness of the reflection lens composed of the multilayer mirror, and flare which is stray light is generated. Due to this flare, exposure fogging occurs and the pattern dimension changes according to the aperture ratio around the pattern. This is the problem of lens flare. Depending on the roughness of the resist and lens, a dimensional change of 0.7 nm may occur every time the aperture ratio increases by 1%.

  In order to solve the lens flare problem, a flare correction technique has been developed in which a pattern width on a mask is adjusted in accordance with an aperture ratio of a peripheral pattern to obtain a pattern with a desired dimensional accuracy. This flare correction technique is described in Patent Documents 1 and 2 listed below.

In this flare correction method, the stray light amount coming from the surrounding area is integrated into the target pattern, and correction is performed by applying a dimensional bias to the mask pattern corresponding to the increased light amount. That is, as shown in FIG. 2, the exposure area is divided into a plurality of calculation mesh areas, and the surrounding area of the target pattern, for example, (α _{i + l, j + m} , δ _{i + l, j + m} ) includes the target pattern. The amount of light (flare) given to the region (α _{i, j} , δ _{i, j} ) is obtained, and the calculation mesh region (α _{i, j} , δ _{i, j} ) is extended over each calculation mesh region around the target pattern. Integrally calculate the amount of light given to.

In this way, on the basis of the case where there is no flare, an increase in the amount of light given to the calculation mesh region (α _{i, j} , δ _{i, j} ) when there is a flare is obtained, and a desired value is obtained under the increased amount of light. In order to obtain a dimension, a dimension bias to the target pattern, that is, a dimension correction corresponding to the increase in the amount of light is performed on the mask pattern on the target calculation mesh region.

  In addition, as a method of dividing the calculation mesh area, there are a method in which the exposure area is a uniformly spaced mesh, a method in which the mesh interval is narrow in the vicinity of the target pattern, and the calculation amount is reduced as a wide mesh interval above a certain distance. Has been proposed. In addition, a method for correcting the aperture density of a pattern has been proposed in calculating the light quantity from a certain peripheral mesh region.

US Pat. No. 6,815,129 JP 2004-126486 A

  When the conventional flare correction method is applied to a gate pattern consisting of a wiring portion and an active gate portion, the wiring portion and the active gate portion are uniformly corrected although the required dimensional accuracy is different. It has become necessary to set a fine calculation mesh in accordance with the active gate portion having high required dimensional accuracy.

  An example of this will be described with reference to FIG. 3 showing a pattern layout diagram. In the figure, reference numeral 101 denotes a gate layer pattern, reference numeral 111 denotes a diffusion layer, and reference numeral 121 denotes a calculation mesh for obtaining an effect associated with flare.

  The gate pattern is required to have high dimensional accuracy, but the gate pattern disposed on the diffusion layer, that is, a so-called active gate pattern portion, particularly requires high dimensional accuracy. In order to perform transistor operation stably, high dimensional accuracy of 5% or 10% is required. On the other hand, the pattern of the gate layer on the field outside the diffusion layer functions as a wiring, and the dimensional accuracy is not required as much as the active gate pattern portion. In some cases, it is acceptable if there is no disconnection, contact with the adjacent wiring, or short circuit. Therefore, as shown in FIG. 3, the gate layer pattern 101 has a place 11 where high dimensional accuracy is required and places 12, 13 which are not so required.

  When a calculation mesh is set on the active gate pattern portion as in the place 11 in FIG. 3, the mask dimension after flare correction may change due to a difference in corrected exposure amount between the calculation mesh regions. This is because the calculation mesh is relatively coarse and is discretely processed. In such local situations, this is not the case with flare. Therefore, due to the roughness of the calculation mesh, there arises a problem that the dimensional accuracy in the most important active gate pattern portion is not sufficient.

  As a method for avoiding this problem, conventionally, the calculation mesh interval has been narrowed. This increases the amount of calculation and data over the entire area, increases the EDA processing time, requires a large-capacity calculation processing system, and is costly. Also, the turn from semiconductor device design to mass production. There is a problem that a turn around time (TAT) increases.

  On the other hand, although the dimensional accuracy is not required so high in the wiring portions at the locations 12 and 13 in FIG.

  An object of the present invention is to provide a mask pattern data method and a semiconductor device manufacturing method capable of performing flare compensation mask data processing easily and at high speed without impairing pattern dimensional accuracy.

  According to an embodiment of the present invention, the pattern whose dimension is to be corrected is a gate pattern including an active gate portion formed on a wiring portion and a diffusion layer, and for each active gate portion, calculation is performed. The mask dimension correction amount corresponding to the amount of light coming from the peripheral area in the mesh area is made uniform.

  According to another embodiment of the present invention, the pattern to be corrected is a gate pattern including a wiring portion and an active gate portion formed on the diffusion layer, and the diffusion layer pattern is extracted from the design mask pattern data. Then, the extracted diffusion layer pattern is widened by a predetermined width Δw to generate a second diffusion layer pattern. Then, a gate pattern existing on the second diffusion layer pattern is extracted to generate an extended second active gate portion. A uniform amount of correction is performed for each second active gate portion.

  According to this embodiment, the mask data processing for flare compensation can be performed easily and at high speed without impairing the pattern dimension accuracy. As a result, the turnaround time from the design of the semiconductor device to mass production can be reduced.

Embodiment 1 FIG.
A first embodiment of the present invention will be described with reference to FIGS. 1, 4, 5 and 6. FIG. 1 is a flowchart showing an example of a mask pattern data creation method according to the present invention. In this embodiment, the mask dimension correction target pattern is a gate pattern including a wiring portion and an active gate portion formed on the diffusion layer.

  First, in step S2, the exposure area is divided into a plurality of calculation mesh areas. Next, in step S2a, a diffusion layer pattern is extracted from the design mask pattern data.

  Next, in step S3, the extracted diffusion layer pattern is widened by a predetermined width Δw to generate a second diffusion layer pattern widened by graphic calculation. This is shown in FIG.

  FIG. 4A shows an example of an original pattern composed of the diffusion layer pattern 111 and the gate layer pattern 101, that is, a design stage pattern. Subsequently, as shown in FIG. 4B, in step S3, the diffusion layer pattern 111 is widened by a predetermined width Δw to generate a second diffusion layer pattern 112. At this time, the widening width Δw depends on the resist process to be applied, exposure illumination conditions, and the like, but is preferably set to 1.5 to 3.0 times the minimum gate length created in the lithography stage.

  Next, in step S4, a gate pattern existing on the second diffusion layer pattern is extracted to generate an extended second active gate portion. For example, as shown in FIG. 4C, the expanded second active gate portion 102 that is a common portion between the widened second diffusion layer pattern 112 and the gate layer pattern 101 is extracted by graphic calculation. Here, the gate layer pattern 101 other than the expanded second active gate portion 102 is defined as a gate wiring 106.

  Next, in step S5, as shown in FIG. 4D, it is determined whether or not the expanded second active gate unit 102 intersects the grid 121 that defines the boundary of the calculation mesh region divided in step S2. judge. If it intersects with the grid 121, the process proceeds to step S 6, where the simple average correction amount ΣDi / N of the exposure correction amount Di associated with the flare assigned to each mesh region that the second active gate unit 102 straddles. Is applied to the second active gate portion 102. Here, N is the number of calculation mesh regions straddling.

  When not straddling, the process proceeds to step S7, and the exposure correction amount D associated with the flare assigned to the corresponding mesh region is applied to the second active gate unit 102.

  Subsequently, in step S8, with respect to the gate layer pattern 101 other than the expanded second active gate portion 102, that is, the gate wiring 106, the gate wiring pattern is divided for each mesh region, An exposure correction amount D associated with the flare assigned to the corresponding mesh area is applied.

  Next, in step S9, mask pattern dimension correction of the corresponding pattern portion is performed based on the corrected exposure amount accompanying the assigned flare.

  FIG. 4D illustrates a case where the expanded second active gate unit 102 intersects the grid 121 that defines the boundary of the calculation mesh. The mask pattern 102a corresponding to the second active gate portion 102 is uniformly subjected to a mask dimension bias obtained from the exposure correction amount due to the average flare in the upper and lower two calculation mesh regions. The gate wiring patterns 106a and 106b divided up and down by the grid 121 are subjected to mask dimension bias obtained from the exposure correction amount caused by the flare belonging to each calculation mesh region.

  Thus, by expanding the diffusion layer pattern and expanding the active gate portion existing on the diffusion layer, the dimensional uniformity of the gate pattern formed on the diffusion layer can be improved. That is, as a result of dividing the mask bias and dividing the pattern discretely, it is possible to prevent the influence of the pattern step generated at the boundary with the gate wiring portion from affecting the active gate portion on the diffusion layer. It can be seen that this extended portion functions as a buffer region for the so-called step difference.

  An application example of the present invention to a circuit pattern is shown in FIG. The pattern of the gate layer is divided into extended second active gate portions 103, 104, and 105 existing on the diffusion layer, and the other portions are divided as gate wirings 106. Here, 111 indicates a diffusion layer pattern, and 121 indicates a grid that defines the boundary of the calculation mesh.

  In FIG. 5, the 2nd active gate part 103 shows the example of the pattern settled in the inside of a calculation mesh area | region. The second active gate unit 104 shows a pattern example straddling two calculation mesh regions. The second active gate unit 105 shows an example of a pattern straddling four calculation mesh regions.

  For reference, FIG. 6 shows a pattern in which the extended second active gate portions 103, 104, and 105 are extracted and their relationship is clearly shown. The second active gate portion 104 is uniformly subjected to a mask dimension bias obtained from the exposure correction amount caused by the average flare in the two calculation mesh regions. Further, the second active gate portion 105 is uniformly subjected to a mask dimension bias obtained from the exposure correction amount caused by the average flare of the four calculation mesh regions. In the second active gate portion extended in this way, the mask bias correction is uniform from the viewpoint of flare correction.

  This technology is a correction technology that responds to flare-induced dimensional changes. Pattern proximity effect correction due to a kind of interference effect, so-called OPC (Optical Proximity Correction), and dimensional correction caused by etching are separately performed. Will be corrected.

  The mask pattern data generation method according to the present embodiment can be coded as a computer program, and executes various recordings (eg, RAM, ROM, hard disk drive, optical disk drive, etc.) and various calculations. It can be easily implemented on a computer equipped with a processor.

  In this way, when trying to obtain the same dimensional accuracy as this method by the conventional method, the calculation mesh needs to be narrowed to less than half, and the correction calculation amount and the correction data amount that increase in proportion to the square of the calculation mesh width Will increase significantly. As a result, the turnaround time (TAT) required for generating the correction mask pattern also increases four times. On the other hand, in the present embodiment, mask data processing for flare compensation can be performed simply and at high speed without reducing the calculation mesh width. Accordingly, the turnaround time is improved by a factor of 4, and the correction calculation amount and the correction data amount are reduced to ¼, so that mask creation becomes easy.

Embodiment 2. FIG.
In the present embodiment, for example, a mask pattern is created on an exposure mask for EUV lithography using the mask pattern data creation method described in the first embodiment, and then a semiconductor wafer is fabricated using the created mask pattern. The semiconductor memory device is manufactured by exposing. Here, an example applied to a DRAM is shown, but the present invention is not limited to this and can be applied to a flash memory.

  As shown in the device configuration diagram of FIG. 7, the memory dealt with here has a memory cell array unit 201 composed of a matrix of memory cells for storing bit information, and a function of directly writing and reading data to and from the memory cells. The memory mat direct peripheral circuit unit 202 and the peripheral circuit unit 203 responsible for data calculation, external input / output, power supply, and the like.

  In the memory semiconductor device, it is required to increase the memory density per unit area as much as possible to increase the bit cost. Therefore, the memory cell array unit 201 has the finest pattern with the highest integration degree. . However, since the same pattern is regularly arranged in the memory cell array unit 201, pattern correction for flare correction is relatively easy and can be handled by manual correction. In addition, since the core memory cell array unit 201 can be used for product development, it can be sufficiently recovered even when a load is applied to EDA (Electrical Design Automation). Therefore, the memory cell array unit 201 may correct the mask pattern by a conventional method without using this method.

  As for the memory mat direct peripheral circuit unit 202, patterns having relatively the same density are used in the development of the products, and the adjacent pattern group is the fixed memory mat direct peripheral circuit unit 202. For this reason, this pattern correction is relatively easy, and there are few changes. Therefore, the mask pattern may be corrected by the conventional method without using this method.

  On the other hand, the peripheral circuit unit 203 is a place where the pattern changes greatly when the product is developed. In order to facilitate the product development, it is required to reduce the turnaround time for mask pattern correction. When the calculation mesh is coarse in the conventional method, the dimensional accuracy of the active gate portion cannot be ensured although it is a peripheral circuit portion. However, when the present method shown in the first embodiment is applied, a desired mesh is obtained even though the calculation mesh is coarse. Dimensional accuracy can be obtained. The high-speed generation of mask pattern data is extremely effective in reducing the turnaround time from pattern design to semiconductor device manufacturing, and can shorten the time to market of the manufactured semiconductor device and increase the added value of the semiconductor device. . In particular, it is possible to reduce the turnaround time for mask pattern correction at the neck when developing the product, which is very effective.

  As described above, according to the present embodiment, mask data processing for flare compensation of a semiconductor memory device can be performed easily and at a high speed with a compact mask pattern data amount without sacrificing dimensional accuracy as compared with the conventional method. Pattern data can be generated.

  The present invention is extremely useful industrially in that a semiconductor device including a fine and highly accurate pattern can be manufactured with high production efficiency.

It is a flowchart which shows an example of the mask pattern data creation method concerning this invention. It is explanatory drawing which showed the calculation concept of the conventional flare correction. It is a top view which shows an example of the pattern layout explaining the problem of the conventional method. 4 (a) to 4 (d) are plan views showing an example of mask pattern dimension correction processing according to the present invention. It is a top view which shows the example of application to a circuit pattern. In FIG. 5, it is a top view which shows only the extended 2nd active gate part 103,104,105. It is a top view which shows the structural example of the semiconductor memory device which can apply this invention.

Explanation of symbols

101 gate pattern,
102, 103, 104, 105 extended second active gate part,
102a corresponding mask pattern,
106 gate wiring, 106a, 106b gate wiring pattern,
111 diffusion layer pattern, 112 widened second diffusion layer pattern,
121 grid, 201 memory cell array,
202 Memory mat direct peripheral circuit section, 203 Peripheral circuit section.

Claims (5)

Mask pattern data for creating mask pattern data that corrects the pattern on the mask so that the desired pattern is projected and exposed when the pattern on the mask is projected and exposed onto the wafer via the projection optical system. In the method
Dividing the exposure area into a plurality of calculation mesh areas to perform the correction calculation;
Calculating the amount of light coming from the surrounding area on each calculation mesh area;
A step of performing mask pattern dimension correction in accordance with the amount of light coming from the peripheral area in each mesh area,
The mask pattern dimension correction target pattern is a gate pattern including a wiring part and an active gate part formed on a diffusion layer,
A mask pattern data generation method characterized in that the mask dimension correction amount corresponding to the amount of light coming from the peripheral area in the calculation mesh area is uniform for each active gate portion. Mask pattern data for creating mask pattern data that corrects the pattern on the mask so that the desired pattern is projected and exposed when the pattern on the mask is projected and exposed onto the wafer via the projection optical system. In the method
The mask dimension correction target pattern is a gate pattern including a wiring part and an active gate part formed on the diffusion layer,
Extracting a diffusion layer pattern from design mask pattern data;
Widening the extracted diffusion layer pattern by a predetermined width Δw to generate a second diffusion layer pattern;
Extracting a gate pattern existing on the second diffusion layer pattern to generate an expanded second active gate portion;
Dividing the exposure area into a plurality of calculation mesh areas to perform the correction;
Calculating the amount of light coming from the surrounding area on each calculation mesh area;
A step of performing mask pattern dimension correction in accordance with the amount of light coming from the peripheral area in each mesh area,
A mask pattern data generation method, wherein a uniform amount of correction is performed on each of the second active gate portions.   When the active gate section intersects the boundary of the calculation mesh area, for each calculation mesh area straddled by the active gate section, the light intensity correction amount is a simple average of the light amount correction amounts coming from the surrounding areas. 3. The mask pattern data generation method according to claim 1, wherein the mask dimension correction amount is set in accordance with the mask pattern correction amount. A step of creating a mask pattern using the mask pattern data creation method according to any one of claims 1 to 3,
And a step of exposing the semiconductor wafer using the created mask pattern.   5. The method of manufacturing a semiconductor device according to claim 4, wherein a peripheral circuit of the semiconductor memory device is manufactured by exposing the semiconductor wafer using the generated mask pattern.