JP2009170544A - Semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor apparatus forming the surface of an SOG layer flatly. <P>SOLUTION: On an interlayer dielectric 2, wiring 3 is formed in a prescribed pattern. On the interlayer dielectric 2 and the wiring 3, an SiOC film 7 is formed along their surfaces. On the SiOC film 7, an SOG layer 8 is formed. The SOG layer 8 allows a part formed on the wiring 3 in the SiOC film 7 to be exposed and has a surface flush with that of the exposed SiOC film 7. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device having a multilayer wiring structure.

For example, a highly integrated LSI employs a so-called multilayer wiring structure in which a plurality of wiring layers are stacked on a semiconductor substrate.
5A to 5F are schematic sectional views showing a method of manufacturing a semiconductor device having a multilayer wiring structure in the order of steps.
First, an interlayer insulating film 101 is formed on a semiconductor substrate (not shown) (for example, a silicon substrate). 5A, a TiN (titanium nitride) layer 102, an Al (aluminum) alloy layer 103, and a TiN layer 104 are stacked in this order from the semiconductor substrate side on the interlayer insulating film 101.

  Next, the TiN layer 102, the Al alloy layer 103, and the TiN layer 104 are selectively etched, whereby the wiring 105 is formed in a predetermined pattern as shown in FIG. 5B. The wiring 105 has a laminated structure in which a main wiring layer (Al alloy layer 103) made of Al alloy is sandwiched between an antireflection film (TiN layer 104) made of TiN and a barrier film (TiN layer 102).

Thereafter, as shown in FIG. 5C, a base film 106 made of SiO ₂ (silicon oxide) is formed on the interlayer insulating film 101 and the wiring 105. The base film 106 has a film thickness smaller than the interval between the wirings 105 and covers the surfaces of the interlayer insulating film 101 and the wirings 105. Thereby, a recess 110 partitioned by the base film 106 is formed between the wirings 105. That is, the base film 106 formed on the side surfaces of the opposing wiring 105 forms the side surface of the recess 110, and the base film 106 formed on the surface of the interlayer insulating film 101 between the wirings 105 forms the bottom surface of the recess 110.

Next, as shown in FIG. 5D, an SOG layer 107 made of an organic SOG material (for example, methylsilsesquioxane: MSQ) is spin-coated on the base film 106. The SOG layer 107 is formed to a thickness that fills the recess 110 defined by the base film 106 and covers a portion of the base film 106 formed on the wiring 105.
Thereafter, as shown in FIG. 5E, the portion formed on the wiring 105 in the SOG layer 107 is removed by etch back, and the surface of the base film 106 is exposed on the wiring 105.

Then, the interlayer insulating film 109 is stacked on the SOG layer 107 and the base film 106, whereby the semiconductor device shown in FIG. 5F is obtained.
JP-A-7-106328

SiO ₂ that is a material of the base film 106 contains a large amount of O (oxygen). Therefore, when the base film 106 exposed from the SOG layer 107 is exposed to an etching gas during the etch back process (see FIG. 5E), O contained in the base film 106 is mixed into the etching gas. Since O mixed in the etching gas increases the etching rate of the SOG layer 107, the portion around the portion where the base film 106 is exposed (the portion formed on the wiring 105 in the base film) is more than the other portions. Etching of the SOG layer 107 proceeds. As a result, as shown in FIG. 5E, a recess 108 is formed in the SOG layer 107 in the direction from the surface thereof toward the semiconductor substrate.

In particular, in the portion where the wirings 105 are dense, the exposed area of the base film 106 increases, and the amount of O mixed in the etching gas also increases. Therefore, the increase in the etching rate of the SOG layer 107 is particularly large in the portion where the wirings 105 are densely packed, so that the depth of the recess 108 generated in the SOG layer 107 is increased.
If such a dent 108 is generated, the flatness of the surface of the interlayer insulating film 109 is impaired as shown in FIG. 5F. Therefore, when a wiring material film is formed on the entire surface of the interlayer insulating film 109 and this is partially removed by etching to obtain an upper wiring pattern on the interlayer insulating film 109, the wiring material film is undesirably etched. There is a possibility that the remaining may occur, resulting in a problem of short circuit between wirings. Further, in the photolithography process when forming a via hole in the interlayer insulating film 109 or when forming an upper layer wiring on the interlayer insulating film 109, the depth of focus is not fixed, and so-called focus failure may occur.

  Accordingly, an object of the present invention is to provide a semiconductor device capable of forming the surface of the SOG layer flat.

  In order to achieve the above object, an invention according to claim 1 includes an interlayer insulating film, a wiring formed in a predetermined pattern on the interlayer insulating film, and the interlayer insulating film and the wiring on the surface thereof. An SOG film formed on the SiOC film, exposing a portion of the SiOC film formed on the wiring, and having a surface flush with the exposed surface of the SiOC film. A semiconductor device comprising a layer.

According to this configuration, the wiring is formed in a predetermined pattern on the interlayer insulating film. A SiOC film is formed along the surface of the interlayer insulating film and the wiring. An SOG layer is formed on the SiOC film. The SOG layer exposes a portion of the SiOC film formed on the wiring, and has a surface that is flush with the exposed surface of the SiOC film.
SiOC (silicon oxide to which carbon is added), which is a material of the SiOC film, has a lower O content than SiO ₂ . Therefore, when a deposition layer made of the material of the SOG layer is formed on the SiOC film and the SOG layer is formed by etching back this deposition layer, even if the SiOC film is exposed to the etching gas, the etching gas Since a large amount of O is not mixed therein, an increase in the etching rate of the SOG layer can be prevented. Therefore, the etching rate of the SOG layer does not increase and the dent does not occur in the SOG layer even around the portion where the SiOC film is exposed (portion formed on the wiring in the SiOC film). As a result, the surface of the SOG layer can be formed flat.

In addition, as described in claim 2, it is preferable that the SiOC film contains 10 atomic% or more and 40 atomic% or less of C (carbon).
When the C content is 10 atomic% or more, the O content can be relatively reduced. Therefore, it is possible to effectively suppress the mixing of O in the etching gas, and it is possible to satisfactorily prevent an increase in the etching rate of the SOG layer.

Moreover, when the C content is 40 atomic% or less, the film strength necessary for the SiOC film and the adhesion to the lower layer of the SiOC film can be ensured.
According to a third aspect of the present invention, an SiO ₂ film may be interposed between the SiOC film, the interlayer insulating film, and the wiring.
SiO ₂ is a material of SiO ₂ film has a higher strength as compared with SiOC, SiO ₂ film, by being interposed between the SiOC film and the interlayer insulating film and the wiring, SOG only SiOC film Compared to the case of forming a base film (interlayer insulating film and a base film interposed between the wiring and the SOG layer), the strength of the base film formed by laminating the SiOC film and the SiO ₂ film The film thickness can be reduced while maintaining the above.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.
The semiconductor device 1 includes a semiconductor substrate (for example, a silicon substrate) (not shown). On the semiconductor substrate, an interlayer insulating film 2 made of SiO ₂ is formed. A wiring 3 is formed on the interlayer insulating film 2 with a predetermined wiring pattern. The wiring 3 has a laminated structure in which a main wiring layer 4 made of Al is sandwiched between a barrier film 5 made of TiN and an antireflection film 6.

  A SiOC film 7 made of SiOC is formed on the interlayer insulating film 2 and the wiring 3. The SiOC film 7 contains, for example, 10 atomic% or more and 40 atomic% or less of C. The SiOC film 7 has a film thickness smaller than the interval between the adjacent wirings 3 and is formed along the surfaces of the interlayer insulating film 2 and the wirings 3. Thereby, a recess 15 partitioned by the SiOC film 7 is formed between the wirings 3. In other words, the SiOC film 7 formed on the side surface of the opposing wiring 3 forms the side surface of the recess 15, and the SiOC film formed on the surface of the interlayer insulating film 2 between the wirings 3 forms the bottom surface of the recess 15. .

The recess 15 defined by the SiOC film 7 is filled with an SOG layer 8 made of an organic SOG material (for example, MSQ). The surface of the SOG layer 8 is a portion formed on the wiring 3 in the SiOC film 7. It is almost flush with the surface.
An interlayer insulating film 9 made of SiO ₂ is formed on the SiOC film 7 and the SOG layer 8. In the interlayer insulating film 9, a via hole 10 penetrating from the upper surface of the interlayer insulating film 9 to the upper surface of the wiring 3 is formed in a portion facing a predetermined portion of the wiring 3. A via 11 made of W (tungsten) is embedded in the via hole 10. An upper layer wiring (not shown) is formed on the interlayer insulating film 9, and the wiring 3 and the upper layer wiring are electrically connected via the via 11.

2A to 2F are schematic sectional views for explaining the manufacturing method of the semiconductor device 1 in the order of steps.
First, an interlayer insulating film 2 is formed on a semiconductor substrate (not shown) (for example, a silicon substrate). Thereafter, as shown in FIG. 2A, a TiN layer 12, an Al alloy layer 13, and a TiN layer 14 are stacked in this order from the semiconductor substrate side on the interlayer insulating film 2 by sputtering.

Next, the TiN layer 12, the Al alloy layer 13, and the TiN layer 14 are selectively etched, whereby the wiring 3 is formed in a predetermined pattern as shown in FIG. 2B.
Thereafter, as shown in FIG. 2C, a SiOC film 7 is formed on the interlayer insulating film 2 and the wiring 3 by plasma CVD (Chemical Vapor Deposition). The SiOC film 7 has a film thickness smaller than the interval between the wirings 3 and is formed so as to cover the surfaces of the interlayer insulating film 2 and the wirings 3.

Next, as shown in FIG. 2D, the material of the SOG layer 8 is spin-coated on the SiOC film 7, thereby forming the deposition layer 16 made of the material of the SOG layer 8. The deposited layer 16 is formed to a thickness that fills the recess 15 defined by the SiOC film 7 and covers a portion of the SiOC film 7 formed on the wiring 3.
Thereafter, the portion formed on the wiring 3 in the deposition layer 16 is removed by etch back, as shown in FIG. 2E. As a result, the surface of the SiOC film 7 is exposed on the wiring 3, and the SOG layer 8 having a surface substantially flush with the SiOC film 7 is formed in the recess 15. This etch-back process etches a mixed gas in which CF ₄ (carbon tetrafluoride) gas and CHF ₃ (methane trifluoride) gas are mixed at a ratio of CF ₄ : CHF ₃ = 1: 1 to 0.8. This is performed by dry etching used as a gas (etchant).

Next, as shown in FIG. 2F, an interlayer insulating film 9 is laminated on the SOG layer 8 and the SiOC film 7 by the CVD method.
Thereafter, the via hole 10 is formed by selectively etching the interlayer insulating film 9. Then, by burying a via 11 made of W in the via hole 10, the semiconductor device 1 shown in FIG. 1 is obtained.

  As described above, the wiring 3 is formed in a predetermined pattern on the interlayer insulating film 2. An SiOC film 7 is formed on the interlayer insulating film 2 and the wiring 3 along their surfaces. An SOG layer 8 is formed on the SiOC film 7. The SOG layer 8 exposes a portion of the SiOC film 7 formed on the wiring 3 and has a surface that is flush with the exposed surface of the SiOC film 7.

SiOC film 7 is a material SiOC has a low content of O in comparison with the SiO _2. Therefore, a deposited layer 16 made of the material of the SOG layer 8 is formed on the SiOC film 7, and when the SOG layer 8 is formed by etching back the deposited layer 16, the SiOC film 7 is exposed to an etching gas. However, since a large amount of O is not mixed into the etching gas, an increase in the etching rate of the SOG layer 8 can be prevented. Therefore, the etching rate of the SOG layer 8 does not increase even in the vicinity of the part where the SiOC film 7 is exposed (the part formed on the wiring 3 in the SiOC film 7), and the SOG layer 8 is depressed. Absent. As a result, the surface of the SOG layer 8 can be formed flat.

Further, when the C content in the SiOC film 7 is 10 atomic% or more, the O content can be relatively lowered. Therefore, it is possible to effectively suppress the mixing of O into the etching gas, and it is possible to favorably prevent an increase in the etching rate of the SOG layer 8.
Further, when the C content in the SiOC film 7 is 40 atomic% or less, the film strength necessary for the SiOC film 7 and the adhesion to the interlayer insulating film 2 can be ensured.

In the etch-back process shown in FIG. 2E, if the etching rates of the SOG layer 8 (deposition layer 16) and the underlying film (in this embodiment, the SiOC film 7) are close, the surfaces of the SOG layer 8 and the underlying film are flattened. Can be formed. This etching rate is adjusted by changing the mixing ratio of CF ₄ and CHF ₃ in the etching gas. For example, when the base film is made of SiO ₂ , the etching rate of the SOG layer 8 and the base film can be made closer to each other by increasing the ratio of the CHF ₃ gas. Can improve the flatness. However, if the ratio of CHF ₃ gas is increased too much, the etching may stop.

In this embodiment, since the SOG layer 8 and the SiOC film 7 which is a base film are both made of an organic material (material containing carbon), the film quality is similar and the etching rate is close. Therefore, the etching rate of the SOG layer 8 and the etching rate of the SiOC film 7 can be matched without extremely increasing the ratio of CHF _{3 in} the etching gas. As a result, the surfaces of the SOG layer 8 and the SiOC film 7 can be formed flat without causing problems such as etching stop.

FIG. 3 is a schematic cross-sectional view showing the structure of a semiconductor device according to another embodiment of the present invention.
The semiconductor device 51 includes a semiconductor substrate (for example, a silicon substrate) not shown. An interlayer insulating film 52 made of SiO ₂ is formed on the semiconductor substrate. A wiring 53 is formed on the interlayer insulating film 52 with a predetermined wiring pattern. The wiring 53 has a laminated structure in which a main wiring layer 54 made of Al is sandwiched between a barrier film 55 made of TiN and an antireflection film 56.

A base film 67 is formed on the interlayer insulating film 52 and the wiring 53. The base film 67 is made of SiO ₂ , the SiO ₂ film 57 formed along the surfaces of the interlayer insulating film 52 and the wiring 53, and the SiOC film 58 made of SiOC and formed along the surface of the SiO ₂ film 57. Are stacked. The SiOC film 58 contains, for example, 10 atomic% or more and 40 atomic% or less of C.

The base film 67 has a film thickness smaller than the interval between the adjacent wirings 53. For example, when the interval between adjacent wirings 53 is 0.6 μm, the SiO ₂ film 57 has a film thickness of 100 nm on the wirings 53 and the SiOC film 58 has a film thickness of 300 nm on the wirings 53. is doing. Thereby, a recess 66 partitioned by the base film 67 is formed between the wirings 53. That is, the base film 67 (SiOC film 58) formed on the side surfaces of the opposing wiring 53 forms the side surface of the recess 66, and the base film 67 (SiOC film 58) formed on the surface of the interlayer insulating film 52 between the wirings 53. ) Forms the bottom surface of the recess 66.

The recess 66 defined by the base film 67 is filled with an SOG layer 59 made of an organic SOG material (for example, MSQ). The surface of the SOG layer 59 is above the wiring 53 in the base film 67 (SiOC film 58). It is almost flush with the surface of the formed part.
On the base film 67 and the SOG layer 59, an interlayer insulating film 60 made of SiO ₂ is formed. In the interlayer insulating film 60, a via hole 61 that penetrates from the upper surface of the interlayer insulating film 60 to the upper surface of the wiring 53 is formed penetratingly at a portion facing a predetermined portion of the wiring 53. A via 62 made of W is embedded in the via hole 61. An upper layer wiring (not shown) is formed on the interlayer insulating film 60, and the wiring 53 and the upper layer wiring are electrically connected through the via 62.

4A to 4G are schematic sectional views for explaining the method for manufacturing the semiconductor device 51 in the order of steps.
First, an interlayer insulating film 52 is formed on a semiconductor substrate (not shown). Thereafter, as shown in FIG. 4A, a TiN layer 63, an Al alloy layer 64, and a TiN layer 65 are stacked in this order from the semiconductor substrate side on the interlayer insulating film 52 by sputtering.

Next, the TiN layer 63, the Al alloy layer 64, and the TiN layer 65 are selectively etched, thereby forming the wiring 53 in a predetermined pattern as shown in FIG. 4B.
Thereafter, as shown in FIG. 4C, a SiO ₂ film 57 is formed on the interlayer insulating film 52 and the wiring 53 by plasma CVD.
Next, as shown in FIG. 4D, a SiOC film 58 is formed on the SiO ₂ film 57 by plasma CVD. As a result, a base film 67 composed of the SiO ₂ film 57 and the SiOC film 58 is formed.

Thereafter, as shown in FIG. 4E, the material of the SOG layer 59 is spin-coated on the base film 67, thereby forming the deposited layer 68 made of the material of the SOG layer 59. The deposited layer 68 is formed to a thickness that fills the recess 66 defined by the base film 67 and covers a portion of the SiOC film 58 formed on the wiring 53.
Thereafter, the portion formed on the wiring 53 in the deposition layer 68 is removed by etch back, as shown in FIG. 4F. As a result, the surface of the base film 67 is exposed on the wiring 53, and the SOG layer 59 having a surface substantially flush with the surface of the portion of the base film 67 formed on the wiring 3 is formed in the recess 66. Is done. This etch-back process is performed by dry etching using a mixed gas of CF ₄ and CHF ₃ as an etching gas.

Next, as shown in FIG. 4G, an interlayer insulating film 60 is laminated on the SOG layer 59 and the base film 67 by the CVD method.
Thereafter, the via hole 61 is formed by selectively etching the interlayer insulating film 60. Then, the via 62 made of W is buried in the via hole 61, whereby the semiconductor device 51 shown in FIG. 3 is obtained.

As described above, the wiring 53 is formed in a predetermined pattern on the interlayer insulating film 52. On the interlayer insulating film 52 and the wiring 53, a base film 67 is formed along the surface thereof. The base film 67 includes a SiO ₂ film 57 in contact with the interlayer insulating film 52 and the wiring 53, and a SiOC film 58 that covers the surface of the SiO ₂ film 57. An SOG layer 59 is formed on the base film 67. The SOG layer 59 exposes a portion of the base film 67 formed on the wiring 53, and has a surface that is flush with the surface of the exposed base film 67 (SiOC film 58).

SiOC which is a material of the film 58 SiOC has a low content of O in comparison with the SiO _2. Therefore, a deposition layer 68 made of the material of the SOG layer 59 is formed on the SiOC film 58, and when the SOG layer 59 is formed by etching back the deposition layer 68, the SiOC film 58 is exposed to an etching gas. However, since a large amount of O is not mixed in the etching gas, an increase in the etching rate of the SOG layer 59 can be prevented. Therefore, the etching rate of the SOG layer 59 does not increase even around the portion where the SiOC film 58 is exposed (portion formed on the wiring 53 in the base film 67), and the SOG layer 59 is depressed. Absent. As a result, the surface of the SOG layer 59 can be formed flat.

Further, when the C content in the SiOC film 58 is 10 atomic% or more, the O content can be relatively lowered. Therefore, it is possible to effectively suppress the mixing of O into the etching gas, and to prevent an increase in the etching rate of the SOG layer 59.
Further, when the C content in the SiOC film 58 is 40 atomic% or less, the film strength necessary for the laminated base film 67 and the adhesion to the interlayer insulating film 52 can be ensured.

Further, SiO ₂ which is a material of SiO ₂ film 57 has a higher strength as compared with SiOC, the SiO ₂ film 57 is interposed between the SiOC film 58 and the interlayer insulating film 52 and the wiring 53 As a result, the strength of the base film 67 is increased as compared with the case where the base film of the SOG layer 59 (the base insulating film interposed between the interlayer insulating film 52 and the wiring 53 and the SOG layer 59) is formed only by the SiOC film 58. The film thickness can be reduced while maintaining. In addition, since SiO ₂ has a higher deposition rate than SiOC, the manufacturing time of the semiconductor device 51 (base film 67) can be shortened as compared with the case where the base film is formed of only the SiOC film 58. Can do.

As mentioned above, although two embodiment of this invention was described, this invention can also be implemented with another form.
For example, in the above embodiment, an organic SOG material (for example, MSQ) is used as the material of the SOG layers 8 and 59, but the material of the SOG layers 8 and 59 is Si (OH) ₄ (silanol) or the like. Inorganic SOG materials may be used.

  In addition, various design changes can be made within the scope of the matters described in the claims.

1 is a schematic cross-sectional view showing a structure of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 1. FIG. 2B is an illustrative sectional view showing a step subsequent to FIG. 2A. FIG. 2D is an illustrative sectional view showing a step subsequent to FIG. 2B. FIG. 2D is an illustrative sectional view showing a step subsequent to FIG. 2C. FIG. 2D is an illustrative sectional view showing a step subsequent to FIG. 2D. FIG. 2D is an illustrative sectional view showing a step subsequent to FIG. 2E. It is an illustration sectional view showing the structure of the semiconductor device concerning other embodiments of the present invention. FIG. 4 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 3. FIG. 4B is an illustrative sectional view showing a step subsequent to FIG. 4A. FIG. 4D is an illustrative sectional view showing a step subsequent to FIG. 4B. FIG. 4D is an illustrative sectional view showing a step subsequent to FIG. 4C. FIG. 4D is an illustrative sectional view showing a step subsequent to FIG. 4D. FIG. 4D is an illustrative sectional view showing a step subsequent to FIG. 4E. FIG. 4D is an illustrative sectional view showing a step subsequent to FIG. 4F. It is an illustrative sectional view for explaining a conventional method for manufacturing a semiconductor device. FIG. 5B is an illustrative sectional view showing a step subsequent to FIG. 5A. FIG. 5B is an illustrative sectional view showing a step subsequent to FIG. 5B. FIG. 5D is a schematic sectional view showing a step subsequent to FIG. 5C. FIG. 5D is an illustrative sectional view showing a step subsequent to FIG. 5D. FIG. 5E is an illustrative sectional view showing a step subsequent to FIG. 5E.

Explanation of symbols

1 semiconductor device 2 interlayer insulating film 3 a wiring 7 SiOC film 8 SOG layer 51 semiconductor device 52 interlayer insulating film 53 wirings 57 SiO ₂ film 58 SiOC film 59 SOG layer

Claims (3)

An interlayer insulating film;
Wiring formed in a predetermined pattern on the interlayer insulating film;
A SiOC film formed along the surface of the interlayer insulating film and the wiring;
A semiconductor device comprising: an SOG layer formed on the SiOC film, exposing a portion of the SiOC film formed on the wiring, and having a surface flush with the exposed surface of the SiOC film.   The semiconductor device according to claim 1, wherein the SiOC film contains 10 atomic% or more and 40 atomic% or less of C (carbon). 3. The semiconductor device according to claim 1, wherein a SiO ₂ film is interposed between the interlayer insulating film and the wiring and the SiOC film.

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