JP2009170468A - MOS field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve both increase of a breakdown voltage and decrease of on-resistance. <P>SOLUTION: In this MOS field-effect transistor formed on a semiconductor substrate, and provided with a source N+ region 8, a body contact region 9, a gate region, a drift region and a drain N+ region 6, and in which the drift region is arranged between the drain N+ region 6 and the gate region, the gate region has a gate electrode 10 and a plurality of trenches 4 projecting from the gate electrode 10; in the drift region, the plurality of trenches 4 and one or more drift parts are alternately arranged; the gate electrode 10 has polysilicon densely doped in the inside; and each of the plurality of trenches 4 has a polysilicon electrode 5 thinly doped in the inside. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to the structure, process and manufacture of semiconductor devices, and more particularly to lateral trench MOS field effect transistors.

  A lateral double-diffused MOS field effect transistor (hereinafter referred to as LDMOSFET) has a high breakdown voltage and a low specific on-resistance due to its efficient structure, and power control electronics. Widely used in the field. Since the LDMOSFET is compatible with the CMOS process, it is integrated into the IC together with the control logic. In general, the LDMOSFET is used as an output driver for supplying a high current to an external load. Generally, the LDMOSFET is integrated in the same IC as the control circuit when the output current capacity is about 2 A to less than about 3 A. For larger currents, using off-chip power transistors is more cost effective.

  FIG. 8 shows a general layout and structure of a conventional LDMOSFET. In the above conventional LDMOSFET, the heavily doped drain diffusion layer is separated from the gate electrode by a relatively long and thinly doped region having the same conductivity type as the drain diffusion layer. It is formed in alignment and has an asymmetric structure adjacent to the gate electrode. This lightly doped drain region is further referred to as the drift region and is designed to withstand high supply voltages.

Two important parameters in the LDMOSFET (key parameter) is a breakdown voltage BVdss and the on-resistance _{R ON.} The physical location and physical meaning of the different components of the on-resistance _RON are shown in FIG.
R _ON = R _ch + R _acc + R _drift
It becomes. Here, R _ch is the resistance of the MOSFET channel in which electrons are induced, R _acc is the resistance of accumulation induced in the region (gate-drain overlap region), and R _drift is thin. It is the resistance of the doped drain region.

In general, in order to obtain a high breakdown voltage BVdss is required lightly doped long drift regions impurities, As a result, the on-resistance as a whole increases, and the breakdown voltage BVdss and the on-resistance R _ON A trade-off relationship is established between the two.

  In general, the LDMOSFET design technique relies on maximizing the use of the doping profile and drift region. As these technologies, the RESURF (REduced SURface electric Field) structure proposed in Non-Patent Document 1 is well known. In the RESURF structure, the N well drift region (HNW, see FIG. 9), the doping concentration and the depth are designed so that the N well drift region is completely depleted in the off state. As a result, the electric field is relaxed and the doping concentration of the drift region can be increased.

  In another method, the drift region is provided around the trench 25 provided between the gate electrode and the drain contact region as described in Patent Document 1 and shown in FIG. Used. In this structure, the channel region is horizontal and current flows in region 14.

  In Patent Document 2 and FIG. 11, the channel is vertical as indicated by reference numeral 25, and the gate electrode 30 is formed in the trench region.

  FIG. 12 shows the structure of the LDMOS represented in Non-Patent Document 2, which is named a super junction structure RESURF LDMOSFET (Super Junction RESURF LDMOSFET). The drift region between the gate and drain N + diffusion layers is formed by alternately arranging N-type regions and P-type regions. The widths and doping concentrations of these N and P regions are designed so that the N and P regions are completely depleted in the off state. In other words, this is a kind of lateral (2-D) RESURF structure. A similar structure is disclosed in US Pat.

FIG. 13 shows an SOI-Super-Junction MOSFET having a trench gate described in Non-Patent Document 3. This MOSFET structure utilizes the same effect as the device shown in FIG. 12, but is implemented in an SOI wafer. In addition, the gate is buried in the trench, and by filling the trench in this manner, the channel current flows parallel to the surface of the wafer but perpendicular to the trench sidewalls.
US Pat. No. 5,569,949 (published October 29, 1996) US Patent No. 7,033,891 (published April 25, 2006) JP 2000-286417 A (published on October 13, 2000) JA Appels, and HMJ Vaes, “HV thin layer devices (RESURF devices)”, Proc. Of Intl. Electron Devices Meeting (IEDM), Technical Digest, 1979, pp. 238-241. SG Nassif-Khalil, LZ Hou and CAT Salama, “SJ / RESURF LDMOST,” IEEE Trans. Electron Devices, Vol. 51, No. 7, pp. 1185-1191, July 2004. JM Park, R. Klima and S. Selberherr, “Lateral trench gate Super-Junction SOI-LDMOSFETs with low ON-resistance,” Institute for Microelectronics, TU Wien, Gusshausstrasse 27-29, A-1040 Vienna, Austria. Paper presented at ESSDERC 2002.

  However, the conventional LDMOSFET has the following problems.

  The conventional LDMOSFET structure shown in FIG. 9 has a limit in reducing the on-resistance because the on-resistance is reduced by the effect of the RESURF (problem a).

  In the LDMOS FEF described in Patent Document 1, since the surface area is reduced by using the length of the drift region around the trench, it is necessary to form the trench deeply, and the process becomes complicated (problem b) ). Further, the LDMOSFET process of Patent Document 1 has the same problem as the problem a.

  The LDMOSFET described in Patent Document 2 is not reduced in size because the drift region is defined by the effect of the RESURF.

  The LDMOSFET device shown in both FIG. 12 and FIG. 13 utilizes a super junction technique implemented by alternating N-type and P-type drift regions. In both cases, the definition of the width and doping concentration of these regions is limited by the arrangement of these regions and the lateral diffusion layer.

  As a result, the prior art is insufficient to reduce the on-resistance of the MOSFET while having high productivity.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a MOS field effect transistor capable of realizing both a high breakdown voltage and a low on-resistance. It is to provide.

In order to solve the above problems, a MOS field effect transistor according to the present invention is formed on a semiconductor substrate and includes a source region, a gate region, a drift region, and a drain region, and the drift region includes the drain region and the gate region. In the MOS field effect transistor provided therebetween, the gate region has a gate electrode portion and a plurality of trenches protruding from the gate electrode portion, and the drift region includes the plurality of trenches and at least one or more drifts. The gate electrode portion has polysilicon doped therein with a doping concentration higher than 1 × 10 ¹⁹ at / cm ³ , and each of the plurality of trenches has an inner portion of 1 × 10 ¹⁹ at / cm ^3. Polysilicon doped at a doping concentration of x10 ¹³ at / cm ³ to 1 x 10 ¹⁹ at / cm ³ It is characterized by having.

  According to the invention, by appropriately setting the doping concentration of the drift portion, the doping concentration of the lightly doped polysilicon in the plurality of trenches, the width of the lightly doped polysilicon and the drift portion, When a positive potential is applied to the drain in the gate-off state, the drift region can be completely depleted. Accordingly, the electric field of the drift portion is relaxed, the breakdown voltage of the drain is improved, and the breakdown voltage BVdss between the drain region and the source region can be increased. Therefore, since the doping concentration of the drift portion can be made higher than before, the on-resistance of the MOS field effect transistor can be made smaller.

The gate region is doped with polysilicon doped at a doping concentration higher than 1 × 10 ¹⁹ at / cm ^{3 and} at a doping concentration of 1 × 10 ¹³ at / cm ³ to 1 × 10 ¹⁹ at / cm ^3. By dividing into polysilicon, the equipotential surface is not concentrated between the gate region and the drain region, the electric field in the drift region is relaxed, and the breakdown voltage of the drain region is improved. As a result, the entire drift region in the high-pressure N well region (HNW) including the thinly doped region is completely depleted.

  As a result, since the electric field is sufficiently relaxed, when the same breakdown voltage is ensured, the doping concentration of the HNW can be set higher, which greatly increases the trade-off relationship between breakdown voltage and on-resistance. Can be improved.

  In the MOS field effect transistor, the semiconductor substrate may be a silicon substrate.

  In the MOS field effect transistor, a voltage different from that of the gate electrode portion may be applied to the polysilicon included in the plurality of trenches.

  Thereby, even in the off state, the polysilicon potential in the plurality of trenches can be set to a potential different from that of the gate electrode portion, and the voltage applied to the drift region can be lowered. Therefore, the electric field in the drift region is relaxed, and the breakdown voltage between the drain region and the source region can be increased.

  In the MOS field effect transistor according to the present invention, as described above, the gate region has a gate electrode portion and a plurality of trenches protruding from the gate electrode portion, and the drift region includes at least one of the plurality of trenches. Two or more drift portions are alternately arranged, the gate electrode portion includes heavily doped polysilicon, and the plurality of trenches each include lightly doped polysilicon. It is.

  Therefore, there is an effect that both the breakdown voltage is increased and the on-resistance is reduced.

  An embodiment of the present invention will be described below with reference to Examples 1 to 2 and FIGS.

[Example 1]
FIG. 1A shows a plan view of a gate drift region lateral diffusion MOS field effect transistor (hereinafter referred to as GD-LDMOSFET) in the present embodiment. FIG. 1B is a cross-sectional view taken along line AB of the GD-LDMOSFET shown in FIG. Further, FIG. 1C shows a cross-sectional view taken along line C-D of the GD-LDMOSFET shown in FIG.

In order to realize the GD-LDMOSFET of this embodiment, a gate electrode 10 embedded in the shallow trench 4 is formed in the GD-LDMOSFET of FIG. The gate electrode 10 is formed to control an electric field in a drift region (hereinafter, simply referred to as a drift region) whose length in the M direction is L _drift .

FIG. 2 is a perspective view of the GD-LDMOSFET including a cross-sectional view taken along the line A-B shown in FIG. FIG. 3 is a cross-sectional view taken along line EF of the GD-LDMOSFET shown in FIG. The cross section between E and F crosses a channel region having a length _Lch (hereinafter simply referred to as a channel region), and has a horizontal portion 11 and trench sidewalls 12.

  4 is a cross-sectional view taken along the line GH of the GD-LDMOSFET shown in FIG. The cross section between GH is a cross-sectional view of a drift region having a plurality of trenches 4, and a lateral direction (from a high-voltage N well region (HNW) 2 and a polysilicon electrode (trench gate electrode) 5 described later ( The space charge layer 13 induced by the electric field in the (L direction) is shown.

  FIG. 5 is a diagram showing the electric field distribution along the drift region of the conventional LDMOSFET and the GD-LDMOS of this embodiment. The electric field between the trenches in the drift region is relaxed due to the space charge layer 13 induced by the trench.

  The structure of the GD-LDMOSFET described above relates to the N-channel type GD-LDMOSFET, but the same applies to the P-channel type GD-LDMOSFET.

  On a P-type semiconductor substrate 1 whose conductivity type is P-type, a high-voltage N-well region 2 whose conductivity type is N-type is formed. Individual semiconductor devices are insulated by a semiconductor oxide 3. The plurality of trenches 4 are formed on the silicon substrate by etching. The polysilicon electrode 5 is formed by filling the trench 4 with polysilicon. The polysilicon electrode 5 is insulated from the silicon substrate by a gate insulator. The channel region of the GD-LDMOSFET of this embodiment is formed by a P-type diffusion region (PB) 7. P-type diffusion region 7 is maintained at the same potential as source N + region 8. The body P + diffusion layer 9 is formed between the semiconductor oxide 3 and the source N + region 8 on the surface of the GD-LDMOSFET. The gate electrode 10 uses the same polysilicon layer as that used for the polysilicon electrode 5, and is formed on the surface of the GD-LDMOSFET along the ± L direction.

  In the drift region, the polysilicon electrodes 5 and the drift portions are alternately arranged. In this structure, since the polysilicon electrode 5 inside the trench 4 is lightly doped, the drift region can be depleted. Therefore, the polysilicon electrode 5 controls the depletion layer in the adjacent drift region, and as a result, the electric field in the drift region can be relaxed. Accordingly, the breakdown voltage BVdss between the drain and the source can be increased. Further, as described above, since the electric field in the drift region can be relaxed, the doping concentration in the drift region can be increased, and the on-resistance can be reduced.

  The drift region is completely depleted by applying a voltage having a potential difference Vd−Vg between the drain voltage Vd and the gate voltage Vg. Among the states in which the GD-LDMOSFET is operating, the state when the gate voltage Vg of the GD-LDMOSFET is zero is an off state, and in the meaning of the voltage applied between the drain and source of the GD-LDMOSFET. The drift region must be completely depleted even under the most severe condition.

When the gate voltage Vg> 0, the following two states are conceivable. The first state is the drain voltage Vd << gate voltage Vg, which is called a triode state. In this state, since the potential difference Vd−Vg <0, the drift region cannot be completely depleted. The second state is drain voltage Vd> gate voltage Vg−threshold voltage Vth, and is called a saturated state. In the saturated state, the drift region can be completely depleted by increasing the drain voltage Vd. The threshold voltage Vth is a gate voltage when the MOSFET changes from the off state to the on state.

Normally, a MOSFET operates with a load connected, but as can be seen by considering an operating characteristic curve with the gate voltage Vg as a parameter, the gate voltage Vg> 0 is greater than the gate voltage Vg = 0. The voltage applied between the drain and source of the GD-LDMOSFET becomes small. That is, when the gate voltage Vg = 0, the strictest condition is the operating condition. Therefore, the GD-LDMOSFET is designed so that the drift region is completely depleted under the most severe conditions. The target of this design is the following four parameters.
1. Drift concentration N _drift
2. Polysilicon electrode 5 doping concentration Ng
3. 3. Alternating polysilicon electrodes 5 and widths of drift portions Potential difference Vd-Vg
By reducing the doping concentration N _drift and the doping concentration Ng in the above parameters, the space charge layer 13 can be easily expanded with a lower potential difference Vd−Vg, and the drift region can be further narrowed.

[Example 2]
In this example, the structure and manufacturing method of the new GD-LDMOSFET shown in Example 1 will be described in detail. In the above description, an N-channel GD-LDMOSFET has been studied, but it will be apparent to those skilled in the art that a P-channel GD-LDMOSFET can be easily implemented by the complement theory.

  Hereinafter, a series of assembly of the trench MOSFET having the structure shown in FIG. 2 will be described. Initially, the silicon substrate 1 is doped P-type. The resistivity of the P-type doped silicon substrate 1 is 10 Ωcm to 100 Ωcm, and the thickness of the P-type doped silicon substrate 1 is 500 μm to 650 μm.

As in the conventional CMOS process, the above series of assembly is performed by performing drive-in processing by a high temperature diffusion process after implanting ³¹ P + ions of 1 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ^−2. Begin by forming an N-well region (HNW) 2. The depth of the formed N well region (HNW) 2 is 2 μm to 10 μm, and this depth depends on the desired electrical characteristics of the device.

  Subsequently, a conventionally used semiconductor oxide 3 for insulation is formed by LOCOS (local oxidation of silicon) (or insulated by a shallow trench 3). The semiconductor oxide 3 has a depth of 300 μm to 600 μm. The semiconductor oxide 3 defines an active region.

Next, the trench 4 is formed by a photoetching technique. The depth of the trench 4 is 300 nm to 1000 nm, and the width of the trench 4 is 200 nm to 500 nm. After the trench 4 is formed by photoetching, a gate insulating layer is formed on the bottom surface of the wafer and the surface of the trench 4 by using, for example, silicon oxide. After the formation of the gate insulating layer, polysilicon is deposited so as to cover the entire wafer. The polysilicon has a thickness of 150 nm to 400 nm. The polysilicon layer is implanted with ³¹ P + ions of 1 × 10 ¹² cm ⁻² to 1 × 10 ¹⁵ cm ⁻² without using any mask.

In the next step, the polysilicon electrode is patterned by conventional photoetching techniques. In this step, a gate electrode 10 on the surface of the MOSFET and a polysilicon electrode (trench gate electrode) 5 are formed. The polysilicon electrode 5 is doped so that the doping concentration is 1 × 10 ¹³ at / cm ³ to 1 × 10 ¹⁹ at / cm ³ .

Next, the source N + region 8, the drain N + region 6 and the heavily doped gate electrode 10 are formed by a photomask technique and about 1 × 10 ¹⁵ cm to form a junction having a depth of 0.2 μm to 0.5 μm. ^-2 to about 3 × 10 ¹⁵ cm ^-2 of N-type impurities ( ³¹ P + or ⁷⁵ As +). The doping concentration of the gate electrode 10 is higher than 1 × 10 ¹⁹ at / cm ³ . Subsequently, in step with the other photomask technique, the body contact region (body P + diffusion layer) 9 for forming a junction depth 0.2Myuemu～0.5Myuemu, about 1 × ^{10 15} cm ^- Doped by implantation of ² to about 3 × 10 ¹⁵ cm ⁻² of P-type impurities ( ¹¹ B + or ⁴⁹ BF ₂ +). The doping concentrations of the polysilicon electrode 5 and the gate electrode 10 are determined based on theory and simulation.

  Finally, as in a typical formation of a conventional IC, deposition of an insulator between layers, formation of a contact hole, and metal wiring are successively performed.

  As described above, the reason why the gate region in the trench 4 needs to be divided into a portion with a high doping concentration (gate electrode 10) and a thin portion (polysilicon electrode 5) will be described. When the doping concentration of the thinly doped region is set high, the gate region in the trench 4 is fixed to 0 V on the entire surface. Therefore, when a positive voltage is applied to the drain, the equipotential surface is as shown by the alternate long and short dash line in FIG. become.

  That is, since the electric field concentrates on the gate edge (region A) surrounded by the broken line or between the gate region and the drain N + region (region B), the region A or region B is used to increase the breakdown voltage of the drain. It is necessary to relax the electric field.

  As an example of the electric field relaxation in the region A, it is conceivable to reduce the HNW concentration.

  On the other hand, when the electric field in the region B is relaxed, it is conceivable to increase the distance in the region B. However, in this case as well, there is a problem that the on-resistance increases.

  Therefore, in the case of the structure shown in FIG. 6, since the on-resistance increases in order to improve the breakdown voltage, the trade-off relationship between the breakdown voltage and the on-resistance cannot be improved.

Therefore, a thin gate region (polysilicon electrode 5) is provided as shown in FIG. The equipotential surface at this time looks like the one-dot chain line shown in FIG. 7, and only the dark gate region (gate electrode 10) is fixed to 0 V, and the equipotential surface is like the one-dot chain line in the thin gate region. As a result, the electric field in the L _drift region is relaxed, and the breakdown voltage of the drain is improved. Thereby, the entire drift region in the HNW is completely depleted including the gate region which is thinly doped.

  As a result, since the electric field is sufficiently relaxed, the HNW doping concentration can be set higher when the same breakdown voltage is ensured, thus greatly improving the trade-off relationship between breakdown voltage and on-resistance. can do.

  Two features of the structure of the GD-LDMOSFET of this embodiment are related. The first feature is that a plurality of trenches are provided in a lightly doped drift region. The second feature is that the drift region has a RESURF structure. By using the polysilicon electrode 5 embedded in the plurality of trenches, surrounding the drift region by the plurality of trenches, and controlling the depletion layer in the drift region and the lateral electric field strength in the drift region, Relaxing the electric field strength is achieved, resulting in a higher breakdown voltage.

In order to obtain such an effect, the interval Xs between the plurality of trenches needs to be optimized together with the doping concentration N _{drift of the} drift portion. In general, the product of the doping concentration N _drift and the spacing Xs between trenches is less than 10 ¹² at / cm ² .

Example 3
In the third embodiment of the present invention, a double trench gate will be described. The double trench gate of the GD-LDMOSFET (semiconductor device) according to the third embodiment of the present invention has two gate electrodes, that is, a gate electrode 10 (main gate electrode) and a polysilicon electrode 5 (sub-gate electrode). ing. As described above, the gate electrode 10 serving as the main gate electrode controls the channel region formed on the back surface of the P-type diffusion region (body region) 7, that is, the junction surface with the high-voltage N-well region 2. A polysilicon electrode (drift gate electrode) 5 which is a sub-gate electrode has the same potential as the main gate electrode or a different potential from the main gate electrode. According to such a configuration, in the GD-LDMOSFET in the off state, the lightly doped drift region can be depleted and the breakdown voltage can be increased.

  The double trench gate makes it possible to set the potential of the polysilicon electrode 5 (drift gate electrode) as the sub-gate electrode to a potential different from that of the gate electrode 10 as the main gate electrode even in the off state. That is, for example, when a voltage of + V1 [V] is applied to the polysilicon electrode 5, the electric field is relaxed by V1 [V], and the HNW concentration, that is, the doping concentration of the HNW region can be increased. It becomes. At this time, the potential of the gate electrode 10 which is the main gate electrode is 0V.

That is, when VD [V] is applied to the drain, and when the double trench gate is not used, VD-0 [V], that is, VD [V] is _added to the drift region whose length in the M direction is L _drift in FIG. However, in the case of a double trench gate, only VD-V1 [V] is applied to the drift region. Therefore, the electric field in the drift region is relaxed, and the breakdown voltage between the drain region and the source region can be increased.

[Summary of Embodiment]
The MOS field effect transistor according to the embodiment of the present invention is formed on a semiconductor substrate and includes a source N + region 8 and a body contact region 9, a gate region, a drift region and a drain N + region 6, and the drift region is a drain N + region. 6 and the gate region, the gate region includes a gate electrode 10 and a plurality of trenches 4 protruding from the gate electrode 10, and the drift region includes a plurality of trenches 4 and At least one or more drift portions are alternately arranged, the gate electrode 10 has polysilicon doped therein with a doping concentration higher than 1 × 10 ¹⁹ at / cm ³ , and the plurality of trenches 4 include And a doping concentration of 1 × 10 ¹³ at / cm ³ to 1 × 10 ¹⁹ at / cm ^{3 respectively} . A polysilicon electrode 5 doped with

  According to the above configuration, the doping concentration of the drift portion, the doping concentration of the lightly doped polysilicon electrode 5 in the plurality of trenches 4, the lightly doped polysilicon electrode 5 in the plurality of trenches 4, and the drift portion When the positive potential is applied to the drain N + region 6 in the gate-off state, the drift region can be completely depleted. Therefore, the electric field of the drift portion is relaxed, and the breakdown voltage BVdss between the drain region and the source region can be increased. Therefore, since the doping concentration of the drift portion can be made higher than before, the on-resistance of the MOS field effect transistor can be made smaller.

The gate region is doped with polysilicon doped at a doping concentration higher than 1 × 10 ¹⁹ at / cm ^{3 and} at a doping concentration of 1 × 10 ¹³ at / cm ³ to 1 × 10 ¹⁹ at / cm ^3. By dividing into polysilicon, the equipotential surface is not concentrated between the gate region and the drain region, the electric field in the drift region is relaxed, and the breakdown voltage of the drain region is improved. As a result, the entire drift region in the high-pressure N well region (HNW) including the thinly doped region is completely depleted.

  As a result, when the same breakdown voltage is secured by sufficiently relaxing the electric field, the doping concentration of the HNW can be set higher, greatly increasing the trade-off relationship between breakdown voltage and on-resistance. Can be improved.

  In the MOS field effect transistor, the P-type semiconductor substrate 1 may be a silicon substrate.

  In the MOS field effect transistor, a voltage different from that of the gate electrode 10 may be applied to the polysilicon electrode 5 included in the plurality of trenches 4.

  Thereby, even in the off state, the potential of the polysilicon electrode 5 provided in the plurality of trenches 4 can be set to a potential different from that of the gate electrode 10, and the voltage applied to the drift region can be lowered. Therefore, the electric field in the drift region is relaxed, and the breakdown voltage between the drain region and the source region can be increased.

  Since the MOS field effect transistor of the present invention can increase the breakdown voltage and reduce the on-resistance, a DC-DC converter and a high-side switch (between the power source and the load are used to perform ON / OFF control of the power source. , Which plays a role of a switch).

FIG. 1A is a plan view of a GD-LDMOSFET according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line A-B of the GD-LDMOSFET shown in FIG. FIG. 1C is a cross-sectional view taken along the line CD of the GD-LDMOSFET shown in FIG. It is a perspective view of GD-LDMOSFET including sectional drawing between AB shown to FIG.1 (b). FIG. 3 is a cross-sectional view taken along line EF of the GD-LDMOSFET shown in FIG. 2. It is sectional drawing between GH of GD-LDMOSFET shown in FIG. It is a figure which shows distribution of the electric field along the drift region of conventional LDMOSFET and GD-LDMOS of embodiment of this invention. It is a figure which shows an equipotential surface when the whole gate region is heavily doped. It is a figure which shows an equipotential surface when the part doped deeply and the part doped lightly are provided in the gate area | region. It is a cross-sectional view and a plan view of a conventional LDMOSFET. It is a cross-sectional view of a conventional LDMOSFET, and shows the components of on-resistance. It is a cross-sectional view of a conventional LDMOSFET. It is a cross-sectional view of a conventional LDMOSFET. It is a cross-sectional view of a conventional LDMOSFET, and shows that the drift region is configured by alternately arranging N-type regions and P-type regions. It is the perspective view of the conventional Super Junction SOI-LDMOSFET provided with the lateral direction trench gate.

Explanation of symbols

1 P-type semiconductor substrate (semiconductor substrate)
2 High-voltage N-well region 3 Semiconductor oxide 4 Trench 5 Polysilicon electrode 6 Drain N + region 7 P-type diffusion region 8 Source N + region (source region)
9 Body contact area (source area)
DESCRIPTION OF SYMBOLS 10 Gate electrode 11 Horizontal part 12 Trench side wall 13 Space charge layer BVdss Breakdown voltage N _drift doping concentration Ng doping concentration Vd Drain voltage Vd-Vg Potential difference Vg Gate voltage Vth Threshold voltage Xs interval

Claims (3)

In a MOS field effect transistor formed on a semiconductor substrate, comprising a source region, a gate region, a drift region and a drain region, wherein the drift region is provided between the drain region and the gate region.
The gate region has a gate electrode portion and a plurality of trenches protruding from the gate electrode portion,
In the drift region, the plurality of trenches and at least one drift portion are alternately arranged,
The gate electrode portion has polysilicon doped therein with a doping concentration higher than 1 × 10 ¹⁹ at / cm ³ ;
2. The MOS field effect transistor according to claim 1, wherein each of the plurality of trenches has polysilicon doped therein with a doping concentration of 1 × 10 ¹³ at / cm ³ to 1 × 10 ¹⁹ at / cm ³ .   2. The MOS field effect transistor according to claim 1, wherein the semiconductor substrate is a silicon substrate.   3. The MOS field effect transistor according to claim 2, wherein a voltage different from that of the gate electrode portion is applied to polysilicon included in the plurality of trenches.