JP2009169485A - Information processing apparatus, semiconductor integrated circuit device, and boot method - Google Patents

Abstract

A semiconductor integrated circuit device to which a serial interface nonvolatile memory storing a boot program and a main program and a volatile memory is connected, without causing an increase in external parts, and designed Provided is a semiconductor integrated circuit device which can shorten the period and which does not incur reticle costs when a boot program is revised.
A system LSI includes a boot loader that is an interface for a serial flash memory, reads a boot program from the serial flash memory, executes the read boot program, and executes a main program in the serial flash memory Is copied to SDRAM4.
[Selection] Figure 1

Description

  The present invention relates to an information processing apparatus including a semiconductor integrated circuit device to which a nonvolatile memory of a serial interface storing a main program and a volatile memory are connected, and a semiconductor integrated device used in such an information processing device The present invention relates to a circuit device and a boot method.

  System LSIs (large scale integrated circuits) installed in mobile phones and PDAs (personal digital assistants) are stored in flash memory after system reset to reduce power consumption and improve processing performance. The main program is copied to an SDRAM (synchronous dynamic random access memory), and the copied program is executed. This is called system boot.

The flash memory includes a parallel interface flash memory (hereinafter referred to as a parallel flash memory) and a serial interface flash memory (hereinafter referred to as a serial flash memory). The parallel flash memory has an advantage that it can be accessed by an ordinary CPU (central processing unit) external bus. The serial flash memory accesses data by serially communicating address and read / write control information, and has the advantage that the number of signals required for access is small.
JP 2002-278781 A JP 2002-287994 A JP-A-6-348504

  Since the parallel Flash memory can be directly accessed from the CPU, the boot sequence can be easily realized when the parallel Flash memory is used. However, since it is necessary to separately provide an external terminal for accessing the flash memory and an external terminal for accessing the SDRAM in the system LSI, there is a problem that the number of external terminals of the system LSI increases.

  In contrast, serial flash memory cannot be addressed directly from the CPU, so when using serial flash memory, a ROM (read only memory) is installed outside or inside the system LSI and the boot program is stored in the ROM. By doing so, the boot sequence is realized.

  Here, when a ROM is mounted outside the system LSI, an increase in external parts becomes a problem. When a ROM is mounted in the system LSI, it is necessary to develop a boot program simultaneously with the development of the system LSI, and it is necessary to perform a system simulation for verification and evaluation of the boot program. For this reason, there is a problem that the development period is increased, and there is a problem that a reticle cost is required for the revision of the system LSI when the boot program is revised.

  Although there is a method of mounting a flash memory in the system LSI, in this case, there is a problem that the manufacturing cost of the system LSI becomes higher than when a general-purpose flash memory is used. is there.

  In view of the above, the present invention is an information processing apparatus including a semiconductor integrated circuit device in which a serial interface nonvolatile memory storing a main program and a volatile memory are connected, and causes an increase in external components. It is a first object of the present invention to provide an information processing apparatus that can reduce the design period and that does not incur reticle costs when the boot program is revised.

  Further, the present invention is a semiconductor integrated circuit device in which a non-volatile memory having a serial interface in which a boot program and a main program are stored and a volatile memory are connected without causing an increase in external parts, A second object of the present invention is to provide a semiconductor integrated circuit device that can shorten the design period and that does not incur reticle costs when the boot program is revised.

  The present invention also relates to an information processing apparatus comprising a serial interface nonvolatile memory storing a main program, a volatile memory, and a semiconductor integrated circuit device to which the nonvolatile memory and the volatile memory are connected. To provide a boot method that does not cause an increase in external parts, can shorten a design period, and does not incur reticle costs when a boot program is revised. Is the third purpose.

  An information processing apparatus disclosed in the present application includes a serial interface nonvolatile memory storing a boot program and a main program, a first volatile memory, and a semiconductor integrated circuit device. The CPU, the second volatile memory, and after releasing the system reset, the boot program in the nonvolatile memory is copied to the second volatile memory, and when the copying is completed, the CPU is reset. An interface for the non-volatile memory that releases the boot program, reads the boot program from the non-volatile memory, and executes the read boot program to execute the main program in the non-volatile memory as the first program. The program is copied to a volatile memory and the copied main program is executed.

  A semiconductor integrated circuit device disclosed in the present application is a semiconductor integrated circuit device in which a serial interface nonvolatile memory storing a boot program and a main program and a first volatile memory are connected to each other. And the boot means copies the CPU, the second volatile memory, and the boot program in the nonvolatile memory to the second volatile memory, and when the copying is completed, the CPU An interface for the non-volatile memory for releasing the reset of the non-volatile memory, reading the boot program from the non-volatile memory, and executing the read boot program to execute the main program in the non-volatile memory 1 to a volatile memory.

  A boot method disclosed in the present application includes a serial interface nonvolatile memory in which a main program is stored, a volatile memory, and a semiconductor integrated circuit device to which the nonvolatile memory and the volatile memory are connected. A boot method in a processing device, wherein a boot program is stored in the nonvolatile memory, the semiconductor integrated circuit device reads the boot program from the nonvolatile memory, executes the read boot program, and executes the boot program The method includes a step of copying the main program in the nonvolatile memory to the volatile memory.

  In the disclosed information processing apparatus, the nonvolatile memory stores the boot program and the main program, and the semiconductor integrated circuit device reads the boot program from the nonvolatile memory, and the read boot Since the program is executed to copy the main program in the nonvolatile memory to the volatile memory and the copied main program is executed, the boot is performed both inside and outside the semiconductor integrated circuit device. There is no need to install a ROM that stores the program.

  Thus, according to the disclosed information processing apparatus, it is not necessary to mount the ROM storing the boot program outside the semiconductor integrated circuit device, so that an increase in external parts is not caused. In addition, since it is not necessary to mount a ROM storing the boot program in the semiconductor integrated circuit device, it is not necessary to perform a system simulation for verification and evaluation of the boot program, thereby shortening the design period. be able to. In addition, since it is not necessary to mount the ROM storing the boot program in the semiconductor integrated circuit device, it is not necessary to update the semiconductor integrated circuit device when the boot program is revised, and the reticle cost is used when the boot program is revised. Can be prevented from occurring.

  In the disclosed semiconductor integrated circuit device, the boot unit is provided, the boot program is read from the nonvolatile memory, the read boot program is executed, and the main program in the nonvolatile memory is loaded. Since copying to a volatile memory is performed, there is no need to mount a ROM storing the boot program both externally and internally.

  As described above, according to the disclosed semiconductor integrated circuit device, it is not necessary to mount the ROM storing the boot program outside, so that an increase in external parts is not caused. In addition, since it is not necessary to mount a ROM storing the boot program therein, it is not necessary to perform a system simulation for verifying and evaluating the boot program, and the design period can be shortened. In addition, since it is not necessary to mount a ROM storing the boot program therein, the disclosed semiconductor integrated circuit device does not need to be revised when the boot program is revised, and the reticle cost is charged when the boot program is revised. It can be prevented from occurring.

  In the disclosed boot method, the boot program is stored in the nonvolatile memory in addition to the main program, and the semiconductor integrated circuit device reads the boot program from the nonvolatile memory, and the read Since the method includes a step of executing a boot program and copying the main program in the nonvolatile memory to the volatile memory, a ROM storing the boot program inside and outside the semiconductor integrated circuit device is provided. There is no need to install.

  As described above, according to the disclosed boot method, it is not necessary to mount the ROM storing the boot program outside the semiconductor integrated circuit device. In addition, since it is not necessary to mount a ROM storing the boot program in the semiconductor integrated circuit device, it is not necessary to perform a system simulation for verification and evaluation of the boot program, thereby shortening the design period. be able to. In addition, since it is not necessary to mount the ROM storing the boot program in the semiconductor integrated circuit device, it is not necessary to update the semiconductor integrated circuit device when the boot program is revised, and the reticle cost is used when the boot program is revised. Can be prevented from occurring.

  FIG. 1 is a block circuit diagram showing an embodiment of an information processing apparatus of the present invention. In FIG. 1, 2 is a system LSI which is an embodiment of the semiconductor integrated circuit device of the present invention, 3 is a serial flash memory connected to the system LSI 2, and 4 is an SDRAM connected to the system LSI 2. The serial flash memory 3 stores a boot program and a main program in advance.

  The system LSI 2 includes a CPU 5, a CPU bus 6, a RAM 7, a boot loader (Boot Loader) 8 that is an interface for the serial Flash memory 3, and a memory controller 9 that controls a write operation and a read operation of the SDRAM 4. .

  The boot loader 8 has a function of reading a program from the serial flash memory 3, but has a serial / parallel function of converting the program read serially from the serial flash memory 3 into parallel and outputting it to the CPU bus 6. . In the system LSI 2, the CPU 5, the CPU bus 6, the RAM 7, the boot loader 8, and the memory controller 9 constitute a boot unit.

  FIG. 2 is a flowchart showing the operation of one embodiment of the information processing apparatus of the present invention (one embodiment of the boot method of the present invention). S1 to S5 in FIG. 2 indicate processes, and correspond to S1 to S5 shown in FIG. In one embodiment of the information processing apparatus of the present invention, after the system reset is released, the boot loader 8 transfers the boot program stored in the serial Flash memory 3 from the serial Flash memory 3 to the RAM 7 (S1). When completed, the CPU 5 cancels the reset (S2). In this example, the reset vector indicates the inside of the RAM 7.

  When the reset is released by the boot loader 8, the CPU 5 fetches the reset vector on the RAM 7 (S 3), executes the boot program in the RAM 7, and executes the main program stored in the serial Flash memory 3 as the SDRAM 4. (S4) When this copy is completed, the program jumps to the start address of the main program in the SDRAM 4 and executes the main program (S5).

  FIG. 3 is a diagram showing the relationship between the serial flash memory 3, the RAM 7 and the SDRAM 4 in one embodiment of the information processing apparatus of the present invention. That is, in one embodiment of the information processing apparatus of the present invention, as described above, the boot program and the main program are stored in the serial flash memory 3 in advance, and the boot program is released by the boot loader 8 after releasing the system reset. The main program is transferred from the serial flash memory 3 to the RAM 7. After the reset of the CPU 5 is released, the main program is transferred from the serial flash memory 3 to the SDRAM 4 by the CPU 5.

  FIG. 4 is a diagram showing a reset release system in an embodiment of the information processing apparatus of the present invention. That is, in one embodiment of the present invention, as described above, after the system reset is released, the boot loader 8 transfers the boot program stored in the serial flash memory 3 to the RAM 7 and, after this transfer is completed, the CPU 5 reset is released. I do.

  When the program size is described in the boot program stored in the serial flash memory 3, the boot loader 8 includes a transfer means 10 for transferring the program and a counter for counting the transfer amount of the program as shown in FIG. 11 and reset canceling means 12 for canceling resetting of the CPU 5, a register 13 for storing the program size described in the boot program is provided, and the count value of the counter 11 is set to the program size stored in the register 13. In this case, the transfer means 10 may be configured to end the transfer of the boot program from the serial flash memory 3 to the RAM 7, and in this case, the size of the boot program is made variable. be able to.

  As described above, in one embodiment of the information processing apparatus of the present invention, the boot program and the main program are stored in the serial Flash memory 3, and the system LSI 2 reads the boot program from the serial Flash memory 3, and the read The boot program is executed, the main program in the serial flash memory 3 is copied to the SDRAM 4, and the copied main program is executed. Therefore, a ROM that stores the boot program both inside and outside the system LSI 2 is mounted. There is no need to do.

  As described above, according to the embodiment of the information processing apparatus of the present invention, it is not necessary to mount the ROM storing the boot program outside the system LSI 2, so that the number of external components is not increased. Further, since it is not necessary to mount a ROM storing a boot program in the system LSI 2, it is not necessary to perform a system simulation for verification and evaluation of the boot program, and the design period can be shortened. Further, since it is not necessary to mount a ROM storing the boot program in the system LSI 2, it is not necessary to update the system LSI 2 when the boot program is revised, and it is possible to prevent the occurrence of reticle costs when the boot program is revised. .

  Here, when the present invention is organized, the present invention includes at least the following information processing apparatus, semiconductor integrated circuit device, and boot method.

  (Supplementary Note 1) A serial interface nonvolatile memory storing a boot program and a main program, a first volatile memory, and a semiconductor integrated circuit device, the semiconductor integrated circuit device including a CPU, a second After the system reset is released, the boot program in the nonvolatile memory is copied to the second volatile memory, and when the copying is completed, the CPU reset is released. An interface for memory, and reads the boot program from the nonvolatile memory, executes the read boot program, and copies the main program in the nonvolatile memory to the first volatile memory. An information processing apparatus that executes the copied main program.

  (Supplementary Note 2) When the reset is released by the interface, the CPU executes the boot program copied to the second volatile memory to execute the main program in the nonvolatile memory. The information processing apparatus according to claim 1, wherein the information processing apparatus is copied to a volatile memory.

  (Supplementary Note 3) The interface includes a register that stores a program size described in the boot program, a counter that counts a transfer amount of the boot program from the nonvolatile memory to the second volatile memory, and Transfer means for terminating transfer of the boot program from the non-volatile memory to the second volatile memory when the count value of the counter reaches the program size stored in the register. The information processing apparatus according to appendix 2.

  (Supplementary Note 4) A semiconductor integrated circuit device to which a serial interface nonvolatile memory storing a boot program and a main program and a first volatile memory are connected, comprising boot means, the boot means comprising: The CPU, the second volatile memory, and the boot program in the nonvolatile memory are copied to the second volatile memory, and when the copying is completed, the reset of the CPU is released. The boot program is read from the nonvolatile memory, the read boot program is executed, and the main program in the nonvolatile memory is copied to the first volatile memory. A semiconductor integrated circuit device.

  (Supplementary Note 5) When the reset is released by the interface, the CPU executes the boot program copied to the second volatile memory to execute the main program in the nonvolatile memory as the first program. The semiconductor integrated circuit device according to appendix 4, wherein the semiconductor integrated circuit device is copied to a volatile memory.

  (Supplementary Note 6) The interface includes a register that stores a program size described in the boot program, a counter that counts a copy size of the boot program in the nonvolatile memory to the second volatile memory, and Transfer means for ending transfer of the boot program from the nonvolatile memory to the second volatile memory when the count value of the counter reaches the program size stored in the register. The semiconductor integrated circuit device according to appendix 5.

  (Supplementary note 7) Boot method in an information processing apparatus comprising a serial interface nonvolatile memory storing a main program, a volatile memory, and a semiconductor integrated circuit device to which the nonvolatile memory and the volatile memory are connected A boot program stored in the non-volatile memory, the semiconductor integrated circuit device reads the boot program from the non-volatile memory, and executes the read boot program in the non-volatile memory. A boot method comprising the step of copying the main program to the volatile memory.

It is a block circuit diagram showing one embodiment of an information processor of the present invention. It is a flowchart which shows operation | movement of one Embodiment of the information processing apparatus of this invention. It is a figure which shows the relationship between the serial Flash memory, RAM, and SDRAM in one Embodiment of the information processing apparatus of this invention. It is a figure which shows the reset cancellation | release system | strain in one Embodiment of the information processing apparatus of this invention. It is a block diagram which shows the structural example of the boot loader with which one Embodiment of the semiconductor integrated circuit device of this invention is provided.

Explanation of symbols

2. System LSI (One Embodiment of Semiconductor Integrated Circuit Device of the Present Invention)
3 ... Serial Flash memory 4 ... SDRAM
5 ... CPU
6 ... CPU bus 7 ... RAM
8 ... Boot loader 9 ... Memory controller 10 ... Transfer means 11 ... Counter 12 ... Reset release means 13 ... Register

Claims (6)

A serial interface non-volatile memory storing a boot program and a main program;
A first volatile memory;
A semiconductor integrated circuit device,
The semiconductor integrated circuit device includes:
CPU,
A second volatile memory;
After the system reset is released, the boot program in the nonvolatile memory is copied to the second volatile memory, and when the copying is completed, the nonvolatile memory interface for releasing the reset of the CPU is provided. Prepared,
The boot program is read from the nonvolatile memory, the read boot program is executed to copy the main program in the nonvolatile memory to the first volatile memory, and the copied main program is An information processing apparatus that executes the information processing apparatus. When the reset is released by the interface, the CPU executes the boot program copied to the second volatile memory to transfer the main program in the nonvolatile memory to the first volatile memory. The information processing apparatus according to claim 1, wherein the information processing apparatus is copied. The interface is
A register for storing a program size described in the boot program;
A counter for counting a transfer amount of the boot program from the nonvolatile memory to the second volatile memory;
Transfer means for ending transfer of the boot program from the nonvolatile memory to the second volatile memory when the count value of the counter reaches the program size stored in the register;
The information processing apparatus according to claim 2, further comprising: A semiconductor integrated circuit device to which a serial interface nonvolatile memory storing a boot program and a main program and a first volatile memory are connected,
With boot means,
The boot means includes
CPU,
A second volatile memory;
Copying the boot program in the non-volatile memory to the second volatile memory, and when the copying is completed, an interface for the non-volatile memory that releases the reset of the CPU, and
A semiconductor integrated circuit comprising: reading the boot program from the nonvolatile memory; and executing the read boot program to copy the main program in the nonvolatile memory to the first volatile memory. apparatus. When the reset is released by the interface, the CPU executes the boot program copied to the second volatile memory to transfer the main program in the nonvolatile memory to the first volatile memory. The semiconductor integrated circuit device according to claim 4, wherein the semiconductor integrated circuit device is copied to a semiconductor device. The interface is
A register for storing a program size described in the boot program;
A counter that counts the copy size of the boot program in the non-volatile memory to the second volatile memory;
Transfer means for ending transfer of the boot program from the nonvolatile memory to the second volatile memory when the count value of the counter reaches the program size stored in the register;
The semiconductor integrated circuit device according to claim 5, comprising:

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