JP2009164538A - Threshold voltage calculation method, threshold voltage calculation program, and threshold voltage calculation device - Google Patents

Abstract

A transistor threshold voltage is extracted by a short-time measurement regardless of an error factor.
A threshold voltage focused on the rate of increase of inversion carriers is defined and extracted. First, the drain current with respect to the increase in the gate voltage of the detection target transistor is measured (step S1). Next, the increment of the gate voltage with respect to the increment of the drain current is calculated (step S2). Next, the increase rate prepared in advance is compared with the calculation result, and it is determined whether or not the calculation result exceeds the increase rate (S _th ) prepared in advance (step S3). Then, the gate voltage when the increase rate is exceeded is set to the threshold voltage of the detection target transistor (step S4).
[Selection] Figure 1

Description

  The present invention relates to a threshold voltage calculation method, a threshold voltage calculation program, and a threshold voltage calculation device, and more particularly to a threshold voltage calculation method, a threshold voltage calculation program, and a threshold voltage calculation device that calculate a threshold voltage of a transistor.

  If the threshold voltage used as a boundary is well defined when the transistor changes from an off state (a state where drain current does not flow) to an on state (a state where drain current flows), what happens to the overall characteristics of the transistor? Can be easily grasped, and it is easy to calculate how the circuit operates. In addition, by grasping variations in threshold voltages of a large number of transistors, it is possible to know whether the operation timing of the integrated circuit is desired. That is, threshold voltage variation is an important indicator in timing design. Thus, it is known that the threshold value is convenient and important for expressing the transistor characteristics.

For this reason, various threshold value defining methods are known (see, for example, Patent Documents 1 and 2).
For example, (1) I _ds / W = I _th (where I _th is a constant value) a method of defining a gate voltage V _g as a threshold voltage (hereinafter referred to as method (A)), or (2) I _ds × L / W = I _th (where I _th is a constant value) A method of defining a gate voltage V _g as a threshold voltage (hereinafter referred to as method (B)), or (3) a maximum mutual conductance GMMax A method (hereinafter referred to as method (C)) of defining a threshold voltage from an intercept of I _ds = 0 by drawing an extrapolation line of the I _ds -V _g curve from the given gate voltage V _g, or (4) d ( An extrapolation of the (I _ds ^1/2 ) -V _g curve from the gate voltage V _g giving the maximum value of I _ds ^1/2 ) / dV _gMax is drawn, and from the intercept of (I _ds ^1/2 ) = 0 A method for defining a threshold voltage (hereinafter referred to as method (D)) is known. Note that _Ids is a drain current, W is a gate width, and L is a gate length. Also, β = 2 (d (I _ds ^1/2 ) / dV _g ) ² is given, and the method (D) is sometimes called βMax extrapolation.
JP-A-6-252395 Japanese Patent No. 36553485

  As transistor miniaturization progresses, particularly in the 90 nm process generation and beyond, variations in threshold voltage occur between adjacent and identically shaped transistors due to fluctuations in the state of impurities contained in the semiconductor.

FIG. 8 is a diagram illustrating how the threshold voltage varies.
The I _ds -V _g characteristics of four transistors having the same shape are measured. In FIG. 8, the broken line indicates the result measured with the drain voltage V _d = 0.1 V, and the solid line indicates the result measured with the drain voltage V _d = 1.2 V. The right axis is a linear axis, and the left axis is a logarithmic axis. A dotted line is an example of a current value that gives a definition in the case of method (A) or method (B), that is, a case where a constant current is defined.

  The variation on the linear axis is 10 mV or less, and the variation hardly affects the circuit characteristics, but there is a variation of about 100 mV in the current-defined threshold voltage in the subthreshold region.

  Along with the recent miniaturization of transistors, as a factor of variation in threshold voltage, a portion caused by the number and position of impurities has become larger in both threshold shift amount and appearance probability. Therefore, it is important to correctly evaluate the variation in the threshold voltage due to the impurity concentration. Therefore, it is necessary to specify whether this variation is due to the impurity concentration or due to other causes. For this reason, it is preferable that the threshold voltage does not vary depending on factors other than the impurity concentration.

  In this regard, in the methods (A) to (D) described above, the threshold voltage varies due to factors other than the difference in impurity concentration due to measurement errors of other parameters used to define the threshold voltage. There is a problem.

(1) Since the method (A) uses the gate width W in the definition, it is affected by an evaluation error of the gate width W; the corresponding part of the I _ds -V _g curve differs depending on the gate length L; When the hump characteristic appears in the sub-threshold region of the I _ds -V _g curve, the hump characteristic is greatly affected; in addition, there is a problem that the threshold voltage and the behavior in the linear plot are too different.

(2) The method (B) is less affected by the gate length L than the method (1), but has a problem of being affected by an evaluation error of the gate length L.
(3) Method (C) can be used only when the drain voltage V _d is very small (linear region); in the case of a short channel, it is affected by the parasitic resistance R _sd ; the extrapolation makes the extraction unstable. In addition, there is a problem that the measurement time becomes long because it is necessary to perform sweep measurement in a wide range of the I _ds -V _g curve.

(4) The method (D) can be used only when the drain voltage V _d is sufficiently large (saturation region); and since it is necessary to perform sweep measurement over a wide range of the I _ds -V _g curve, the measurement time is long. There is a problem of becoming.

  The present invention has been made in view of the above points, and is hardly influenced by other error factors, and it is possible to pay attention to the increase rate of inversion carriers, a threshold voltage calculation method, a threshold voltage calculation program, and a threshold voltage calculation. An object is to provide an apparatus.

In order to achieve the above object, a threshold voltage calculation method for calculating a threshold voltage of a transistor is provided. This calculation method includes the following steps.
(1) A step in which the measuring device measures a drain current with respect to an increase in the gate voltage of the detection target transistor.

(2) The arithmetic unit calculates the increment of the gate voltage with respect to the logarithmic increment of the drain current.
(3) A step in which the arithmetic device determines whether or not the arithmetic result exceeds an increase rate prepared in advance.

(4) A step in which the arithmetic unit sets the gate voltage when the increase rate is exceeded to the threshold voltage of the detection target transistor.
According to such a threshold voltage calculation method, the drain current with respect to the increase in the gate voltage is measured by the measuring device. An arithmetic unit calculates an increase in gate voltage relative to a logarithmic increase in drain current. And it is judged whether the calculation result exceeded the increase rate prepared beforehand. Then, the gate voltage when the increase rate is exceeded is set to the threshold voltage of the detection target transistor.

  According to the disclosed threshold voltage calculation method, threshold voltage calculation program, and threshold voltage calculation device, it is possible to focus on the rate of increase of the inverted carrier, almost without being influenced by other error factors. Moreover, the measurement time can be shortened.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, an outline of the present invention will be described, and then an embodiment will be described.
FIG. 1 is a diagram showing an outline of the present invention.

The disclosed threshold voltage calculation method is a method of calculating a threshold voltage of a transistor, and is realized by a measurement device and a calculation device.
First, the measuring device measures the drain current with respect to the increase in the gate voltage of the detection target transistor (step S1).

Next, the arithmetic unit calculates the increase in the gate voltage with respect to the logarithmic increase in the drain current (step S2).
Next, the calculation device compares the increase rate prepared in advance with the calculation result, and determines whether or not the calculation result exceeds the increase rate (Slope) prepared in advance (step S3). An example of this increase rate is 0.20 V / decade.

Then, the arithmetic device sets the gate voltage when the increase rate is exceeded to the threshold voltage of the detection target transistor (step S4).
According to such a threshold voltage calculation method, the drain current with respect to the increase in the gate voltage is measured by the measuring device. The arithmetic unit calculates the increase in the gate voltage relative to the increase in the drain current. And it is judged whether the calculation result exceeded the increase rate prepared beforehand. Then, the gate voltage when the increase rate is exceeded is set to the threshold voltage of the detection target transistor.

Embodiments of the present invention will be described below.
FIG. 2 is a diagram illustrating a hardware configuration example of the measurement system.
The measurement system 500 includes a computer 100, a measurement device 200, and a prober 300.

  The computer 100 is entirely controlled by a CPU (Central Processing Unit) 101. A random access memory (RAM) 102, a hard disk drive (HDD) 103, a graphic processing device 104, an input interface 105, and an interface 106 are connected to the CPU 101 via a bus 107.

  The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 stores various data necessary for processing by the CPU 101. The HDD 103 stores an OS and application programs. A program file is stored in the HDD 103.

  A monitor 11 is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 11 in accordance with a command from the CPU 101. A keyboard 12 and a mouse 13 are connected to the input interface 105. The input interface 105 transmits a signal transmitted from the keyboard 12 or the mouse 13 to the CPU 101 via the bus 107.

The interface 106 is connected to the measuring device 200 and the prober 300. The interface 106 transmits / receives data to / from other computers.
The measuring device 200 is a device that performs current-voltage control and current-voltage measurement, and has a minute current measuring function, a minute voltage measuring function, and the like.

Although it does not specifically limit as the measuring apparatus 200, For example, the structure by a semiconductor parameter analyzer, a switching matrix, etc. are mentioned.
The prober 300 is used for testing each chip area in a wafer state before an assembly process for manufacturing an LSI. The prober 300 inputs a test signal to the electrode part (the upper surface of the Al pad, Au bump, solder bump, etc.) of the chip area, which is the measurement area, via the probe of a probe card (not shown). Further, a result signal is acquired from the electrode unit and sent to the measuring apparatus 200. The measurement data is sent to the computer 100 via a GPIB (General Purpose Interface Bus) board, graphed, and displayed on the monitor 11.

Next, a measurement method using the measurement system 500 will be described.
FIG. 3 is a flowchart showing a measurement method using the measurement system.
First, the measurement device 200 applies with increasing gate voltage V _g based on the source to the gate terminal of the measured transistor (step S11).

Next, the measuring apparatus 200 measures the drain current _Ids flowing through the measurement target transistor (step S12).
Next, the computer 100 calculates Slope from the increasing rate of I _ds −V _g (step S13). This calculation process will be described later.

Next, the computer 100 determines whether or not the calculated Slope exceeds a preset set value (step S14). If it does not exceed the set value (No in step S14), and proceeds to step S11, it continues to perform step S11 and subsequent steps are the gate voltage V _g is increased from the previous.

On the other hand, when the set value is exceeded (Yes in step S14), the threshold voltage V _thsl is calculated (step S15). The process ends here.
Next, the processing for calculating Slope in step S13 and the processing for calculating threshold voltage V _thsl in step S15 will be described in detail.

In the present embodiment, the slope is calculated using the following equation (1).
Slope = dV _g / dlog ₁₀ I _ds (1)
Further, the threshold voltage V _thsl is set to the threshold voltage V _thsl with the gate voltage V _{g in} which the Slope obtained by the equation (1) matches the preset value prepared in advance.

For example, when the setting value prepared in advance is 0.20 [V / decade], the gate voltage V _g that satisfies Slope = 0.20 [V / decade] is defined as the threshold voltage V _thsl 0.2. In this way, the value of Slope defining V _thsl is hereinafter referred to as S _th .

Similarly, the gate voltages V _g at which S _th = 0.30, 0.40, 0.50 [V / decade] are defined as V _thsl 0.3, V _thsl 0.4, and V _thsl 0.5, respectively. .
Accordingly, it is possible to focus only on the rate of increase of the inverted carriers, hardly depending on other error factors such as the gate length L, the gate width W, the capacitance C _OX , the mobility, and the hump.

The value of the threshold voltage V _thsl is not particularly limited, but is preferably 0.1 to 0.5, more preferably 0.2 to 0.5, and 0.3 to 0.4. Is more preferable. By setting the threshold voltage V _thsl in this way, other error factors can be surely eliminated, and the value becomes close to the existing threshold voltage definition (for example, methods (A) to (D)). In other words, if _Sth is too small, it is easily affected when hump characteristics or punch-through characteristics appear in the subthreshold region of the I _ds -V _g curve. On the other hand, if _Sth is too large, it is far from the threshold voltage value according to the existing threshold voltage definition.

FIG. 4 is a diagram illustrating a threshold voltage determination method according to the present embodiment.
For reference, the gate inversion capacitance C _inv is shown.
In FIG. 4, the black circle plot represents the measured drain current I _ds , and the solid line represents the model value of I _{ds obtained by} adjusting the model parameters so as to reproduce the measured value of the drain current I _ds based on the compact model of the transistor. It is.

The value of Slope gate voltage _{V g} is in the vicinity of 0V (about 0.07), the so-called sub-threshold slope: are called (subsreshold slope S value).
The right scale in FIG. 4 represents the slope scale, and of the two scales provided on the left side, the inner scale represents the drain current I _ds scale, and the outer scale represents the gate inversion capacitance C _inv. The scale is shown.

Next, the relationship of the threshold voltage due to the difference in the gate length of the transistor will be described.
FIG. 5 is a diagram illustrating a relationship of threshold voltages depending on a difference in gate length of a transistor.
In FIG. 5, actually measured dV _g / log (I _ds ) in each transistor having different gate lengths is plotted as [V / decade].

In FIG. 5, a1 is a gate inversion capacitance C _inv with a gate length of 540 nm, b1 is a Slope with a gate length of 540 nm, and c1 is a model value of I _{ds with} a gate length of 540 nm. Further, a2 is a gate inversion capacitance C _inv with a gate length of 220 nm, b2 is a slope with a gate length of 220 nm, and c2 is a model value of I _{ds with} a gate length of 220 nm. Further, a3 is a gate inversion capacitance C _inv with a gate length of 140 nm, b3 is a slope with a gate length of 140 nm, and c3 is a model value of I _{ds with} a gate length of 140 nm. Further, a4 is a gate inversion capacitance C _inv with a gate length of 110 nm, b4 is a slope with a gate length of 110 nm, and c4 is a model value of I _{ds with} a gate length of 110 nm. Further, a5 is a gate inversion capacitance C _inv with a gate length of 90 nm, b5 is a slope with a gate length of 90 nm, and c5 is a model value of I _{ds with} a gate length of 90 nm.

The difference in drain current value due to the difference in gate length is mainly due to the parasitic resistance R _sd between the source and drain. On the other hand, with the threshold voltage obtained by the measurement method of the present embodiment, the influence of the parasitic resistance R _sd can be eliminated. That is, FIG. 4 shows that Slope is substantially constant regardless of the gate length L in the vicinity of the threshold voltage V _thsl . The reason is shown below.

Based on the compact model of the transistor, near the threshold voltage V _thsl ,
I _ds = U ₀ · V _ds · V _geff (2)
It becomes. Here, U ₀ is given by U ₀ = μ ₀ WC _OX / L, and indicates a constant obtained by converting the electric field mobility μ ₀ .

Taking the log on both sides of equation (2), the following equation (3) is obtained.
log I _ds = log U ₀ + log V _ds + log _{V geff} (3)
When both sides of Equation (3) are differentiated, logU ₀ + logV _{ds on} the right side is a constant, and thus becomes 0 by differentiation. Only the part depending on the shape of the curve of I _ds -V _g remains.

Accordingly, the shape of the curve becomes a substantially constant value near the threshold voltage V _{thsl regardless} of the gate length L, the gate width W, the gate capacitance C _OX , and the electric field mobility μ ₀ .
Next, the result of measuring the threshold voltage of the pMOS transistor using the threshold voltage determination method of the present embodiment will be described.

FIG. 6 is a diagram showing the measurement results of the pMOS transistor. In FIG. 6, the corresponding measurement results in FIG. 5 are denoted by the same reference numerals as in FIG.
Not fully lower the value of the Slope at a small area of the gate voltage _{V g} to the gate length L = 90 nm gone is affected slightly punchthrough characteristics but, nMOS transistors Similarly, the shape of the curve in the vicinity of the threshold voltage _{V Thsl} Regardless of the gate length L, the value is almost constant.

Incidentally, when comparing the gate inversion capacitance _{C inv} and the threshold voltage _{V Thsl,} it has become a threshold voltage _{V Thsl} was reached 80% to 9% of the maximum value of the gate inversion capacitance _{C inv.}
Next, an example in which the measurement results of the threshold voltage measurement method of this embodiment and the other methods are compared is shown.

FIG. 7 is a diagram illustrating a comparative example.
The threshold voltage measured by another method (method (A), method (B), method (D)) and the threshold voltage obtained by the threshold voltage measurement method of this embodiment (S _th = 0.4) In order to evaluate the variation, the threshold voltage in each method is measured at multiple points, and the standard deviation of the measured threshold voltage is obtained.

The threshold voltage measurement method and method (D) of the present embodiment have smaller variations than the methods (A) and (B). Therefore, these methods are more preferable as the threshold voltage measurement method.
Furthermore, the threshold voltage measurement method of the present embodiment requires a shorter measurement time than method (D). Therefore, it can be said that the threshold voltage measurement method of the present embodiment is most suitable for variation evaluation.

As described above, according to the measurement system 500 of the present embodiment, the gate voltage V _{g in} which the Slope obtained by the equation (1) matches the preset setting value is set to the threshold voltage V _thsl. Therefore, it is possible to focus on the increasing rate of the inversion carriers almost without being influenced by other error factors such as the gate length L, the gate width W, the capacitance C _{OX of the} oxide film, the mobility, and the hump.

Further, it is possible to evaluate the common regardless of the value of the drain voltage V _d.
Further, the same evaluation standard can be given regardless of the gate length L.
Also, the extraction is very stable because a large part of I _ds −V _g is used and no extrapolation is used.

Therefore, when the threshold voltage variation of the narrow channel is evaluated, when the threshold voltage V _thsl is compared with the threshold voltage of the method (A), the threshold voltage V _thsl is not affected by the variation of the gate width W. It is possible to easily determine the difference between the variation in the impurity concentration and the variation in the impurity concentration.

Similarly, when evaluating variation in threshold voltage of a device having a hump characteristic in the subthreshold region of the I _ds -V _g curve, it is easy to determine the difference between variation in hump or variation in impurity concentration. Can do.

Similarly, when the threshold voltage V _thsl is compared with the threshold voltage of the method (C), the threshold voltage V _thsl is not affected by the dependence of the mobility on the gate voltage V _g and the variation of the parasitic resistance R _sd . The difference between the parasitic resistance R _sd variation and the impurity concentration variation can be easily determined. Further, it can be easily determined whether or not the influence of the GMMax extraction error and the variation of the parasitic resistance R _sd can be ignored.

In general, in the extrapolation method (method (C), method (D), ie, using GMMax, βMax), the sweep of I _ds -V _g cannot be omitted in the measurement, and the measurement time becomes long. According to the measurement method of this form, the _slope value is sequentially obtained at the time of measurement, and when the set value is exceeded, the threshold voltage V _thsl is calculated, so that the sweep can be terminated in the middle, greatly increasing the measurement time. Can be shortened.

Moreover, this measurement method is suitable for evaluation on a linear scale of I _ds −V _g and is preferable as a threshold voltage definition used for circuit evaluation.
As described above, the threshold voltage calculation method, the threshold voltage calculation program, and the threshold voltage calculation apparatus of the present invention have been described based on the illustrated embodiment, but the present invention is not limited to this, and the configuration of each unit is as follows. Any structure having a similar function can be substituted. Moreover, other arbitrary structures and processes may be added to the present invention.

In addition, the present invention may be a combination of any two or more configurations (features) of the above-described embodiments.
The above processing functions can be realized by a computer. In that case, a program describing the processing contents of the functions that the computer 100 should have is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic recording device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic recording device include a hard disk device (HDD), a flexible disk (FD), and a magnetic tape. Examples of the optical disc include a DVD (Digital Versatile Disc), a DVD-RAM (Random Access Memory), a CD-ROM (Compact Disc Read Only Memory), and a CD-R (Recordable) / RW (ReWritable). Examples of the magneto-optical recording medium include MO (Magneto-Optical disk).

  When distributing the program, for example, a portable recording medium such as a DVD or a CD-ROM in which the program is recorded is sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the threshold voltage calculation program stores, for example, a program recorded on a portable recording medium or a program transferred from a server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time the program is transferred from the server computer, the computer can sequentially execute processing according to the received program.

Regarding the above embodiment, the following additional notes are disclosed.
(Supplementary Note 1) In a threshold voltage calculation method for calculating a threshold voltage of a transistor,
A measuring device measuring a drain current with respect to an increase in a gate voltage of a detection target transistor;
A computing device computing the increment of the gate voltage relative to the logarithmic increment of the drain current;
A step of determining whether or not the result of the calculation exceeds an increase rate prepared in advance;
Setting the gate voltage when the arithmetic unit exceeds the increase rate to a threshold voltage of the detection target transistor;
A threshold voltage calculation method characterized by comprising:

(Additional remark 2) The said increase rate prepared previously is 0.1-0.5, The threshold voltage calculation method of Additional remark 1 characterized by the above-mentioned.
(Supplementary note 3) The threshold voltage calculation method according to supplementary note 1, wherein the drain current is measured while calculating the increase rate.

(Additional remark 4) In the threshold voltage calculation program which calculates the threshold voltage of a transistor using the drain current with respect to the increase in the gate voltage of the detection object transistor measured by the measuring apparatus,
On the computer,
Calculating an increment of the gate voltage relative to a logarithmic increment of the drain current;
Determining whether the result of the calculation exceeds a pre-prepared increase rate; and
Setting the gate voltage when the increase rate is exceeded to the threshold voltage of the detection target transistor;
The threshold voltage calculation program characterized by performing this.

(Additional remark 5) In the threshold voltage calculating apparatus which calculates the threshold voltage of a transistor using the drain current with respect to the increase in the gate voltage of the detection object transistor measured by the measuring apparatus,
Calculating an increment of the gate voltage relative to a logarithmic increment of the drain current;
It is determined whether the result of the calculation has exceeded a prepared increase rate,
Setting the gate voltage when the increase rate is exceeded to the threshold voltage of the transistor to be detected;
A threshold voltage calculation device characterized by the above.

(Additional remark 6) In the threshold voltage calculation system which calculates the threshold voltage of a transistor,
A measuring device for measuring a drain current with respect to an increase in a gate voltage of a detection target transistor;
Calculating an increment of the gate voltage with respect to a logarithmic increment of the drain current, determining whether a result of the calculation exceeds a predetermined increase rate, and determining the gate voltage when the increase rate is exceeded; An arithmetic unit for setting the threshold voltage of the detection target transistor;
A threshold voltage calculation system comprising:

It is a figure which shows the outline | summary of this invention. It is a figure which shows the hardware structural example of a measurement system. It is a flowchart which shows the measuring method using a measuring system. It is a figure which shows the determination method of the threshold voltage of this Embodiment. It is a figure which shows the relationship of the threshold voltage by the difference in the gate length of a transistor. It is a figure which shows the measurement result of a pMOS transistor. It is a figure which shows a comparative example. It is a figure which shows a mode that a threshold voltage varies.

Explanation of symbols

100 Computer 200 Measuring Device 300 Prober 500 Measuring System

Claims (5)

In a threshold voltage calculation method for calculating a threshold voltage of a transistor,
A measuring device measuring a drain current with respect to an increase in a gate voltage of a detection target transistor;
A computing device computing the increment of the gate voltage relative to the logarithmic increment of the drain current;
A step of determining whether or not the result of the calculation exceeds an increase rate prepared in advance;
Setting the gate voltage when the arithmetic unit exceeds the increase rate to a threshold voltage of the detection target transistor;
A threshold voltage calculation method characterized by comprising:   The threshold voltage calculation method according to claim 1, wherein the increase rate prepared in advance is 0.1 to 0.5.   The threshold voltage calculation method according to claim 1, wherein the drain current is measured while calculating the increase rate. In a threshold voltage calculation program for calculating a threshold voltage of a transistor using a drain current with respect to an increase in a gate voltage of a detection target transistor measured by a measurement device,
On the computer,
Calculating an increment of the gate voltage relative to a logarithmic increment of the drain current;
Determining whether the result of the calculation exceeds a pre-prepared increase rate; and
Setting the gate voltage when the increase rate is exceeded to the threshold voltage of the detection target transistor;
The threshold voltage calculation program characterized by performing this. In the threshold voltage calculation device that calculates the threshold voltage of the transistor using the drain current with respect to the increase in the gate voltage of the detection target transistor measured by the measurement device,
Calculating an increment of the gate voltage relative to a logarithmic increment of the drain current;
It is determined whether the result of the calculation has exceeded a prepared increase rate,
Setting the gate voltage when the increase rate is exceeded to the threshold voltage of the transistor to be detected;
A threshold voltage calculation device characterized by the above.

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