JP2009164453A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

For example, a semiconductor device capable of reducing leakage current (standby current) without reducing switching speed in a highly integrated circuit such as SRAM, and a method of manufacturing the same are provided.
A first transistor structure Q1 and a second transistor structure Q2 share a source / drain region 15b. The gate electrode 20 of the first transistor structure Q1 is composed of W (tungsten), while the gate electrode 10 of the second transistor structure Q2 is composed of n-type Si, so that the work function of W (tungsten) is n Since it is larger than the work function of type Si, the threshold voltage of the first transistor structure Q1 is higher than the threshold voltage of the second transistor structure Q2.
[Selection] Figure 13

Description

  The present invention relates to a semiconductor integrated circuit having a fine gate electrode, for example, a semiconductor device such as an SRAM (Static Random Access Memory), and a manufacturing method thereof.

  Reduction of the gate length is indispensable for high integration of LSI (Large Scale Integrated Circuit). However, when the gate length is shortened, an increase in leakage current between the source and the drain becomes a problem. If the Vth (threshold voltage) of the transistor is set high, the leakage current between the source and drain is reduced.

  However, since Vth is determined by the well concentration, it is necessary to increase all Vth of transistors in the same well in order to reduce the leakage current. As a result, the on-current of the transistor is lowered, and the switching speed is lowered.

  For example, in an SRAM, it is easier to integrate a transistor for driving a flip-flop and a writing / reading transistor in the same WELL. However, the driving transistor is preferably as the on-current is higher, and operates at a higher speed. On the other hand, it is preferable that the writing / reading transistor has less leakage current.

  As a countermeasure, it is possible to increase Vth only for a specific transistor by locally injecting a dopant into the substrate using a mask different from WELL formation. However, there arises a problem that the variation in Vth increases due to the change in the dopant concentration.

  On the other hand, Patent Document 1 below proposes a method of controlling Vth of a CMOS device using a work function of a gate electrode material. According to this document, a transistor structure having a dummy gate electrode is formed using a normal process, then an interlayer film is formed, the interlayer film is polished to the upper surface of the gate electrode, and then a PMOS transistor and an NMOS transistor A technique is described in which both dummy gate electrodes are replaced with metal, which is another material.

US Pat. No. 6,291,282 B1

  It is possible to change the work function of the gate electrode by selectively replacing the gate electrode material with a mask having openings corresponding to the individual gate electrode shapes.

  However, when there is a layout in which two gate electrodes are arranged close to each other at a minute interval like an SRAM, the work function of one or both of two adjacent gate electrodes will be changed by selective replacement using a mask. Then, due to mask misalignment, there is a possibility that the adjacent contact and the gate come into contact with each other, and the yield decreases. In addition, since the number of steps for forming the mask increases, there is a problem that the manufacturing cost increases.

  An object of the present invention is to reduce the leakage current (standby current) without lowering the switching speed in a highly integrated circuit such as SRAM, for example, by setting the operating characteristics of two adjacent transistors separately. A semiconductor device and a method for manufacturing the same are provided.

  According to an embodiment of the present invention, of two adjacent transistors, one source region and the other drain region are formed as the same impurity diffusion region, and the threshold voltages of the transistors are different from each other.

  The threshold value of each transistor can be set to a desired value by changing the work function of the material constituting the gate electrode.

  Further, the gate electrodes of two adjacent transistors may be arranged at the minimum pitch of the wiring design rule.

  When applied to an SRAM cell, the drive transistor and the access transistor of the flip-flop circuit may be adjacent to each other so that the threshold voltages of the transistors are different from each other.

  According to another aspect of the present invention, of two adjacent transistors, one gate electrode is patterned using a hard mask made of an oxide film, and the other gate electrode is patterned using a resist film. Do.

  According to this embodiment, since the threshold voltages of two adjacent transistors are different from each other, the leakage current between the source and the drain, the on-current, the switching speed, and the like can be individually set. By applying this method to, for example, a highly integrated circuit such as SRAM, the leakage current (standby current) can be reduced without reducing the switching speed.

  Further, by patterning the gate electrodes of the two transistors using a hard mask and a resist film, adjacent gate electrodes can be formed with a minimum pitch.

Embodiment 1 FIG.
1 to 13 are sectional views showing an example of a method for manufacturing a semiconductor device according to the present invention. First, as shown in FIG. 1, a protective thin oxide film 1 made of SiO ₂ or the like is formed on a semiconductor substrate such as Si (silicon) by oxidation, and then a well region 2 is formed by ion implantation. To do. Next, after removing the oxide film 1, as shown in FIG. 2, an oxide film 3 made of SiO ₂ or the like is formed, and then a high dielectric constant film 4 made of, for example, HfO ₂ or the like is formed.

Next, as shown in FIG. 3, a conductive layer 5 in which P (phosphorus) is doped into Si is formed on the high dielectric constant film 4 as a gate electrode material, and subsequently, SiO ₂ as a hard mask material. An oxide film 6 made of or the like is formed.

  Next, as shown in FIG. 4, the oxide film 6 is patterned by photolithography to form a hard mask 7. Next, after coating the entire surface of the resist, patterning is performed by photolithography to form a resist film 8. At this time, the position of the hard mask 7 corresponds to the gate electrode of the first transistor structure, while the position of the resist film 8 corresponds to the gate electrode of the second transistor structure.

  Next, as shown in FIG. 5, the exposed portions of the conductive layer 5 that are not covered with the hard mask 7 and the resist film 8 are removed by etching, and gate electrodes 9 and 10 are formed, respectively. Then, the resist film 8 located on the gate electrode 10 is removed so that the hard mask 7 located on the gate electrode 9 remains.

Next, as shown in FIG. 6, an oxide film 11 made of SiO ₂ or the like is entirely formed on the upper surface of the substrate, the sidewalls and upper surfaces of the gate electrode 9 and the hard mask 7, and the sidewalls and upper surfaces of the gate electrode 10 by film formation. To form.

  Next, after an insulating film made of SiN or the like is formed on the entire surface of the oxide film 11, a dry etching process is performed, and the gate electrode 9 and the side walls of the hard mask 7 and the gate electrode 10 are formed as shown in FIG. The oxide film 11 and the insulating film at locations other than the sidewalls are removed, and the sidewall oxide film 11a and the sidewall insulating film 12 are formed.

  Next, as shown in FIG. 8, after the source / drain extension 13 is formed by ion implantation, the sidewall insulating film 14 made of SiN or the like is formed on the sidewalls of the gate electrode 9 and the hard mask 7 and the sidewalls of the gate electrode 10. Form. Subsequently, a source region 15a having a first transistor structure, a source / drain region 15b, and a drain region 15c having a second transistor structure are formed by ion implantation. The source / drain region 15b functions as a drain region of the first transistor structure and a source region of the second transistor structure.

  Here, the source region and the drain region in the transistor structure are determined according to the potential of each region with respect to the gate electrode during operation, and if set to the opposite potential, the source region becomes the drain and the drain region becomes the source It is also possible to function as.

  Subsequently, Ni (nickel) diffusion treatment is performed to form a Ni silicide film 16 on each exposed surface of the source region 15 a, the source / drain region 15 b, the drain region 15 c, and the gate electrode 10.

  Next, as shown in FIG. 9, an interlayer insulating film 17 made of SiN or the like is formed on the entire surface.

  Next, as shown in FIG. 10, an interlayer insulating film 18 made of SiN or the like is formed on the entire surface of the interlayer insulating film 17, and then a planarization process such as CMP (Chemical Mechanical Polishing) is performed to form a hard mask. The interlayer insulating films 17 and 18 are partially polished until 7 is exposed.

  Next, as shown in FIG. 11, selective etching is performed to remove only the exposed hard mask 7, and then selective etching is performed to remove the gate electrode 9.

  Next, as shown in FIG. 12, W (tungsten) is buried in the gate opening 19 from which the gate electrode 9 has been removed, and a planarization process such as CMP is performed to form the gate electrode 20.

  Next, as shown in FIG. 13, after an interlayer insulating film 21 made of SiN or the like is formed, a contact hole 22 is opened, W (tungsten) is buried in the contact hole 22, and a contact plug is formed thereon. A wiring layer 23 is formed on the substrate.

  Thus, the gate electrode 20 of the left first transistor structure Q1 is made of W (tungsten), while the gate electrode 10 of the right second transistor structure Q2 is made of P-doped n-type Si. be able to. The work function of W (tungsten) is larger than that of n-type Si. As a result, the threshold voltage of the first transistor structure Q1 is higher than the threshold voltage of the second transistor structure Q2.

  FIG. 14A is a circuit diagram showing an example of an SRAM cell, and FIG. 14B is a layout diagram of the SRAM cell. The SRAM cell shown in FIG. 14A includes six transistors.

  A first series circuit including a load transistor P1 and a drive transistor Nd1 is connected between power supply lines Vcc and Vss. A second series circuit including the load transistor P2 and the drive transistor Nd2 is connected between the power supply lines Vcc and Vss. The output side of the first series circuit is connected to the gates of the load transistor P2 and the drive transistor Nd2, and the output side of the second series circuit is connected to the gates of the load transistor P1 and the drive transistor Nd1, It is composed.

  An access transistor Na1 is connected between the output side of the first series circuit and the bit line B, and the gate of the access transistor Na1 is connected to the word line W. The access transistor Na2 is connected between the output side of the second series circuit and the inverted bit line IB, and the gate of the access transistor Na2 is connected to the word line W.

  Referring to FIG. 14B, the access transistors Na1 and Na2 have a first transistor structure Q1 having a gate electrode 20 made of W (tungsten), as shown in FIG. As shown in FIG. 13, the drive transistors Nd1 and Nd2 have a second transistor structure Q2 including a gate electrode 10 made of n-type Si.

  The access transistor Na1 and the drive transistor Nd1 are arranged adjacent to each other and share the source / drain region 15b shown in FIG. Similarly, the access transistor Na2 and the drive transistor Nd2 are arranged adjacent to each other and share the source / drain region 15b shown in FIG.

  The load transistors P1 and P2 have a second transistor structure Q2 including a gate electrode 10 made of n-type Si.

  The gate electrodes of each transistor structure are arranged at a predetermined pitch according to the wiring design rules. Among them, the gate electrode of the access transistor Na1 and the gate electrode of the drive transistor Nd1 are adjacently arranged at the minimum pitch, and similarly, the gate electrode of the access transistor Na2 and the gate electrode of the drive transistor Nd2 are adjacently arranged at the minimum pitch. The degree of integration of SRAM can be increased.

  Since access transistors Na1 and Na2 have gate electrodes made of W (tungsten), their threshold voltages are higher than those of drive transistors Nd1 and Nd2 having gate electrodes made of n-type Si. Therefore, leakage current (standby current) in access transistors Na1 and Na2 can be reduced. On the other hand, since the ON currents of the drive transistors Nd1 and Nd2 remain the same as before, it is possible to prevent the switching speed from decreasing.

  In the above description, the 6-transistor type SRAM cell is illustrated, but the present invention can also be applied to a 4-transistor type SRAM cell in which the load transistors P1 and P2 are replaced by resistance elements.

  The present invention is extremely useful industrially in that a semiconductor device having desired operating characteristics can be realized with a high degree of integration.

It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on this invention. FIG. 14A is a circuit diagram showing an example of an SRAM cell, and FIG. 14B is a layout diagram of the SRAM cell.

Explanation of symbols

1 oxide film, 2 well region, 3 oxide film, 4 high dielectric constant film, 5 conductive layer,
6 oxide film, 7 hard mask, 8 resist film, 9, 10 gate electrode,
11 oxide film, 11a sidewall oxide film, 12 sidewall insulating film,
13 source / drain extension, 14 sidewall insulating film,
15a source region, 15b source / drain region, 15c drain region,
16 Ni silicide film, 17, 18 interlayer insulation film, 19 gate opening,
20 gate electrode, 21 interlayer insulation film, 22 contact hole,
23 wiring layer, Na1, Na2 access transistor,
P1, P2 load transistor, Nd1, Nd2 drive transistor.

Claims (7)

A semiconductor substrate;
A first transistor structure formed on a semiconductor substrate and having a first gate electrode, a first source region, and a first drain region;
A second transistor structure formed on a semiconductor substrate and having a second gate electrode, a second source region, and a second drain region;
The first source region and the second drain region are formed as the same region;
A semiconductor device, wherein the threshold voltage of the first transistor structure is different from the threshold voltage of the second transistor structure.   2. The semiconductor device according to claim 1, wherein a work function of a material constituting the first gate electrode is different from a work function of a material constituting the second gate electrode. The semiconductor device includes three or more transistor structures, and the gate electrodes of each transistor structure are arranged at a predetermined pitch.
The semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode are arranged at a minimum pitch. A semiconductor device includes a first series circuit including a first load element and a first drive transistor, and a flip-flop circuit including a second series circuit including a second load element and a second drive transistor;
A first access transistor connected to the output side of the first series circuit and the input side of the second series circuit;
An SRAM cell comprising a second access transistor connected to the output side of the second series circuit and the input side of the first series circuit,
The first driving transistor and the first access transistor have the first transistor structure and the second transistor structure, respectively.
The semiconductor device according to claim 1, wherein the second drive transistor and the second access transistor have the first transistor structure and the second transistor structure, respectively. Depositing an oxide film on the semiconductor substrate;
Depositing a first electrode material on the oxide film;
Forming a hard mask made of an oxide film and a resist film on the first electrode material;
Etching the first electrode material to form a first gate electrode corresponding to the hard mask and a second gate electrode corresponding to the resist film, respectively;
Removing the resist film so that the hard mask remains;
Forming a source region and a drain region in a semiconductor substrate;
Forming an interlayer film on the semiconductor substrate so as to cover each gate electrode;
Exposing the hard mask by partial polishing of the interlayer film;
Removing the exposed hard mask and first gate electrode;
And a step of burying a second electrode material in the removed portion to form a third gate electrode.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the work function of the first electrode material is different from the work function of the second electrode material.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the first electrode material is silicon and the second electrode material is tungsten.