JP2009164344A - Semiconductor testing device and semiconductor testing method - Google Patents

Abstract

Provided is a method for improving the test efficiency by optimizing the arrangement of two or more integrated circuits to be tested simultaneously.
A semiconductor device is formed on a semiconductor wafer by repeatedly performing the test using a probe card capable of simultaneously testing m (two or more natural number) integrated circuits on the semiconductor wafer. A semiconductor test apparatus for testing n (natural number greater than m) integrated circuits, the apparatus testing n integrated circuits formed on another semiconductor wafer close to the semiconductor wafer 8 A test time totaling unit 22 that totals the time distribution required for each integrated circuit, a multi-location determining unit 24 that determines the arrangement of m integrated circuits to be tested simultaneously with reference to the total time distribution, And a test execution unit 25 that repeatedly executes the test of the integrated circuit according to the determined arrangement. This optimizes the arrangement of two or more integrated circuits to be tested simultaneously and shortens the test time.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor test apparatus and a semiconductor test method for testing an integrated circuit formed on a semiconductor wafer using a probe card capable of simultaneously testing two or more integrated circuits.

  With the recent increase in the diameter of semiconductor wafers and the higher integration and reduction of semiconductor integrated circuits, the number of semiconductor products that can be manufactured from a single semiconductor wafer has increased, and manufacturing costs have been reduced. .

  On the other hand, not all semiconductor products formed on semiconductor wafers are good products, so it is common to screen defective products by testing the electrical characteristics of integrated circuits formed on semiconductor wafers. Has been done. This test is usually performed with a probe needle in contact with an electrode pad of an integrated circuit on a semiconductor wafer. As described above, when the number of semiconductor products increases, the time required for a test per semiconductor wafer also increases and the inspection cost increases.

  Therefore, in order to reduce the inspection cost, for example, a test for two or more integrated circuits can be performed simultaneously by bringing a probe needle into contact with electrode pads of a plurality of integrated circuits. Probe cards have been developed. By using the probe card for multi-probing, the number of integrated circuits to be tested at a time increases, so that the test time can be shortened and the inspection cost can be reduced.

In Patent Document 1, when a test is performed using an asymmetric probe card for multi-probing, a probe card having a symmetric location in software and a probe card having an asymmetric location are touched down ( A device has been disclosed in which the stress applied to the integrated circuit is made uniform by avoiding redundant inspection of the same integrated circuit by properly using each shot).
JP 2004-253585 A

  By the way, various test items are included in the integrated circuit test performed using the probe card, but it is not determined as good unless all of these test items pass, but even one of these test items fails. If so, the test is interrupted at that time and is determined to be defective. Therefore, the time required for the test is generally shorter for a defective product than for a good product.

  When two or more integrated circuits to be tested at the same time include a good product and a defective product, the probe needle that has tested the defective integrated circuit must wait for the test of the good product being performed at the same time to end. Test efficiency will be reduced. Accordingly, the test time required for one semiconductor wafer is also prolonged, and the inspection cost is increased.

  The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor test apparatus and a semiconductor test method with high test efficiency by optimizing the arrangement of two or more integrated circuits to be tested simultaneously. It is to be.

  A first feature of the present invention is that a test is repeatedly performed using a probe card capable of simultaneously testing m (two or more natural numbers) integrated circuits on a semiconductor wafer. A semiconductor test apparatus for testing n (natural number greater than m) integrated circuits formed, wherein the semiconductor test apparatus is formed on another semiconductor wafer adjacent to the semiconductor wafer. A test time counting unit that counts the distribution of time required for the test for each integrated circuit, a multi-placement determination unit that determines the placement of m integrated circuits to be tested at the same time with reference to the calculated time distribution, And a test execution unit that repeatedly executes the test of the integrated circuit according to the determined arrangement.

  The distribution of time required for testing each integrated circuit in two or more semiconductor wafers close to each other tends to approximate. If this tendency is used, the time distribution required for testing the n integrated circuits of the semiconductor wafer is predicted for each integrated circuit from the distribution of time required for testing the n integrated circuits of the other semiconductor wafers. can do. Therefore, the arrangement of m integrated circuits to be tested simultaneously is determined with reference to the distribution of time required for testing n integrated circuits formed on another semiconductor wafer adjacent to the semiconductor wafer. Thereby, the arrangement of two or more integrated circuits to be tested at the same time can be optimized, the test time per semiconductor wafer can be shortened, and the inspection cost can be suppressed.

  In the first feature of the present invention, the multi-placement determining unit is used to test n integrated circuits in a group of m integrated circuits that can be taken with respect to n integrated circuits formed on a semiconductor wafer. You may select the arrangement | positioning with the shortest total time which requires. Thereby, the arrangement of two or more integrated circuits to be tested at the same time can be optimized, the test time per semiconductor wafer can be shortened, and the inspection cost can be suppressed.

  In the first aspect of the present invention, when there are a plurality of other semiconductor wafers close to the semiconductor wafer, the test time counting unit is required for testing a plurality of integrated circuits corresponding to the formation positions between the plurality of other semiconductor wafers. You may take the average value of the time. This makes it possible to predict the test time with higher accuracy.

  In the first feature of the present invention, the semiconductor test apparatus is configured so that each of the other semiconductor wafers can be compared with the time required for the test of the integrated circuit when the distance between the plurality of other semiconductor wafers and the semiconductor wafer is different. A weighting unit that performs weighting according to the distance may be further included, and the test time counting unit may total the weighted time distribution. Thereby, since weighting according to the distance between wafers is performed with respect to test time, more accurate test time can be predicted.

  The second feature of the present invention is that the test is repeatedly performed using a probe card capable of simultaneously testing m (2 or more natural number) integrated circuits on the semiconductor wafer. A semiconductor test method for testing n (natural number larger than m) integrated circuits formed, wherein the semiconductor test method is formed on another semiconductor wafer adjacent to the semiconductor wafer. A first stage for totalizing the time distribution required for the test for each integrated circuit, a second stage for determining the arrangement of m integrated circuits to be tested simultaneously with reference to the total time distribution, And a third stage of repeatedly testing the integrated circuit according to the determined arrangement.

  In the second aspect of the present invention, the second step is to test n integrated circuits in a group of m integrated circuits that can be taken for n integrated circuits formed on a semiconductor wafer. It may be a step of selecting an arrangement that requires the shortest overall time.

In the second aspect of the present invention, when there are a plurality of other semiconductor wafers close to the semiconductor wafer, in the first stage, it is necessary to test a plurality of integrated circuits whose formation positions correspond between the plurality of other semiconductor wafers. You may take the average value of the time.

  In the second aspect of the present invention, the semiconductor test method is configured to measure the time required for testing the integrated circuit before the first stage when the distance between the semiconductor wafer and the other semiconductor wafers is different. The method may further include a step of performing weighting according to the distance of each of the other semiconductor wafers.

  According to the present invention, it is possible to provide a semiconductor test apparatus and a semiconductor test method with high test efficiency by optimizing the arrangement of two or more integrated circuits to be tested simultaneously.

  Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same parts are denoted by the same reference numerals and description thereof is omitted.

  With reference to FIG. 1A, a configuration of a semiconductor test apparatus according to an embodiment of the present invention will be described. The semiconductor test apparatus is an apparatus for testing electrical characteristics of a plurality of integrated circuits formed on the semiconductor wafer 8, and is used to determine whether each integrated circuit is a good product or a defective product.

  The semiconductor test apparatus includes a prober 2 and a tester 3. The prober 2 transmits an electrical signal to the integrated circuit by bringing the probe needle 7 into contact with the stage 4 on which the semiconductor wafer 8 is placed, and the electrode pad of the integrated circuit formed on the semiconductor wafer 8, and integrating the probe. And a probe card 5 for receiving an electrical signal output from the circuit. The stage 4 can move in the X axis parallel to the main surface of the semiconductor wafer 8 on which the integrated circuit is formed, the Y axis orthogonal to the main surface, and the Z axis direction perpendicular to the main surface of the semiconductor wafer 8. it can.

  The tester 3 includes a test head 6 connected to the probe card 5, a control calculation unit 11 that controls the test head 6 and the entire prober 2, and a memory 12 that stores information necessary for the test. Via the probe needle 7 of the probe card 5.

  The control operation unit 11 controls the movement of the stage 4 to bring the probe needle 7 of the probe card 5 into contact with the electrode pad of the integrated circuit of the semiconductor wafer 8 placed on the stage 4. In a state where the probe needle 7 of the probe card 5 is in contact with the electrode pad of the integrated circuit of the semiconductor wafer 8, the tester 3 inputs and inputs an electrical signal having a predetermined test pattern to the electrode pad of the integrated circuit. The quality of the integrated circuit is determined by analyzing the electrical signal output from the electrode pad of the integrated circuit with respect to the generated electrical signal. The control calculation unit 11 measures the time required for the test for each integrated circuit, and stores the measured time in the memory 12.

  The probe card 5 is a so-called multi-probing probe card that can simultaneously perform tests on m integrated circuits by bringing probe needles into contact with electrode pads of m integrated circuits. Here, “m” is a natural number of 2 or more. A test of all the n integrated circuits formed on the semiconductor wafer 8 is performed by repeatedly performing the test of the integrated circuit using the probe card 5 for multi-probing while controlling the movement of the stage 4. be able to. Here, “n” is a natural number larger than m. In the embodiment of the present invention, an example of a probe card 5 for multi-probing for simultaneously testing two (m = 2) integrated circuits formed on a semiconductor wafer 8 will be described.

  2 (a) to 2 (f) and FIGS. 3 (a) to 3 (f) show n pieces formed on a semiconductor wafer by repeatedly performing a test using a probe card for multi-probing. FIG. 2A to FIG. 2F show probe cards Sa that can be simultaneously tested for two integrated circuits arranged in the vertical direction (Y direction). The case where is used is shown.

  First, the control calculation unit 11 adjusts the position of the stage 4 with respect to the test head 6 so that the probe needle of the probe card Sa is in the position surrounded by the dotted line in FIG. 2A, and then the probe of the probe card Sa The needle 7 is brought into contact with the electrode pad of the integrated circuit on the semiconductor wafer 8. Then, the tester 3 performs a predetermined test. In addition, in the position of the probe card Sa shown in FIG. 2A, the integrated circuit 9 is formed in the lower part, but since the integrated circuit 9 is not formed in the upper part, it is shown in FIG. In the shot, the test is performed only on the integrated circuit 9 in the lower part. As a test result (good / bad determination), a non-defective product determination is indicated by “P (pass)”, and a defective product determination is indicated by “F (fail)”.

  Thereafter, as shown in FIG. 2B, the control calculation unit 11 moves the stage 4 to the adjacent integrated circuit 9 in the lateral direction (X direction), and brings the probe needle 7 into contact with the electrode pad of the integrated circuit 9. In this state, the tester 3 performs a predetermined test. Similarly, as shown in FIG. 2C, the stage 4 is moved to test the integrated circuit. In this way, all the integrated circuits formed on the semiconductor wafer 8 as shown in FIG. 2 (f) are obtained by repeatedly performing the movement of the stage 4, the contact of the probe needle 7, and the test of the integrated circuit 9. A predetermined test can be performed for 9. 2C and 2D indicate the moving direction of the probe card Sa.

  FIG. 3A to FIG. 3F show a case where a probe card Sb that can be tested simultaneously on two integrated circuits arranged in an oblique direction is used. In this case, similarly to the example of FIGS. 2A to 2F, the stage 4 is moved, the probe needle 7 is contacted, and the integrated circuit 9 is repeatedly tested, so that FIG. ), A predetermined test can be performed on all the integrated circuits 9 formed on the semiconductor wafer 8. As shown in FIGS. 2 (f) and 3 (f), there is no difference in pass / fail judgment of each integrated circuit even if the types (Sa, Sb) of probe cards to be used are different.

  FIG. 4A shows the quality determination of the integrated circuit performed by the procedure shown in FIG. 2 on a map on the semiconductor wafer 8, and FIG. 4B and FIG. The time required for the test of the integrated circuit is shown by a map on the semiconductor wafer 8. As described above, the result of the test performed by the semiconductor test apparatus of FIG. 1A is the “pass-fail map” as shown in FIG. 4A, or as shown in FIG. 4B or 4C. Such a “test time map” is stored in the memory 12 of FIG. The pass / fail map stores only the pass / fail judgment of each integrated circuit in correspondence with the position on the semiconductor wafer 8, and the test time map shows the time required for the test of each integrated circuit on the position on the semiconductor wafer 8. It is memorized corresponding to. The example of the test time map in FIG. 4B is a case where the test time of a good integrated circuit is uniformly displayed as 30 seconds and the test time of a defective integrated circuit is uniformly displayed as 10 seconds, as shown in FIG. An example of the test time map is a case where the test time for each defective integrated circuit is displayed as a map. In the embodiment of the present invention, the case where a test time map as shown in FIG. 4B is stored in the memory 12 of FIG.

FIG. 5A to FIG. 5D are wafer maps showing examples of arrangement of m (= 2) integrated circuits that can be taken for n (= 22) integrated circuits formed on the semiconductor wafer 8. FIGS. 5A and 5B are examples of arrangement of probe cards Sa that can simultaneously test two integrated circuits arranged in the vertical direction (Y direction). FIG. 5C and FIG. 5D are arrangement examples of probe cards Sb that can simultaneously test two integrated circuits arranged in an oblique direction.

  As shown in FIGS. 5A and 5B, the vertical probe card Sa can take two arrangements for the 22 integrated circuits formed on the semiconductor wafer 8. Further, as shown in FIGS. 5C and 5D, the probe card Sb in the oblique direction can be arranged in two ways with respect to the 22 integrated circuits formed on the semiconductor wafer 8.

For each arrangement shown in FIGS. 5A to 5D, a test time per semiconductor wafer 8 is calculated.
In the case of FIG.
30 seconds × 10 = 300 seconds 10 seconds × 4 = 40 seconds → total 340 seconds In the case of FIG.
30 seconds × 9 = 270 seconds 10 seconds × 5 = 50 seconds → total 320 seconds In the case of FIG.
30 seconds × 11 = 330 seconds 10 seconds × 3 = 30 seconds → total 360 seconds In the case of FIG.
30 seconds × 10 = 300 seconds 10 seconds × 5 = 50 seconds → total 350 seconds In this way, even if the type of probe card (Sa, Sb) used is the same, two integrated circuits that simultaneously perform the test If the arrangement of is different, a difference appears in the test time per semiconductor wafer 8. With respect to the probe card Sb in the oblique direction, the number of shots is one more in FIG. 5D than in FIG. 5C, but the overall test time is shortened. When two integrated circuits to be tested at the same time are a good product and a defective product, the probe needle that has tested the defective integrated circuit can move the stage 4 until the test of the good product being performed at the same time is completed. Since it cannot be performed, it waits until the time (30 seconds) required for a good quality test passes. When two integrated circuits to be tested at the same time are both non-defective or defective, the time required for the test is 30 seconds or 10 seconds, respectively.

  Therefore, the semiconductor test apparatus according to the embodiment of the present invention has the control operation unit 11 shown in FIG. 1B in order to optimize the arrangement of two integrated circuits to be tested at the same time and increase the test efficiency.

  As shown in FIG. 1B, the control calculation unit 11 aggregates the distribution of time required for testing n integrated circuits formed on another semiconductor wafer adjacent to the semiconductor wafer 8 for each integrated circuit. The test time totaling unit 22 that performs the test, the multi-location determination unit 24 that determines the layout of the two integrated circuits to be tested simultaneously with reference to the distribution of the totaled time, and the integration according to the determined layout of the two integrated circuits A test execution unit 25 that repeatedly executes a circuit test and a weighting unit 21 are included.

Here, the “semiconductor wafer 8” is a semiconductor wafer to be tested from which the integrated circuit test will be performed, and the “other semiconductor wafer” has already been tested for the integrated circuit, and whether or not each integrated circuit is determined as good or bad. The semiconductor wafer is stored in the memory 12 with time data required for the test. “Adjacent” indicates that a physical distance between two semiconductor wafers is short in a process of manufacturing a semiconductor wafer from a single crystal rod (ingot) or a process of forming an integrated circuit on a semiconductor wafer. . For example, two semiconductor wafers belong to the same ingot, two semiconductor wafers belong to a close position in the ingot, and two semiconductors are formed in the process of forming an integrated circuit on the semiconductor wafer. This includes that the wafer belongs to the same lot and that the distance between two semiconductor wafers in the same lot is short. Here, “adjacent” is used as a term including both “adjacent” where two semiconductor wafers are adjacent to each other and “near” where several semiconductor wafers are interposed between two semiconductor wafers.

  The test time totaling unit 22 searches the data in the memory 12 and reads the time required for testing each integrated circuit from the memory 12 for other semiconductor wafers close to the semiconductor wafer 8, and the result shown in FIG. Aggregate as a test time map as shown. As a result, the time distribution required for testing the n integrated circuits formed on the other semiconductor wafer is aggregated for each integrated circuit.

  The distribution of time required for testing each integrated circuit in two or more semiconductor wafers close to each other tends to approximate. If this tendency is used, the time distribution required for testing the n integrated circuits of the semiconductor wafer is predicted for each integrated circuit from the distribution of time required for testing the n integrated circuits of the other semiconductor wafers. can do. When test time maps as shown in FIG. 4B are tabulated as test results of other semiconductor wafers, the test target semiconductor wafer 8 adjacent to the other semiconductor wafers is also shown in FIG. It is expected that an approximate test time distribution will be obtained.

  Note that the test time totaling unit 22 has an average value acquisition unit 23, and when there are a plurality of other semiconductor wafers close to the semiconductor wafer 8, the average value acquisition unit 23 has a formation position between the plurality of other semiconductor wafers. The average value of the time required for testing the corresponding integrated circuits is taken. As a result, the test time distribution can be predicted with higher accuracy.

  Further, the weighting unit 21 weights the time required for the test of the integrated circuit according to the distance of each of the other semiconductor wafers when the distance between the plurality of other semiconductor wafers and the semiconductor wafer 8 is different. Do. The test time totaling unit 22 totals the weighted test time distribution. Thereby, the prediction accuracy of the test time distribution is further improved.

  The multi-placement determining unit 24 refers to the test time map tabulated as shown in FIG. 4B, and determines the placement of two integrated circuits to be tested simultaneously. For example, the multi-placement determining unit 24 performs n integrations formed on the semiconductor wafer 8 as shown in FIGS. 5A to 5D with respect to the test time map of FIG. Among the two integrated circuit arrangement groups that can be taken for the circuit, an arrangement is selected that minimizes the overall time required to test n integrated circuits. Specifically, the multi-arrangement determination unit 24 calculates the entire test time per semiconductor wafer 8 for each of the two integrated circuit arrangements shown in FIGS. Choose an arrangement that gives the shortest overall test time.

  The test execution unit 25 repeatedly executes the test of the integrated circuit according to the arrangement of the two selected integrated circuits.

  With reference to FIG. 6, an example of a semiconductor test method using the semiconductor test apparatus of FIG.

  (A) First, in step S01, the control calculation unit 11 searches the data in the memory 12, and data of time required for testing each integrated circuit for another semiconductor wafer close to the semiconductor wafer 8 to be tested. Judge whether there is. If there is time data (YES in S01), the process proceeds to step S02, and if there is no time data (NO in S01), the process proceeds to step S05. For example, since it can be determined that there is no other semiconductor wafer that is close to the semiconductor wafer to be tested first for one lot and has already been tested, in this case (S01). NO), the process proceeds to step S05.

  (B) In step S02, the test time totaling unit 22 reads the time required for testing each integrated circuit from the memory 12 for the other semiconductor wafers close to the semiconductor wafer 8, as shown in FIG. Aggregate as test time map. In the example of FIG. 6, the case where there is one other semiconductor wafer will be described.

  (C) Proceeding to step S03, the multi-placement determining unit 24 calculates the entire test time per semiconductor wafer 8 for each of the two integrated circuit placements shown in FIGS. 5 (a) to 5 (d). . Thereafter, the process proceeds to step S04, where the multi-placement determining unit 24 has the shortest overall test time per semiconductor wafer 8 out of the two integrated circuit placement groups shown in FIGS. 5 (a) to 5 (d). Select an arrangement. 5A to 5D, the arrangement in which the entire test time is the shortest is FIG. 5B, so the multi-arrangement determination unit 24 selects the arrangement shown in FIG. 5B. .

  (D) Proceeding to step S05, the test execution unit 25 repeatedly executes the test of the integrated circuit according to the selected arrangement shown in FIG. Through the above procedure, a predetermined test can be performed on all the integrated circuits formed on the semiconductor wafer 8.

  As described above, according to the embodiment of the present invention, the following effects can be obtained.

  The distribution of time required for testing each integrated circuit in two or more semiconductor wafers close to each other tends to approximate. If this tendency is utilized, the time distribution required for testing n integrated circuits of other semiconductor wafers (22 in the example of FIG. 4B) will be calculated from the n distributions of the semiconductor wafer 8 to be tested. The distribution of time required for testing the integrated circuit can be predicted for each integrated circuit. Therefore, referring to the distribution of time required for testing n integrated circuits formed on another semiconductor wafer adjacent to the semiconductor wafer 8, the arrangement of two (m = 2) integrated circuits to be tested simultaneously. Thus, the arrangement of two integrated circuits to be tested simultaneously can be optimized, the test time per semiconductor wafer can be shortened, and the inspection cost can be suppressed.

Among the arrangement groups of two (m = 2) integrated circuits that can be taken for the n integrated circuits formed on the semiconductor wafer, an arrangement in which the total time required for testing the n integrated circuits is the shortest. The selection determines the placement of the two integrated circuits to be tested simultaneously. Thereby, the test time per semiconductor wafer can be shortened and the inspection cost can be suppressed.
(First modification)
In the example of the semiconductor test method shown in FIG. 6, the number of other semiconductor wafers close to the semiconductor wafer 8 is one. However, when there are a plurality of other semiconductor wafers, the flowchart shown in FIG. The integrated circuit formed in the test can be tested.

  With reference to FIG. 7, a first modification of the semiconductor test method using the semiconductor test apparatus of FIG.

(A) First, in step S11, the control calculation unit 11 searches for data in the memory 12, and data on the time required for testing each integrated circuit for another semiconductor wafer adjacent to the semiconductor wafer 8 to be tested. Judge whether there is. If time data is present (YES in S11), the process proceeds to step S12. If time data is not present (NO in S11), the process proceeds to step S17.

  (B) In step S <b> 12, the control calculation unit 11 determines whether there are a plurality of other semiconductor wafers close to the semiconductor wafer 8. If there are a plurality of sheets (YES in S12), the process proceeds to step S13, and if there are not a plurality of sheets (NO in S12), the process proceeds to step S14.

  (C) In step S13, the average value acquisition unit 23 takes the average value of the time required for the test for the plurality of integrated circuits corresponding to the formation positions among the plurality of other semiconductor wafers. Then, it progresses to step S14.

  (D) The processing contents of steps S14 to S17 are the same as those of steps S02 to S05 in FIG.

Thus, when there are a plurality of other semiconductor wafers close to the semiconductor wafer 8, by taking the average value of the time required for the test for a plurality of integrated circuits corresponding to the formation positions between the plurality of other semiconductor wafers, More accurate test time can be predicted.
(Second modification)
In the example of the semiconductor test method shown in FIG. 7, the distance between a plurality of other semiconductor wafers and the semiconductor wafer 8 is not taken into account, but by taking this distance into account, a more accurate test time can be predicted. It becomes.

  With reference to FIG. 8, a second modification of the semiconductor test method using the semiconductor test apparatus of FIG.

  (A) First, in step S21, the control calculation unit 11 searches the data in the memory 12, and data on the time required for testing each integrated circuit for another semiconductor wafer close to the semiconductor wafer 8 to be tested. Judge whether there is. If there is time data (YES in S21), the process proceeds to step S22, and if there is no time data (NO in S21), the process proceeds to step S29.

  (B) In step S <b> 22, the control calculation unit 11 determines whether there are a plurality of other semiconductor wafers close to the semiconductor wafer 8. If there are a plurality of sheets (YES in S22), the process proceeds to step S23, and if there are not a plurality of sheets (NO in S22), the process proceeds to step S25.

  (C) In step S23, the control calculation unit 11 determines whether or not the distances between the plurality of other semiconductor wafers and the semiconductor wafer 8 are different from each other. If the distance is different (YES in S23), the process proceeds to step S24. If the distance is not different (NO in S23), the process proceeds to step S25.

  (D) In step S24, the weighting unit 21 weights the time required for the test of the integrated circuit according to the distance of each of the other semiconductor wafers. Thereafter, the process proceeds to step S25.

  (E) The processing contents of steps S25 to S29 are the same as those of steps S13 to S17 in FIG.

Thus, when the distances between the plurality of other semiconductor wafers and the semiconductor wafer 8 are different from each other, the weighting unit 21 responds to the distance of each of the other semiconductor wafers with respect to the time required for the test of the integrated circuit. Weighting. Then, the test time totaling unit 22 totals the weighted time distribution. This makes it possible to predict the test time with higher accuracy.

  As described above, the present invention has been described by way of one embodiment and modifications thereof. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples, and operational techniques will be apparent to those skilled in the art.

  For example, after testing all semiconductor wafers in a specific lot, the test time map is totaled for all semiconductor wafers, the trend of test time distribution is analyzed for the semiconductor product types, The arrangement of two or more integrated circuits to be tested at the same time is preset and applied to the semiconductor wafer to be tested first for the next lot of the same type. As a result, the test efficiency can be improved for the semiconductor wafer to be tested first in the lot.

  In the embodiment of the present invention, the case where the test time totaling unit 22 totals the test time map shown in FIG. 4B has been described, but the path fail map shown in FIG. 4A or FIG. The detailed test time map shown in c) may be totaled. When tabulating the pass / fail maps shown in FIG. 4A, if the test times required for the pass (P) and fail (F) are set, the same semiconductor test method as in FIG. 4 (b) is performed. be able to. By using the detailed test time map shown in FIG. 4C, the test efficiency can be further improved.

  5 (a) to 5 (d), the vertical probe card Sa and the diagonal probe card Sb are taken as examples. However, the present invention also applies to multi-probing probe cards having other arrangements. The invention can be applied. The same applies to a probe card for multi-probing capable of simultaneously testing three or more integrated circuits.

  In the embodiment of the present invention, the case where the tester 3 includes the control calculation unit 11 and the memory 12 has been described. However, the prober 2 may include the control calculation unit 11 and the memory 12.

  Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters according to the scope of claims reasonable from this disclosure.

FIG. 1A is a block diagram showing the configuration of the semiconductor test apparatus according to the embodiment of the present invention, and FIG. 1B is a block diagram showing the configuration of the control arithmetic unit 11 of FIG. . 2 (a) to 2 (f) show a case where a semiconductor wafer is repeatedly tested by using a probe card Sa that can simultaneously test two integrated circuits arranged in the vertical direction (Y direction). The procedure for testing all of the n integrated circuits formed in FIG. 3 (a) to 3 (f) are formed on a semiconductor wafer by repeatedly performing a test using a probe card Sb that can be simultaneously tested on two integrated circuits arranged in an oblique direction. A procedure for testing all n integrated circuits is shown. FIG. 4A shows the quality determination of the integrated circuit performed by the procedure shown in FIG. 2 on a map on the semiconductor wafer 8, and FIG. 4B and FIG. The time required for the test of the integrated circuit is shown by a map on the semiconductor wafer 8. FIG. 5A to FIG. 5D are wafer maps showing examples of arrangement of m (= 2) integrated circuits that can be taken for n (= 22) integrated circuits formed on the semiconductor wafer 8. FIGS. 5A and 5B are examples of arrangement of probe cards Sa that can simultaneously test two integrated circuits arranged in the vertical direction (Y direction). FIG. 5C and FIG. 5D are arrangement examples of probe cards Sb that can simultaneously test two integrated circuits arranged in an oblique direction. It is a flowchart which shows an example of the semiconductor test method using the semiconductor test apparatus of Fig.1 (a). It is a flowchart which shows the semiconductor test method in connection with a 1st modification. It is a flowchart which shows the semiconductor test method in connection with a 2nd modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 2 ... Prober 3 ... Tester 4 ... Stage 5, Sa, Sb ... Probe card 6 ... Test head 7 ... Probe needle 8 ... Semiconductor wafer 9 ... Integrated circuit 11 ... Control operation part 12 ... Memory 21 ... Weighting part 22 ... Test time totalization Unit 23 ... Average value acquisition unit 24 ... Multi-placement determination unit 25 ... Test execution unit

Claims (8)

By repeating the test using a probe card capable of simultaneously performing tests on m (natural numbers of 2 or more) integrated circuits on the semiconductor wafer, n (larger than m) formed on the semiconductor wafer A semiconductor test apparatus for testing a natural number of integrated circuits,
A test time counting unit for counting the distribution of time required for testing n integrated circuits formed on another semiconductor wafer adjacent to the semiconductor wafer for each integrated circuit;
A multi-location determining unit that determines the layout of m integrated circuits to be tested simultaneously with reference to the aggregated time distribution;
And a test execution unit that repeatedly executes a test of the integrated circuit according to the determined arrangement.   The multi-arrangement determining unit has the shortest total time required for testing n integrated circuits in the arrangement group of m integrated circuits that can be taken for n integrated circuits formed on a semiconductor wafer. The semiconductor test apparatus according to claim 1, wherein the arrangement is selected.   When there are a plurality of other semiconductor wafers close to the semiconductor wafer, the test time counting unit calculates an average value of the time required for the test for a plurality of integrated circuits corresponding to formation positions between the plurality of other semiconductor wafers. 3. The semiconductor test apparatus according to claim 1, wherein the semiconductor test apparatus is taken.   A weighting unit that weights the time required for the test of the integrated circuit according to the distance of each of the other semiconductor wafers when the distance between the plurality of other semiconductor wafers is different from that of the semiconductor wafer; The semiconductor test apparatus according to claim 3, further comprising a test time totaling unit that totalizes the weighted distribution of the time. By repeating the test using a probe card capable of simultaneously performing tests on m (natural numbers of 2 or more) integrated circuits on the semiconductor wafer, n (larger than m) formed on the semiconductor wafer A semiconductor test method for testing a natural number of integrated circuits,
A first stage in which a distribution of time required for testing n integrated circuits formed on another semiconductor wafer adjacent to the semiconductor wafer is aggregated for each integrated circuit;
A second step of determining the placement of m integrated circuits to be tested simultaneously with reference to the aggregated time distribution;
And a third step of repeatedly testing the integrated circuit according to the determined arrangement. In the second stage, the total time required for testing n integrated circuits is the shortest among the arrangement groups of m integrated circuits that can be taken for n integrated circuits formed on a semiconductor wafer. The semiconductor test method according to claim 5, wherein the placement is selected. When there are a plurality of other semiconductor wafers close to the semiconductor wafer,
7. The semiconductor test according to claim 5, wherein, in the first stage, an average value of times required for the test is taken for a plurality of integrated circuits corresponding to formation positions among a plurality of other semiconductor wafers. Method. When the distance between a plurality of other semiconductor wafers and the semiconductor wafer is different,
8. The method according to claim 7, further comprising the step of weighting the time required for testing the integrated circuit according to the distance of each of the other semiconductor wafers before the first step. The semiconductor test method as described.

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