JP2009158051A - Nonvolatile semiconductor memory device and read test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device capable of performing a read test through the same path as a normal read without adding a test circuit to the read path.
A nonvolatile semiconductor memory device is used for error correction based on a memory cell array configured by arranging a plurality of electrically rewritable nonvolatile memory cells and input data input from the outside. A parity generation circuit that generates a check code, a first write control circuit that writes the input data to the memory cell array, a second write control circuit that writes the check code to the memory cell array, and the first control circuit And an internal control circuit for controlling whether or not to perform the write operation by the second write control circuit.
[Selection] Figure 1

Description

  The present invention relates to a nonvolatile semiconductor memory device and a read test method thereof, for example, a NOR flash memory equipped with an ECC function.

  Semiconductor products such as computers and LSI (Large Scale Integration) have been applied to various fields, and the demand for reliability has been increasing. In order to realize high reliability of semiconductor products, a method of using highly reliable parts in each component and devising the configuration is adopted. Memory is no exception as this highly reliable component.

  For memory data, high reliability technology using static redundancy is adopted. A code having error detection and correction capability is referred to as ECC (Error Checking and Correcting), and thereby a high-reliability technique for correcting and reading out erroneous data bits at the time of reading is disclosed (for example, see Patent Document 1). ).

  In a memory having such a mechanism, when the memory data is in an erroneous data state or when an erroneous determination reading is performed in the reading path, reading is performed at the time of reading ability evaluation (read access test) including an error correction delay. It is conceivable to add a test circuit capable of processing the input of the sense amplifier or processing the input of the ECC circuit.

However, when the read access test is performed by the above method, the circuit cost for generating the error bit is increased, and a logic stage is added to the read path, and the evaluation is performed with an operation (or path) different from normal. The problem of becoming may arise.
JP 2000-137995 A

  The present invention provides a non-volatile semiconductor memory device capable of performing a read test through the same path as a normal read without adding a test circuit to the read path.

  A nonvolatile semiconductor memory device according to one embodiment of the present invention performs error correction based on a memory cell array including a plurality of electrically rewritable nonvolatile memory cells and input data input from the outside. A parity generation circuit for generating a check code to be used; a first write control circuit for writing the input data to the memory cell array; a second write control circuit for writing the check code to the memory cell array; And an internal control circuit for controlling whether or not to perform a write operation by the control circuit and whether or not to perform a write operation by the second write control circuit.

  According to the present invention, it is possible to provide a non-volatile semiconductor memory device that can perform a read test through the same path as a normal read without adding a test circuit to the read path.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device, for example, a NOR flash memory 100 according to this embodiment.

  The NOR flash memory 100 includes an address buffer 101, an input / output buffer 102, a parity generation circuit 103, a memory cell array 104, a first write control circuit 105, a second write control circuit 106, a sense amplifier circuit 107, and a sense amplifier circuit 108. A parity generation circuit 109, a syndrome generation circuit 110, a decode circuit 111, a data correction circuit 112, an internal control circuit 113, and flip-flop circuits 114, 115, and 116.

  The address buffer 101 temporarily holds an address input from the external host system to the NOR flash memory 100 and transfers the address to the input / output buffer 102 and the internal control circuit 113.

  The input / output buffer 102 temporarily holds data input from the external host system to the NOR flash memory 100 and transfers the data to the first write control circuit 105 and the parity generation circuit 103. Further, when data is output from the NOR flash memory 100 to the external host system, the data read through the data correction circuit 112 is temporarily held.

  Data between the external host system and the input / output buffer 102 in units of 16 bits (1 word) via, for example, 16 IO terminals (IO [0], IO [1]... IO [15]). I / O is performed. In addition, a path through which data can be input to the multiplexer 117 from the 16 IO terminals without going through the input / output buffer 102 is provided.

  The parity generation circuit 103 generates a parity bit (check code) based on the data transferred from the input / output buffer 102. For example, the parity generation circuit generates an m-bit check code for n-bit input data that is a part of data held in the input / output buffer 102. The parity generation circuit 103 has a function capable of correcting a 1-bit error generated in (n + m) -bit data including, for example, n-bit input data and an m-bit check code.

  The correction capability of the parity generation circuit 103 is appropriately determined in consideration of the error bit occurrence rate caused by the physical characteristics of the memory cell, and the correction capability (number of error bits that can be corrected) is calculated. Accordingly, a decoding method such as a Hamming code, a Reed-Solomon code, or a BCH (Bose-Chaudhuri-Hocqenghen) code may be selected.

  The memory cell array 104 is configured by arranging a plurality of blocks as a minimum unit that can be erased independently, each including a plurality of electrically rewritable memory cells. The memory cell array 104 has a main body data storage area for storing input data transferred from the input / output buffer 102 and an ECC area for storing a check code transferred from the parity generation circuit 103. The n-bit input data and the m-bit check code can be stored in a plurality of memory cells connected to the same word line, for example.

  The allocation of the main body data area and the ECC area shown in FIG. 1 is an example, and does not necessarily mean that the area is physically divided into two areas. That is, any data arrangement may be used as long as n-bit input data can be stored in the memory cell array 104 in association with an m-bit check code generated based on the n-bit input data. Absent.

  The memory cell has a two-layer gate structure including a floating gate electrode and a control gate electrode, and retains data in a nonvolatile manner in response to a change in the threshold voltage of the transistor due to the amount of electrons injected into the floating gate electrode. Is possible.

  The memory cell may store, for example, data “1” (erased state) in the order of threshold voltage or binary data of data “0”, or data “11” (erased state) in order of threshold voltage. ), 4-value data of data “10”, data “01”, and data “00” may be stored.

  The first write circuit 105 receives n-bit (n is a positive integer) input data transferred from the input / output buffer 102 and writes this input data in the main body data storage area of the memory cell array 104. The first write circuit 105 is controlled by the control signal enableA input from the flip-flop circuit 114, and for example, write enable is enabled when enableA = "0", and write disable is enabled when enableA = "1".

  The second write circuit 106 receives an m-bit (m is a positive integer) check code transferred from the parity generation circuit 103 via the multiplexer 117, and writes this check code in the ECC area of the memory cell array 104. Further, the check code input from the outside via the multiplexer 117 is received without going through the input / output buffer 102 and the parity generation circuit 103, and this check code is written in the ECC area of the memory cell array 104.

  The check code input to the second write control circuit 106 without passing through the parity generation circuit 103 uses an m-bit value calculated in advance according to an input data pattern used in a read test described later. It ’s fine.

  Similar to the first write circuit 105, the second write circuit 106 is controlled by a control signal enableB input from the flip-flop circuit 115. For example, write enable is enabled when enableB = "0", and enableB = "1". Writing is not permitted.

  The sense amplifier circuit 107 includes a plurality of sense amplifiers and a data latch circuit. The sense amplifier connected to each bit line of the memory cell array 104 loads data to the bit line, detects the potential of the bit line, and holds it in the data latch circuit. Data read from the main data area of the memory cell array 104 by the sense amplifier circuit 107 is transferred to the first write control circuit 105, the parity generation circuit 109, and the data correction circuit 112.

  The sense amplifier circuit 108 includes a plurality of sense amplifiers and a data latch circuit. The sense amplifier connected to each bit line of the memory cell array 104 loads data to the bit line, detects the potential of the bit line, and holds it in the data latch circuit. The check code read from the ECC area of the memory cell array 104 by the sense amplifier circuit 107 is transferred to the second write control circuit 106 and the syndrome generation circuit 110.

  The parity generation circuit 109 has a configuration substantially similar to that of the parity generation circuit 103 described above. That is, an m-bit check code is generated for n-bit data read by the sense amplifier circuit 107 from the main body data area of the memory array 104.

  The syndrome generation circuit 110 is exclusive of the check code generated by the parity generation circuit 109 based on the data read from the main body data area of the memory cell array 104 and the check code written in the ECC area of the memory cell array 104. Generate a logical sum. That is, if the exclusive OR of two check bits is “0”, it is determined that the data is correct, and if it is “1”, it is determined that the data is error data.

  The decode circuit 111 decodes the exclusive OR between the check codes generated by the syndrome generation circuit 110 into a signal indicating the correction bit position. The signal indicating the correction bit position is transferred to the data correction circuit 112.

  The data correction circuit 112 calculates an exclusive OR of the correction bit position input from the decode circuit 111 and the read data transferred from the sense amplifier circuit 107. As a result, it is possible to correct a bit in which an error has occurred and output the bit to the outside via the input / output buffer 102.

  The internal control circuit 113 controls the first write control circuit 105, the second write control circuit 106, and the memory cell array 104, and manages various automatic operations (write operation, read operation, erase operation) of the NOR flash memory 100. To do. Further, a test mode signal is generated based on a special test mode setting command input from the IO terminal and address terminal. The test mode signal is input to the flip-flop circuits 114, 115, and 116.

  The state of the flip-flop circuit 114 is set by the clock signal CLK generated by the internal control circuit 113 and the test mode signal, and holds “0” data when reset. The flip-flop circuit 114 can invert the state to “1” data by the test mode signal, and transfers the held data state to the first write control circuit 105 as the control signal enableA.

  The state of the flip-flop circuit 115 is set by the clock signal CLK generated by the internal control circuit 113 and the test mode signal, and holds “0” data when reset. The flip-flop circuit 115 can invert the state to “1” data by the input of the test mode signal, and transfers the held data state to the second write control circuit 106 as the control signal enableB.

  The state of the flip-flop circuit 116 is set by the clock signal CLK generated by the internal control circuit 113 and the test mode signal, and holds “0” data when reset. The flip-flop circuit 116 can invert the state to “1” data by the input of the test mode signal, and sets the data signal selected by the multiplexer 117 according to the data state.

  For example, when the flip-flop circuit 116 holds “0” data, the input data transferred from the parity generation circuit 103 is selected and transferred to the second write control circuit 106. On the other hand, when the flip-flop circuit 116 holds “1” data, the input data (check code) is selected from the IO terminal without passing through the input / output buffer 102 and the parity generation circuit 103, and 2 to the write control circuit 106.

  The multiplexer 117 is controlled by the flip-flop circuit 116 and receives a check code input from the parity generation circuit 103 or a check code input directly from the IO terminal without passing through the input / output buffer 102 and the parity generation circuit 103. Either one is transferred to the second write control circuit 106.

  FIG. 2 is an equivalent circuit diagram showing the configuration of the write circuit 200 for one bit inside the first write control circuit 105. Note that the second write control circuit 106 has a similar circuit configuration. The first write control circuit 105 includes n write circuits 200. The second write circuit 106 includes m write circuits 200.

  Each write circuit 200 includes an EXOR gate 201, an AND gate 202, an RS flip-flop circuit 203, a NOR gate 204, an OR gate 205, an AND gate 206, and inverters 207 and 208.

  The EXOR gate 201 receives input data (write source data) and data read from the sense amplifier (S / A read data), and outputs an exclusive OR of both data. The write source data means “0” data for write target data, and “1” data means non-write data. The S / A read data means written data if “1” data, and unwritten data (erased state) if “0” data.

  The AND gate 202 receives the output signal of the EXOR gate 201 and the verification result update signal input from the internal control circuit 113, and outputs a logical product of both data. The verify result update signal is output when the sense amplifier circuit 107 or the sense amplifier in the sense amplifier circuit 108 determines the read data and the data is held in the data latch.

  The RS flip-flop circuit 203 receives the output signal of the AND gate 202 as a set (S) input, and receives a verification result clear signal from the internal control circuit 113 as a reset input (R).

  The NOR gate 204 receives the data state held by the RS flip-flop circuit 203 and the control signal enableA input from the flip-flop circuit 114, and outputs a negative OR of both data.

  The OR gate 205 receives the signal obtained by inverting the output signal of the NOR gate 204 by the inverter 207 and the control signal enableA, and outputs the logical product of both data as a coincidence flag generation signal. The coincidence flag generation signal includes (n + m) bits bundled in the first write control circuit 105 and the second write control circuit 106, and a logical flag is generated to generate a coincidence flag.

  The AND gate 206 receives the output signal of the NOR gate 204 and a signal obtained by inverting the write source data by the inverter 208, and outputs the logical product of both data as write data. Write data means data to be written if it is “1” data and data that is not write if it is “0” data. A write operation is performed on a memory cell corresponding to a bit whose write data is “1”.

  Hereinafter, the write operation of the NOR flash memory 100 according to the present embodiment will be described.

(1) Normal Write Operation During a normal write operation performed by the user, no test mode signal is generated by the internal control circuit 113, so that the flip-flop circuits 114, 115, and 116 are all in a reset state. Therefore, writing by the first write control circuit 105 and the second write control circuit 106 is both permitted. Further, the check code generated by the parity generation circuit 103 can be input to the second write control circuit 106.

  First, data is input from the IO terminal in units of one word and stored in the input / output buffer 102. After n bits of data are stored in the input / output buffer 102, the parity generation circuit 103 generates an m-bit check code.

  The n-bit input data and the m-bit check code are associated with each other, and writing to the memory cell array 104 is performed by the first write circuit 105 and the second write circuit 106, respectively. Hereinafter, a specific write operation will be described in detail with reference to FIG.

  In a flash memory such as a NOR type flash memory, generally, whether or not the threshold voltage of a memory cell has reached a predetermined value is automatically verified (verify operation) inside the memory chip to guarantee a write operation. .

  First, before the write operation starts, the control circuit 113 outputs a verify result clear signal to reset the RS flip-flop circuit 203 to the “0” data state. Next, for example, “0” data as write source data, that is, write target data is input to the EXOR gate 201. The S / A read data is not fixed, and the output signal of the EXOR gate 201 is indefinite. However, since the verify result output signal is not output, the output of the AND gate 202 is “0”.

  At this time, the output signal of the RS flip-flop circuit 203 maintains “0”. Since the control signal enableA (enableB) is “0” because writing is permitted, the output of the NOR gate 204 becomes “1”. Therefore, the output of the AND gate 206 is “1” (data to be written), and writing (injecting electrons) into the memory cell is performed.

  Next, in order to verify whether or not the threshold voltage of the memory cell has reached a predetermined value, data held in the memory cell is read. When the read data is held in the sense amplifier circuit 107 or the data latch in the sense amplifier circuit 108, a verify result update signal is output. When the threshold voltage of the memory cell has not reached the predetermined value, the S / A read data is “0”, and the output of the EXOR gate 201 is “0”. Therefore, since the output of the AND gate 202 is “0”, writing is performed again.

  On the other hand, when the threshold voltage of the memory cell reaches a predetermined value, since the S / A read data is “1”, the output of the EXOR gate 201 is “1”. Therefore, the output of the AND gate 202 becomes “1”, and the output signal of the RS flip-flop circuit 203 changes to “1”. Therefore, the output of the AND gate 206 is “0” (data not to be written), and thereafter, writing to the memory cell is not performed.

  As described above, it is determined whether or not writing is completed for each bit, and when the match flag generation signal of all bits (n + m bits) is “1”, it is determined that the writing operation is completed, and writing is performed. End the operation.

  In the NOR flash memory 100 according to the present embodiment, since the write operation of the first write control circuit 105 and the second control circuit 106 is set to be permitted in the reset state, the user can use the same method as usual. A write operation can be performed.

(2) Write operation during read test (2-1) First, a case where an error is added to an arbitrary bit of the main data to test whether or not the data is correctly corrected will be described with reference to FIG. To do.

  The internal control circuit 113 generates a test mode signal based on a special test mode setting command input from the IO terminal and the address terminal. The test mode signal is input to the flip-flop circuits 114, 115, and 116. The flip-flop circuit 114 is set to "1" data, the flip-flop circuit 115 is set to "0" data, and the flip-flop circuit 116 is set to "0" data. .

  As a result, the write operation by the first write control circuit 105 is not permitted. Further, the write operation by the second write control circuit 106 is permitted. Further, the check code generated by the parity generation circuit 103 can be transferred to the second write control circuit 106 via the multiplexer 117.

  In this state, n-bit write data (correct input data) is input from the outside. Based on the n-bit input data, the parity generation circuit 103 generates an m-bit check code (correct parity data).

  At this time, since the write operation by the first write control circuit 105 is not permitted, the input data is not written into the main body data area of the memory cell array 104. On the other hand, since the write operation by the second write control circuit 106 is permitted, a check code is written in the ECC area of the memory cell array 104 (hatched area in the upper part of FIG. 3).

  Next, the internal control circuit 113 switches the test mode signal, the flip-flop circuit 114 is set to “0” data, and the flip-flop circuit 115 is set to “1” data. As a result, the write operation by the first write control circuit 105 is permitted, and the write operation by the second write control circuit 106 is not permitted. Since the flip-flop circuit 116 is not allowed to perform the write operation by the second write control circuit 106, it may be set to either “0” data or “1” data.

  In this state, for example, data (input data including an error) obtained by inverting one bit in n-bit correct input data input earlier is input. Based on the n-bit input data including the error, the parity generation circuit 103 generates an m-bit check code (parity data including the error).

  At this time, since the write operation by the first write control circuit 105 is permitted, input data including an error is written in the main data area of the memory cell array 104 (the hatched area in the lower part of FIG. 3). On the other hand, since the write operation by the second write control circuit 106 is not permitted, the check code is not written to the ECC area of the memory cell array 104.

  In the above-described write operation during the read test, control is performed so that only data for which writing is permitted is subjected to the verify operation. For example, when the first write control circuit 105 is not allowed to write, the control signal enableA is “1”, and therefore the n-bit write circuit 200 in the first write control circuit 105 has a match flag. Always outputs “1”. Therefore, the write operation of the second write control circuit 106 is not affected.

  Similarly, for example, when the second write control circuit 106 is not permitted to write, since the control signal enableB is “1”, the write circuit 200 for m bits in the second write control circuit 106 is Therefore, “1” is always output as the match flag. Therefore, the write operation of the first write control circuit 105 is not affected.

  Through the above steps, the memory cell array 104 is in a state where n-bit data including a 1-bit error is stored in the main body data area and an m-bit correct check code is stored in the ECC area. That is, after the writing of the input data and the check code is completed, it is possible to easily realize a failure model in which the bits in the main data area are inverted due to, for example, deterioration of the retention characteristics of the memory cell.

  (2-2) Next, a case where an error is added to an arbitrary bit of parity data to test whether the data is correctly corrected will be described with reference to FIG.

  The internal control circuit 113 generates a test mode signal based on a special test mode setting command input from the IO terminal and the address terminal. The test mode signal is input to the flip-flop circuits 114, 115, and 116. The flip-flop circuit 114 is set to "1" data, the flip-flop circuit 115 is set to "0" data, and the flip-flop circuit 116 is set to "0" data. .

  As a result, the write operation by the first write control circuit 105 is not permitted. Further, the write operation by the second write control circuit 106 is permitted. In addition, the check code generated by the parity generation circuit 103 can be input to the second write control circuit 106 via the multiplexer 117.

  In this state, n-bit write data (input data including an error) is input from the outside. As input data including an error, as in (2-1), for example, data obtained by inverting one bit in correct input data of n bits may be used. Based on the n-bit input data, the parity generation circuit 103 generates an m-bit check code (parity data including an error).

  At this time, since the write operation by the first write control circuit 105 is not permitted, the input data is not written into the main body data area of the memory cell array 104. On the other hand, since the write operation by the second write control circuit 106 is permitted, a check code is written in the ECC area of the memory cell array 104 (hatched area in the upper part of FIG. 4).

  Next, the internal control circuit 113 switches the test mode signal, the flip-flop circuit 114 is set to “0” data, and the flip-flop circuit 115 is set to “1” data. As a result, the write operation by the first write control circuit 105 is permitted, and the write operation by the second write control circuit 106 is not permitted. Since the flip-flop circuit 116 is not allowed to perform the write operation by the second write control circuit 106, it may be set to either “0” data or “1” data.

  In this state, data (correct input data) obtained by inverting the error bit in the n-bit input data previously input is input from the outside. Based on this n-bit correct input data, the parity generation circuit 103 generates an m-bit check code (correct parity data).

  At this time, since the write operation by the first write control circuit 105 is permitted, correct input data is written into the main body data area of the memory cell array 104 (the hatched area in the lower part of FIG. 4). On the other hand, since the write operation by the second write control circuit 106 is not permitted, the check code is not written to the ECC area of the memory cell array 104.

  In the above-described write operation during the read test, control is performed so that only data for which writing is permitted is subjected to the verify operation. For example, when the first write control circuit 105 is not allowed to write, the control signal enableA is “1”, and therefore the n-bit write circuit 200 in the first write control circuit 105 has a match flag. Always outputs “1”. Therefore, the write operation of the second write control circuit 106 is not affected.

  Similarly, for example, when the second write control circuit 106 is not permitted to write, since the control signal enableB is “1”, the write circuit 200 for m bits in the second write control circuit 106 is Therefore, “1” is always output as the match flag. Therefore, the write operation of the first write control circuit 105 is not affected.

  Through the above steps, the memory cell array 104 is in a state where n-bit correct data is stored in the main body data area and an m-bit check code including a 1-bit error is stored in the ECC area. That is, after the writing of the input data and the check code is completed, a defective model in which bits in the ECC area are inverted due to, for example, deterioration of the retention characteristics of the memory cell can be easily realized.

  (2-3) Next, another example in which an error is added to an arbitrary bit of parity data to test whether the data is correctly corrected will be described with reference to FIG.

  The internal control circuit 113 generates a test mode signal based on a special test mode setting command input from the IO terminal and the address terminal. The test mode signal is input to the flip-flop circuits 114, 115, and 116. The flip-flop circuit 114 is set to "1" data, the flip-flop circuit 115 is set to "0" data, and the flip-flop circuit 116 is set to "1" data. .

  As a result, the write operation by the first write control circuit 105 is not permitted. Further, the write operation by the second write control circuit 106 is permitted. Further, it is possible to input a check code directly input from the outside to the second write control circuit 106 via the multiplexer 117 without passing through the input / output buffer 102 and the parity generation circuit 103.

  In this state, an m-bit check code (parity data including an error) is input from the outside. The check code input here is an error bit forcibly realized by inverting any one bit in the check code calculated in advance based on the input data pattern.

  At this time, since the write operation by the first write control circuit 105 is not permitted, the input data is not written into the main body data area of the memory cell array 104. On the other hand, since the write operation by the second write control circuit 106 is permitted, a check code is written in the ECC area of the memory cell array 104 (hatched area in the upper part of FIG. 5).

  Next, the internal control circuit 113 switches the test mode signal, the flip-flop circuit 114 is set to “0” data, and the flip-flop circuit 115 is set to “1” data. As a result, the write operation by the first write control circuit 105 is permitted, and the write operation by the second write control circuit 106 is not permitted. Since the flip-flop circuit 116 is not allowed to perform the write operation by the second write control circuit 106, it may be set to either “0” data or “1” data.

  In this state, n-bit input data (correct input data) is input from the outside. Based on this n-bit correct input data, the parity generation circuit 103 generates an m-bit check code (correct parity data).

  At this time, since the write operation by the first write control circuit 105 is permitted, correct input data is written into the main body data area of the memory cell array 104 (the hatched area in the lower part of FIG. 5). On the other hand, since the write operation by the second write control circuit 106 is not permitted, the check code is not written to the ECC area of the memory cell array 104.

  In the above-described write operation during the read test, control is performed so that only data for which writing is permitted is subjected to the verify operation. For example, when the first write control circuit 105 is not allowed to write, the control signal enableA is “1”, and therefore the n-bit write circuit 200 in the first write control circuit 105 has a match flag. Always outputs “1”. Therefore, the write operation of the second write control circuit 106 is not affected.

  Similarly, for example, when the second write control circuit 106 is not permitted to write, since the control signal enableB is “1”, the write circuit 200 for m bits in the second write control circuit 106 is Therefore, “1” is always output as the match flag. Therefore, the write operation of the first write control circuit 105 is not affected.

  Through the above steps, the memory cell array 104 is in a state where n-bit correct data is stored in the main body data area and an m-bit check code including a 1-bit error is stored in the ECC area. That is, after the writing of the input data and the check code is completed, a defective model in which bits in the ECC area are inverted due to, for example, deterioration of the retention characteristics of the memory cell can be easily realized.

  Compared with the method described in (2-2), it is not necessary to store n bits of input data in the input / output buffer 102 in order to generate a check code including an error. Since there is no need to generate a check code, the test time can be shortened.

  Data stored in the memory cell array 104 can be read by the same method as the normal read operation by performing the write operation according to (2-1), (2-2), and (2-3) described above. It is. Therefore, it is determined whether or not error correction by the sense amplifier circuits 107 and 108, the parity generation circuit 109, the syndrome generation circuit 110, the decode circuit 111, and the data correction circuit 112 is performed correctly, or when error correction is performed. Various readout tests such as measurement of the time required for the readout operation can be performed.

  In this embodiment, since a NOR flash memory having a function capable of correcting a 1-bit error is assumed, a failure model in which a 1-bit error occurs in (n + m) bits is considered. Of course, the present invention can also be applied to a case where two or more bits are inverted in a nonvolatile semiconductor memory device capable of correcting these error bits.

  As described above, the NOR type flash memory 100 according to the present embodiment is provided with separate write control circuits corresponding to the main body data area and the ECC area, respectively, and independently controlling them, so that In comparison, the following effects can be obtained.

  (1) The chip area can be reduced.

  In the NOR flash memory 100 according to the present embodiment, the write operation to the main data area and the ECC area is independently controlled using two write control circuits. As a result, it is not necessary to mount an extra test circuit in the read path, and the chip area can be reduced.

  (2) An increase in reading time can be prevented.

  In the NOR type flash memory 100 according to the present embodiment, the write operation to the main body data area and the ECC area is controlled independently using two write control circuits. As a result, it is possible to realize a state in which an error has occurred in an arbitrary bit in the main data area or the ECC area, so that it is not necessary to add a special logic circuit for testing to the read path. Therefore, the influence (read delay etc.) on the normal read operation performed by the user cannot occur.

  (3) It is possible to perform a test along the same path as a normal read operation.

  In the NOR flash memory 100 according to the present embodiment, it is not necessary to add a special logic circuit for testing to the read path. Therefore, it is possible to perform a reading test in accordance with the actual usage situation of the user.

  Although the present invention has been described using the present embodiment, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention in the implementation stage. . Further, the present embodiment includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the present embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and described in the column of the effect of the invention. In a case where at least one of the obtained effects can be obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

1 is a block diagram showing a configuration of a NOR flash memory 100 according to an embodiment of the present invention. 4 is an equivalent circuit of the write circuit 200 in the NOR flash memory 100 according to the embodiment of the present invention. FIG. 3 is a schematic diagram for explaining a read test method in the NOR flash memory 100 according to the embodiment of the present invention. FIG. 3 is a schematic diagram for explaining a read test method in the NOR flash memory 100 according to the embodiment of the present invention. 1 is a schematic diagram for explaining a read test method in a NOR flash memory 100 according to an embodiment of the present invention.

Explanation of symbols

100 NOR flash memory 101 Address buffer 102 Input / output buffer 103 Parity generation circuit 104 Memory cell array 105 First write control circuit 106 Second write control circuit 107 Sense amplifier circuit 108 Sense amplifier circuit 109 Parity generation circuit 110 Syndrome generation circuit 111 Decode circuit 112 Data correction circuit 113 Internal control circuit 114 Flip-flop circuit 115 Flip-flop circuit 116 Flip-flop circuit 117 Multiplexer 200 Write circuit 201 EXOR gate 202 AND gate 203 RS flip-flop circuit 204 NOR gate 205 OR gate 206 AND gate 207 Inverter 208 inverter

Claims (5)

A memory cell array configured by arranging a plurality of electrically rewritable nonvolatile memory cells;
A parity generation circuit that generates a check code used for error correction based on externally input data;
A first write control circuit for writing the input data to the memory cell array;
A second write control circuit for writing the check code to the memory cell array;
An internal control circuit for controlling whether to perform a write operation by the first control circuit and whether to perform a write operation by the second write control circuit;
A non-volatile semiconductor memory device comprising:   The nonvolatile semiconductor memory device according to claim 1, wherein the internal control circuit can independently control a write operation by the first control circuit and the second control circuit.   3. The nonvolatile semiconductor memory device according to claim 1, further comprising a path for inputting the check code from the outside to the second write circuit without going through the parity generation circuit. A read test method for a nonvolatile semiconductor memory device according to claim 2,
Inputting first input data to the nonvolatile semiconductor memory device from the outside;
Generating a first check code based on the first input data by the parity generation circuit;
Writing the first check code into the memory cell array by the second write control circuit;
Inputting second input data obtained by inverting at least one bit in the first input data to the nonvolatile semiconductor memory device from the outside;
Writing the second input data into the memory cell array by the first write control circuit;
Reading the second input data and the first check code written in the memory cell array;
A read test method for a non-volatile semiconductor memory device. A read test method for a nonvolatile semiconductor memory device according to claim 3,
Inputting the check code to the nonvolatile semiconductor memory device from the outside;
Writing the check code into the memory cell array by the second write control circuit;
Inputting the input data to the nonvolatile semiconductor memory device from the outside;
Writing the input data into the memory cell array by the first write control circuit;
Reading the input data and the check code written to the memory cell array;
A read test method for a non-volatile semiconductor memory device.

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