JP2009152418A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device capable of suppressing an increase in power consumption of the semiconductor device is provided.
The power MOSFET 100 (semiconductor device) is formed on a silicon substrate 1 and is formed on the silicon substrate 1 so as to reach the buried drain layer 2 into which impurities are introduced and the buried drain layer 2. A groove portion 11 having an insulating film 12 formed on the inner surface thereof, a groove portion 13 formed so as to protrude further downward from a lower end portion of the groove portion 11, and a conductive member 14 embedded in the groove portion 11 and the groove portion 13; It has. The buried drain layer 2 and the conductive member 14 are in contact with each other.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a buried layer into which an impurity is introduced and a manufacturing method thereof.

  Conventionally, a semiconductor device including a buried layer into which an impurity is introduced is known (for example, see Patent Document 1).

  The semiconductor device described in Patent Document 1 is formed on a semiconductor substrate, is formed on the substrate so as to reach the buried layer, and a silicon oxide film ( It includes a groove (first groove) in which an insulating member is formed, and polysilicon (conductive member) embedded in the groove and introduced with phosphorus. Further, since the silicon oxide film is not formed on the bottom surface portion of the groove, the polysilicon buried in the groove and the buried layer are electrically connected.

JP 2003-303960 A

  However, in the semiconductor device disclosed in Patent Document 1, the polysilicon (conductive member) embedded in the groove and the embedded layer are in contact with each other only at the bottom portion of the groove (the portion where the silicon oxide film is not formed). Therefore, the contact area between the polysilicon (conductive member) embedded in the groove and the embedded layer is reduced. Therefore, in the semiconductor device of Patent Document 1, the resistance at the contact portion between the polysilicon (conductive member) and the buried layer increases as the contact area between the polysilicon and the buried layer decreases. As a result, there is a problem that the power consumption of the semiconductor device increases.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device capable of suppressing an increase in power consumption of the semiconductor device and its semiconductor device. It is to provide a manufacturing method.

  The semiconductor device according to the present invention is formed on a semiconductor substrate, is formed in a semiconductor substrate so as to reach the buried layer, and has an insulating film formed on the inner surface thereof. 1 groove part, the 2nd groove part formed so that it may protrude further below from the lower end part of the 1st groove part, and the conductive member embedded in the 1st groove part and the 2nd groove part, and a buried layer and conductivity It is characterized in that the member is in contact. The “semiconductor substrate” is a wide concept including not only a single substrate but also a substrate in which an epitaxial layer is formed on the surface of the substrate.

  In the present invention, as described above, the second groove portion is formed so as to protrude further downward from the lower end portion of the first groove portion. Thereby, the conductive member embedded in the second groove portion and the embedded layer can be brought into contact not only at the bottom surface portion of the second groove portion but also at the side surface portion of the second groove portion. As a result, as compared with the conventional configuration in which the conductive member and the buried layer are in contact only in the bottom surface portion of the groove, the conductive member and the buried layer are in contact with each other also in the side surface portion of the second groove portion. The contact area between the conductive member and the buried layer can be increased. Therefore, the resistance at the contact portion between the conductive member and the buried layer can be reduced. That is, it is possible to suppress an increase in power consumption of the semiconductor device due to an increase in resistance at a contact portion between the conductive member and the buried layer.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a sectional view showing the structure of a trench gate type power MOSFET (semiconductor device) 100 according to the first embodiment of the present invention.

The power MOSFET 100 is formed on the surface of the silicon substrate 1 as shown in FIG. The silicon substrate 1 includes a substrate 1a and an epitaxial layer 1b formed by epitaxial growth on the substrate 1a. An n ⁺ type buried drain layer 2 is formed in the silicon substrate 1 by introducing predetermined impurities. The buried drain layer 2 is formed so as to straddle the substrate 1a and the epitaxial layer 1b. The buried drain layer 2 has an impurity concentration distribution such that the impurity concentration differs in the depth direction. Specifically, the buried drain layer 2 has a maximum impurity concentration at the interface 1c between the substrate 1a and the epitaxial layer 1b, and the impurity concentration gradually decreases from the interface 1c upward and downward. ing. An n ⁻ type drain drift region 3 made of the epitaxial layer 1 b is formed on the surface of the silicon substrate 1. The silicon substrate 1 and the buried drain layer 2 are examples of the “semiconductor substrate” and “buried layer” of the present invention, respectively.

In the silicon substrate 1, ap ⁺ type impurity region 4 a for isolating the element is formed so as to surround the buried drain layer 2. A p ⁺ -type impurity region 4b for isolating elements is formed above the impurity region 4a. An element isolation insulating film 5 made of SiO ₂ is formed in a region corresponding to the impurity region 4 b on the surface of the silicon substrate 1. A power MOSFET 100 is formed in a region surrounded by the impurity regions 4 a and 4 b and the element isolation insulating film 5.

In the region surrounded by the element isolation insulating film 5, a plurality (three in the first embodiment) of groove portions 6 are formed on the surface of the silicon substrate 1 at a predetermined interval in the X direction and perpendicular to the X direction. It is formed so as to extend in the (perpendicular to the plane of the paper). A gate insulating film 7 made of SiO ₂ is formed in the groove 6. A gate electrode 8 made of polysilicon is formed so as to be in contact with the gate insulating film 7. A p-type body region 9 is formed between two adjacent grooves 6, and an n ⁺ -type source region 10 is formed on the entire surface of the body region 9.

As shown in FIG. 1, among the plurality of trenches 6, the drain drift region 3 passes between the outermost trench 6 a in the X direction and the element isolation insulating film 5 to the buried drain layer 2. A groove 11 is formed so as to reach. An insulating film 12 made of SiO ₂ is formed on the inner surface of the groove 11. The groove 11 and the insulating film 12 are examples of the “first groove” and the “insulating film” in the present invention, respectively.

  Here, in the first embodiment, the groove 13 is formed so as to protrude further downward from the lower end of the groove 11. The groove 13 is formed so as to cross a region (interface 1c between the substrate 1a and the epitaxial layer 1b) where the impurity concentration of the buried drain layer 2 is maximum. The groove 13 has a cross-sectional shape that reflects the cross-sectional shape of the inner surface of the insulating film 12. Further, the lower end portion 13 a of the groove 13 is located in the region of the buried drain layer 2, and is formed so that the groove 13 does not protrude below the buried drain layer 2. An insulating film is not formed on the inner surface of the groove 13. The groove 13 is an example of the “second groove” in the present invention.

  Inside the groove 11 and the groove 13, a conductive member 14 made of tungsten or the like for drawing a drain current is embedded in contact with the insulating film 12. Since the insulating film is not formed on the inner surface of the groove portion 13, the conductive member 14 and the buried drain layer 2 are in contact with each other on the bottom surface portion 13 b and the side surface portion 13 c of the groove portion 13. As a result, the conductive member 14 embedded in the groove 13 and the embedded drain layer 2 are electrically connected. The conductive member 14 is an example of the “drain extraction layer” in the present invention.

A p ⁻ -type impurity region 15 is formed in a region between the outermost groove 6 a and the groove 11 among the plurality of grooves 6. An impurity region 15 a having an impurity concentration (p ⁺ ) higher than the impurity concentration (p ⁻ ) of the impurity region 15 is formed on the surface of the impurity region 15. The impurity region 15a is formed in order to reduce the contact resistance between the impurity region 15 and a contact plug 18c described later.

  On the surface of the silicon substrate 1, an interlayer insulating film 16 composed of insulating films 16a and 16b is formed. The groove 11 is formed so as to penetrate the insulating film 16a. Contact holes 17a to 17c are formed in the interlayer insulating film 16, and contact plugs 18a to 18c are formed in the contact holes 17a to 17c, respectively. The contact plug 18 a is connected to the conductive member 14 embedded in the groove portions 11 and 13. The contact plug 18b is connected to the source region 10, and the contact plug 18c is connected to the impurity region 15a.

  The power MOSFET 100 is configured to apply a positive voltage to the buried drain layer 2 via the contact plug 18 a and the conductive member 14. The power MOSFET 100 is configured to apply a ground voltage to the source region 10 through the contact plug 18b and to apply a ground voltage to the impurity region 15 through the contact plug 18c and the impurity region 15a. The power MOSFET 100 is configured to be turned on by forming a channel in the body region 9 along the side surface of the groove 6 when a voltage higher than the threshold voltage is applied to the gate electrode 8. ing. The power MOSFET 100 is configured such that a depletion layer is formed at the pn junction between the drain drift region 3 and the body region 9 when a voltage is applied between the source and drain.

  In the first embodiment, as described above, the groove portion 13 is formed so as to protrude further downward from the lower end portion of the groove portion 11. Thereby, the conductive member 14 embedded in the groove 13 and the buried drain layer 2 can be brought into contact not only at the bottom surface portion 13 b of the groove portion 13 but also at the side surface portion 13 c of the groove portion 13. Thereby, compared with the conventional configuration in which the conductive member and the buried layer are in contact with each other only in the bottom surface portion of the groove, the conductive member 14 and the buried drain layer 2 are also present in the side surface portion 13c of the groove portion 13. The contact area between the conductive member 14 and the buried drain layer 2 can be increased by the amount of contact. Accordingly, the resistance at the contact portion between the conductive member 14 and the buried drain layer 2 can be reduced. As a result, the on-resistance of the power MOSFET 100 can be reduced, so that an increase in power consumption of the power MOSFET 100 can be suppressed.

  In the first embodiment, as described above, the lower end portion 13 a of the groove 13 is positioned in the region of the buried drain layer 2. As a result, the conductive member 14 and the buried drain layer 2 can be brought into contact with each other on the entire bottom surface portion 13b and side surface portion 13c of the groove portion 13.

  In the first embodiment, as described above, the trench 13 is formed so as to cross the region (interface 1c between the substrate 1a and the epitaxial layer 1b) where the impurity concentration of the buried drain layer 2 is maximized. The region where the impurity concentration of the buried drain layer 2 is maximum is the region where the resistance of the buried drain layer 2 is the smallest. Thereby, the resistance at the contact portion between the conductive member 14 and the buried drain layer 2 can be further reduced.

  2 to 6 are cross-sectional views for explaining a manufacturing process of the power MOSFET 100 according to the first embodiment of the present invention.

  First, as shown in FIG. 2, after applying a diffusing agent containing an n-type impurity to a predetermined region of the substrate 1a, heat treatment is performed to introduce the n-type impurity into the substrate 1a. At this time, the substrate 1a has an impurity concentration distribution in which the impurity concentration on the surface of the substrate 1a is the highest and the impurity concentration gradually decreases from the surface of the substrate 1a downward. Thereafter, the epitaxial layer 1b is formed by epitaxially growing silicon on the surface of the substrate 1a. Then, by performing a heat treatment, impurities on the surface of the substrate 1a are diffused into the epitaxial layer 1b. As a result, the impurity concentration distribution has a maximum impurity concentration at the interface 1c between the substrate 1a and the epitaxial layer 1b, and an impurity concentration distribution that gradually decreases from the interface 1c in the upward and downward directions. A drain layer 2 is formed.

Thereafter, drain drift region 3, impurity regions 4a and 4b, and element isolation insulating film 5 made of SiO ₂ are formed. Then, a predetermined region on the surface of the drain drift region 3 is patterned by using a photolithography technique and an etching technique. Thereby, the groove part 6 is formed. Thereafter, a gate insulating film 7 made of SiO ₂ is formed by a thermal oxidation method. Then, the gate electrode 8 is formed in the groove 6. Specifically, a polysilicon layer is deposited so as to fill the groove 6. Then, after doping the impurity into the polysilicon layer, the polysilicon layer is etched back.

  Next, the body region 9 and the source region 10 are formed in the region between the groove portions 6. Specifically, a resist mask having a predetermined pattern is provided using a photolithography technique. Then, the body region 9 is formed by ion implantation of p-type impurities, and the source region 10 is formed by ion implantation of n-type impurities. Thereafter, the resist mask is removed.

  Next, a resist mask having a predetermined pattern is provided using a photolithography technique, and impurity regions 15 are formed by ion implantation of p-type impurities. Thereafter, the resist mask is removed. Next, a resist mask having a predetermined pattern is provided by using a photolithography technique, and an impurity region 15 a is formed on the surface of the impurity region 15 by ion implantation of p-type impurities. Thereafter, the resist mask is removed.

  Thereafter, heat treatment is performed using an RTA (Rapid Thermal Annealing) method to recover crystal defects during the ion implantation, and at the time of forming the body region 9, the source region 10, and the impurity regions 15 and 15a. The activated impurities are activated.

  Thereafter, an insulating film 16a is formed on the surfaces of the drain drift layer 3, the element isolation insulating film 5, the gate insulating film 7, the gate electrode 8, the source region 9, the impurity region 15 and the impurity region 15a.

  Next, a predetermined region of the insulating film 16a and the semiconductor substrate 1 is patterned by using a photolithography technique and an etching technique. As a result, the groove 11 is formed between the impurity region 15 and the element isolation insulating film 5. The groove 11 is formed so as not to cross the region (interface 1c between the substrate 1a and the epitaxial layer 1b) that reaches the buried drain layer 2 and has the highest impurity concentration in the buried drain layer 2.

Next, an insulating film 12 made of SiO ₂ is formed on the inner surface of the groove 11. Specifically, as shown in FIG. 3, the SiO ₂ layer 12a is formed by a CVD (Chemical Vapor Deposition) method. Thereafter, as shown in FIG. 4, a portion of the SiO ₂ layer 12a formed on the upper surface of the insulating film 16a and a portion formed on the bottom surface of the groove 11 are removed by anisotropic dry etching. Thereby, the insulating film 12 covering the inner surface of the groove 11 is formed.

  Next, as shown in FIG. 5, by performing anisotropic dry etching using the insulating film 12 as a mask, the groove 13 that protrudes further downward from the lower end of the groove 11 is formed. By using the insulating film 12 as a mask, the groove 13 is formed to have a cross-sectional shape reflecting the cross-sectional shape of the insulating film 12. At this time, the trench 13 traverses the region (interface 1c between the substrate 1a and the epitaxial layer 1b) where the impurity concentration of the buried drain layer 2 is maximum, and the lower end 13a of the trench 13 is a region of the buried drain layer 2. The groove 13 is formed so as to be located inside.

  Then, as shown in FIG. 6, a conductive member 14 such as tungsten is embedded in the groove portion 11 where the insulating film 12 is formed on the inner surface and the groove portion 13 where the insulating film is not formed on the inner surface. As a result, the conductive member 14 and the buried drain layer 2 are electrically connected in the entire bottom surface portion 13b and side surface portion 13c of the groove portion 13. Thereafter, the surfaces of the insulating film 16a and the conductive member 14 are planarized by CMP (Chemical Mechanical Polishing).

Next, as shown in FIG. 1, an insulating film 16b made of SiO ₂ is formed on the surfaces of the insulating film 16a and the conductive member 14 by the CVD method. Then, contact holes 17b and 17c are formed in the interlayer insulating film 16 (insulating film 16a and insulating film 16b), and a contact hole 17a is formed in the insulating film 16b. Finally, contact plugs 18a to 18c are formed in the contact holes 17a to 17c. In this way, the power MOSFET 100 according to the first embodiment is formed.

  In the first embodiment, as described above, after forming the insulating film 12 on the inner surface of the groove 11, the groove 13 can be easily formed by performing etching using the insulating film 12 as a mask.

(Second Embodiment)
FIG. 7 is a cross-sectional view showing the structure of a vertical bipolar transistor (semiconductor device) 200 according to the second embodiment of the present invention.

The bipolar transistor 200 is formed on the surface of the silicon substrate 1 as shown in FIG. An n ⁺ type buried collector layer 19 is formed in the silicon substrate 1 by introducing predetermined impurities. The buried collector layer 19 has the same configuration as the buried drain layer 2 of the first embodiment. An n ⁻ -type collector region 20 made of the epitaxial layer 1b is formed on the surface of the silicon substrate 1. The buried collector layer 19 is an example of the “buried layer” in the present invention.

  Impurity region 4a and impurity region 4b for isolating elements are formed in silicon substrate 1. Further, two element isolation insulating films 5 are formed on both sides of the bipolar transistor 200 on the surface of the silicon substrate 1. An insulating film 21 is formed in a region between the two element isolation insulating films 5 on the surface of the silicon substrate 1.

  A p-type well 22 as a base of the bipolar transistor 200 is formed on the surface of the silicon substrate 1 in the region 200 a between the insulating film 21 and the element isolation insulating film 5. A p-type well 23 as a base extraction layer and an n-type well 24 as an emitter are formed on the surface of the p-type well 22.

  On the surfaces of the element isolation insulating film 5, the insulating film 21, the p-type well 22, the p-type well 23, and the n-type well 24, an interlayer insulating film 25 including an insulating film 25a and an insulating film 25b is formed. .

  Further, as shown in FIG. 7, the surface of the silicon substrate 1 in the region 200 b between the insulating film 21 and the element isolation insulating film 5 penetrates the insulating film 25 a and the collector region 20 to the buried collector layer 19. A groove 11 is formed so as to reach. An insulating film 12, a groove 13, and a conductive member 14 are formed in the groove 11. The conductive member 14 is an example of the “collector lead layer” in the present invention. Since the positional relationship between the groove 13 and the buried collector layer 19 is the same as the positional relationship between the groove 13 and the buried drain layer 2 in the first embodiment, description thereof is omitted.

  Contact holes 26 a and 26 b are formed in the interlayer insulating film 25. A contact hole 26c is formed in the insulating film 25b. Contact plugs 27a to 27c are formed in the contact holes 26a to 26c, respectively. Contact plug 27a and contact plug 27b are connected to n-type well 24 and p-type well 23, respectively. The contact plug 27 c is connected to the conductive member 14 embedded in the groove portions 11 and 13.

  In the second embodiment, as described above, the conductive member 14 embedded in the groove 13 and the embedded collector layer 19 are provided by providing the groove 13 formed so as to protrude further downward from the lower end of the groove 11. Can be brought into contact not only with the bottom surface portion 13 b of the groove portion 13 but also with the side surface portion 13 c of the groove portion 13. As a result, the contact area between the conductive member 14 and the buried collector layer 19 can be increased, and the resistance at the contact portion between the conductive member 14 and the buried collector layer 19 can be reduced. Therefore, an increase in power consumption of bipolar transistor 200 due to an increase in resistance at the contact portion between conductive member 14 and buried collector layer 19 can be suppressed.

  Other effects of the second embodiment are the same as those of the first embodiment.

  The manufacturing process of the bipolar transistor 200 is the same as that of the first embodiment in the manufacturing process of the groove 11, the insulating film 12, the groove 13, and the conductive member 14, and the other manufacturing processes are general manufacturing of the bipolar transistor. Since it is the same as the process, the description is omitted.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the above-described embodiment, an example in which the groove 13 having a cross-sectional shape reflecting the cross-sectional shape of the insulating film 12 formed on the inner surface of the groove 11 is formed by forming the groove 13 by anisotropic dry etching. However, the present invention is not limited to this. For example, like the power MOSFET 300 of the first modification of the first embodiment shown in FIGS. 8 and 9, the inner surface of the groove portion 28 that protrudes further downward from the lower end portion of the groove portion 11 is wider than the inner surface of the insulating film 12. You may form as follows. As shown in FIG. 9, the width W <b> 1 in the direction orthogonal to the depth direction of the groove 28 is larger than the width W <b> 2 in the direction orthogonal to the depth direction of the region formed by the inner surface of the insulating film 12. Is formed. Thereby, the surface area of the groove part 28 can be made larger than the surface area of the groove part 13 of the first embodiment. As the surface area of the groove 28 is increased, the contact area between the conductive member 14 and the buried drain layer 2 can be increased. Thereby, the resistance at the contact portion between the conductive member 14 and the buried drain layer 2 can be further reduced. The groove 28 can be formed by performing isotropic dry etching using the insulating film 12 as a mask. The groove 28 is an example of the “second groove” in the present invention.

  In the power MOSFET 300 according to the first modified example, a corner is formed at the connection portion between the groove 28 and the groove 11, and thus a corner is also formed in the conductive member 14 embedded in the groove 28. Therefore, electric field concentration occurs at the corners of the conductive member 14. Therefore, like the power MOSFET 400 according to the second modification of the first embodiment shown in FIG. 10, the groove 29 may be formed so as to protrude further downward from the lower end of the groove 11. The groove portion 29 protrudes downward from the lower end portion of the groove portion 11 and is formed so as to be wider than the first portion 29a having a cross-sectional shape reflecting the cross-sectional shape of the insulating film 12 and the inner surface of the first portion 29a. And a second portion 29b having an inner surface. The width in the direction perpendicular to the depth direction of the second portion 29 b of the groove 29 is formed to be larger than the width in the direction perpendicular to the depth direction of the region formed by the inner surface of the insulating film 12. . The first portion 29a and the second portion 29b are smoothly connected. As a result, the contact area between the conductive member 14 embedded in the groove 29 and the buried drain layer 2 can be increased, so that the resistance at the contact portion between the conductive member 14 and the buried drain layer 2 is further reduced. can do. Further, since the first portion 29a has an inner surface shape reflecting the inner surface of the insulating film 12, no corner portion is formed in the conductive member 14 embedded in the connection portion between the groove 11 and the first portion 29a. Further, since the first portion 29 a and the second portion 29 b are smoothly connected, no corner portion is formed in the conductive member 14 embedded in the groove portion 29. Therefore, in the power MOSFET 400 according to the second modification, it is possible to suppress electric field concentration from occurring in the conductive member 14. The groove 29 is formed by forming the first portion 29a by performing anisotropic dry etching using the insulating film 12 as a mask, and then forming the second portion 29b by performing isotropic dry etching. It is possible to form. The groove 29 is an example of the “second groove” in the present invention.

  In the first and second embodiments, the buried drain layer 2 and the buried collector layer 19 are formed by forming an epitaxial layer on the surface of the substrate 1a after introducing impurities into the substrate 1a. However, the present invention is not limited to this, and the buried drain layer 2 or the buried collector layer 19 may be formed by ion implantation.

  Moreover, although the example using the conductive member 14 made of tungsten is shown in the above embodiment, the present invention is not limited to this, and other conductive members such as polysilicon into which impurities are introduced may be used. .

It is sectional drawing which shows power MOSFET by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of power MOSFET by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of power MOSFET by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of power MOSFET by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of power MOSFET by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of power MOSFET by 1st Embodiment of this invention. FIG. 6 is a cross-sectional view illustrating a bipolar transistor according to a second embodiment of the present invention. It is sectional drawing which shows power MOSFET by the 1st modification of 1st Embodiment of this invention. FIG. 9 is an enlarged cross-sectional view illustrating a periphery of a lower end portion of a groove portion of the power MOSFET illustrated in FIG. 8. It is sectional drawing which shows power MOSFET by the 2nd modification of 1st Embodiment of this invention.

Explanation of symbols

1 Silicon substrate (semiconductor substrate)
2 Buried drain layer (buried layer)
11 Groove (first groove)
12 Insulating film 13 Groove (second groove)
13a Lower end portion 13b Bottom surface portion 13c Side surface portion 14 Conductive member 28 Groove portion (second groove portion)
29 Groove (second groove)
100 Power MOSFET (semiconductor device)
200 Bipolar transistor (semiconductor device)
300 Power MOSFET (semiconductor device)
400 Power MOSFET (semiconductor device)

Claims (8)

A buried layer formed in a semiconductor substrate and doped with impurities;
A first groove portion formed in the semiconductor substrate so as to reach the buried layer and having an insulating film formed on an inner surface thereof;
A second groove formed so as to protrude further downward from the lower end of the first groove;
A conductive member embedded in the first groove and the second groove,
The semiconductor device, wherein the buried layer and the conductive member are in contact with each other.   The semiconductor device according to claim 1, wherein a lower end portion of the second groove portion is located in a region of the buried layer. The buried layer has a region where the impurity concentration is maximized,
The semiconductor device according to claim 1, wherein the second groove portion is formed so as to cross a region where the impurity concentration of the buried layer is maximized. The buried layer includes a buried drain layer;
The semiconductor device according to claim 1, wherein the conductive member includes a drain extraction layer electrically connected to the buried drain layer. The buried layer includes a buried collector layer;
The semiconductor device according to claim 1, wherein the conductive member includes a collector lead layer electrically connected to the buried collector layer.   The width of the direction orthogonal to the depth direction of the said 2nd groove part is larger than the width | variety of the direction orthogonal to the depth direction of the area | region formed by the inner surface of the said insulating film. The semiconductor device according to item. Forming a buried layer doped with impurities in a semiconductor substrate;
Forming a first groove in the semiconductor substrate to reach the buried layer;
Forming an insulating film on the inner surface of the first groove,
Forming a second groove portion by etching so as to protrude further downward from a lower end portion of the first groove portion;
And a step of embedding a conductive member in the first groove and the second groove. The step of forming the second groove portion includes
The method of manufacturing a semiconductor device according to claim 7, further comprising: forming the second groove portion by performing etching using the insulating film as a mask after forming the insulating film on an inner surface of the first groove portion. .

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