JP2009152485A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

A semiconductor device manufacturing method and a semiconductor device in which a strained SOI structure with high carrier mobility can be formed at low cost with few crystal defects.
A SiGe layer and a Si layer are sequentially formed on a Si substrate, and Si ₃ N ₄ films are formed thereon. Next, a support hole h that penetrates the Si ₃ N ₄ films 9 and 13 and the Si layer 5 and the SiGe layer is formed. Then, the SiO ₂ film 21 is formed so as to fill the support hole h. Next, the SiO ₂ film 21 and the Si layer 5 are partially etched to form a groove H that exposes the SiGe layer. Then, by etching the SiGe layer through the groove H, a cavity 25 is formed between the Si layer 5 and the Si substrate 1, and a SiO ₂ film is formed so as to fill the cavity 25. At this time, the compressive stress of the Si ₃ N ₄ film 9 and the tensile stress of the Si ₃ N ₄ film 13 are applied to the Si layer 5 to increase the strain of the Si layer 5.
[Selection] Figure 8

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  2. Description of the Related Art Conventionally, there is known a method of increasing the speed of a field effect transistor formed in a semiconductor layer by imparting strain to a semiconductor layer having a channel region to improve mobility of electrons and holes. Here, Non-Patent Document 1 discloses a method of applying strain to the entire Si thin film layer (ie, SOI layer) on the buried insulating layer (ie, BOX layer) in the SOI (Silicon On Insulator) structure. .

On the other hand, Patent Document 1 discloses a method (so-called SBSI method) in which an SOI transistor can be formed at low cost by partially forming an SOI structure on a bulk Si substrate. In the SBSI method, a Si / SiGe layer is formed on a Si substrate, and only the SiGe layer is selectively removed by utilizing a difference in etching rate between Si and SiGe, whereby the Si substrate and the Si layer are removed. A cavity is formed, and an insulating layer is formed in the cavity. In this way, an SOI structure composed of the insulating layer and the Si layer is formed on the Si substrate. According to the SBSI method, the thickness of the Si layer (that is, the SOI layer) can be controlled systematically and the thickness can be reduced, and the SOI structure can be formed at low cost.
JP 2005-354024 A K. Rim, K.M. Chan, D.C. Boyd, J .; Ott, N.M. Kiymko, F.M. Casdone, L.M. Tai, S .; Koester, M.C. Cobb, D.C. Canaperi, B.M. To, E .; Duch, I.D. Babich, R.A. Carruthers, P.M. Saunders, G.M. Walker, Y. et al. Zhang, M .; Steen, and M.M. Ieon “Fabrication and Mobility Characeristics of Ultra-thin Strained Si Dirty on Insulator (SSDOI) MOSFETs” 2003 IEEE 3.1.1-3.1.4.

The conventional manufacturing method as disclosed in Non-Patent Document 1 uses an expensive SOI wafer, and it is necessary to epitaxially grow the SiGe layer thickly or to perform a high-temperature oxidation process. For this reason, there is a problem that the cost is high and it is difficult to control crystal defects in the SOI layer (that is, the Si layer that forms the upper layer of the SOI structure).
In the conventional manufacturing method, the same strained SOI layer is formed on the entire surface of the wafer. However, when the mobility of electrons and holes is improved by two-dimensional tensile strain, it is caused by strain such as deterioration in junction breakdown voltage and increase in junction leakage. It was not possible to satisfy all the characteristics in the trade-off relationship. In particular, since the strain dependency of mobility differs between electrons and holes, the transistor performance of Pch and Nch cannot be improved at the same time.
The present invention has been made in view of such circumstances, and gives the optimum strain according to various devices such as Pch and Nch, or low voltage drive device and low voltage drive device, and carrier mobility. An object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device which can form a strained SOI structure having a high strain at a low cost with few crystal defects.

  [Invention 1] A method of manufacturing a semiconductor device of Invention 1 includes a step of forming a first semiconductor layer on a semiconductor substrate, a step of forming a second semiconductor layer on the first semiconductor layer, and the second semiconductor layer. Forming a surface insulating film for generating strain on the second semiconductor layer; etching the surface insulating film; the second semiconductor layer; and the first semiconductor layer; A step of forming a first groove penetrating the second semiconductor layer and the first semiconductor layer, a step of forming a support in the first groove, the surface insulating film, and the second semiconductor layer. Etching to form a second groove exposing the first semiconductor layer, and etching the first semiconductor layer through the second groove, thereby forming the second semiconductor layer and the semiconductor substrate. A step of forming a cavity in between, and the surface insulating film It is characterized in that comprises the step of applying a force to said second semiconductor layer, and forming an insulating film on the cavity.

Here, the “semiconductor substrate” of the present invention is, for example, a bulk silicon (Si) substrate, the “first semiconductor layer” is, for example, a single crystal silicon germanium (SiGe) layer, and the “second semiconductor layer” is, for example, It is a single crystal Si layer. The SiGe layer and the Si layer can be formed by, for example, an epitaxial growth method. The “support” of the present invention is made of, for example, a silicon oxide (SiO ₂ ) film, a silicon nitride (Si ₃ N ₄ ) film, or a semiconductor film such as polysilicon (Poly-Si). “Strain” means strain of the crystal lattice.

Furthermore, the “surface insulating film” of the present invention is made of, for example, a Si ₃ N ₄ film or a SiO ₂ film, or a film in which these are laminated, and has a force (for example, stress) that acts on at least the second semiconductor layer. It is. “Applying the force of the surface insulating film to the second semiconductor layer” means that a load corresponding to the direction and magnitude of the stress of the surface insulating film is applied from the surface insulating film to the second semiconductor layer. Meaning. For example, as shown in FIG. 20A, when the surface insulating film (for example, the Si ₃ N ₄ film 9) has a compressive stress, the second semiconductor layer (for example, the Si layer 5) in contact with the surface insulating film is formed. A compressive load is applied according to the direction and magnitude of the compressive stress. As shown in FIG. 20B, when the surface insulating film (for example, Si ₃ N ₄ film 13) has a tensile stress, it is pulled to the second semiconductor layer (for example, Si layer 5) in contact with the surface insulating film. A tensile load is applied according to the direction and magnitude of the stress. In this way, the strain of the second semiconductor layer is increased by “acting the force of the surface insulating film on the second semiconductor layer”. When the amount of strain of the second semiconductor layer is zero (0), strain is generated in the second semiconductor layer by “applying the force of the surface insulating film to the second semiconductor layer”.
The “insulating film” of the present invention is made of, for example, a SiO ₂ film, a Si ₃ N ₄ film, or a film in which these are laminated.

  According to the method for manufacturing a semiconductor device of the first aspect, a strained SOI structure having high carrier mobility can be formed only at a required location on a semiconductor substrate. For example, a strained SOI structure can be formed only in a region where a pMOS transistor is formed and / or a region where an nMOS transistor is formed. Further, a strain opposite to compression or tension can be applied to each region independently. Since it is not necessary to use an expensive SOI wafer having a strained SOI structure on the entire surface of the substrate, the manufacturing cost of the semiconductor device can be reduced. In addition, when forming a strained SOI structure, for example, it is not necessary to form a thick SiGe layer or perform a high-temperature oxidation process, thereby suppressing the occurrence of crystal defects in the SOI layer (ie, the second semiconductor layer). can do.

  [Invention 2] A method of manufacturing a semiconductor device of Invention 2 includes a step of forming a first semiconductor layer on a semiconductor substrate, a step of forming a second semiconductor layer on the first semiconductor layer, and the second semiconductor layer. Forming a surface insulating film for generating strain on the second semiconductor layer; etching the surface insulating film; the second semiconductor layer; and the first semiconductor layer; A step of forming a first groove penetrating the second semiconductor layer and the first semiconductor layer, a step of forming a support in the first groove, the surface insulating film, and the second semiconductor layer. Etching to form a second groove exposing the first semiconductor layer, and etching the first semiconductor layer through the second groove, thereby forming the second semiconductor layer and the semiconductor substrate. A step of forming a cavity in between, and the surface insulating film Applying a force to the second semiconductor layer, and forming an insulating film on the upper surface of the semiconductor substrate facing the inside of the cavity and the lower surface of the second semiconductor layer while leaving the cavity And a step of forming a conductive film in the cavity where the insulating film is formed.

  According to such a method, as in the first aspect, the manufacturing cost of the semiconductor device can be reduced, and the generation of crystal defects in the SOI layer (that is, the second semiconductor layer) can be suppressed. Further, the conductive film can be used as, for example, a back gate electrode. In that case, the threshold voltage of the MOS transistor can be controlled by the back gate bias.

[Invention 3, 4] The method for manufacturing a semiconductor device according to Invention 3 is the method for manufacturing a semiconductor device according to Invention 1 or 2, wherein the step of forming the cavity and the force of the surface insulating film are applied to the second semiconductor. The step of acting on the layer is performed in parallel.
According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first or second aspect of the present invention, wherein the surface insulating film is subjected to a heat treatment after the step of forming the hollow portion so that the surface insulating film has a force. The method further includes a step of changing and applying the changed force to the second semiconductor layer.
According to the method for manufacturing a semiconductor device of inventions 3 and 4, when increasing the strain of the second semiconductor layer, a cavity exists under the second semiconductor layer, and the lower surface of the second semiconductor layer is covered with another film. Since it is not fixed, the strain can be increased with a relatively small force.

[Invention 5] A method for manufacturing a semiconductor device according to Invention 5 is the method for manufacturing a semiconductor device according to any one of Inventions 1 to 4, wherein a region where a pMOS transistor is formed and an nMOS transistor are formed on the semiconductor substrate. And forming the surface insulating film includes forming a first surface insulating film having compressive stress on the second semiconductor layer in the region where the pMOS transistor is formed, and the nMOS transistor. Forming a second surface insulating film having a tensile stress on the second semiconductor layer in a region where the film is formed.
According to the method for manufacturing a semiconductor device of the fifth aspect, the second semiconductor layer having compressive strain is formed on the semiconductor substrate in the region where the pMOS transistor is formed (hereinafter also referred to as pMOS region), and the nMOS transistor is formed. A second semiconductor layer having tensile strain can be formed on a semiconductor substrate in a region to be formed (hereinafter also referred to as an nMOS region).

  Note that “compressive strain” refers to strain generated by receiving a compressive load, and is strain in which the interstitial distance in the crystal lattice is reduced. When the surface insulating film has a compressive stress, a compressive load acts on the second semiconductor layer from the surface insulating film, and compressive strain is generated in the second semiconductor layer in response to the compressive load. “Tensile strain” refers to strain generated by receiving a tensile load, and is strain in which the interstitial distance in the crystal lattice is expanded. When the surface insulating film has a tensile stress, a tensile load acts on the second semiconductor layer from the surface insulating film, and tensile strain is generated in the second semiconductor layer in response to the tensile load.

  [Invention 6] The semiconductor device manufacturing method of Invention 6 is the method of manufacturing a semiconductor device according to any one of Inventions 1 to 5, wherein the surface insulating film is removed from the second semiconductor layer, and the surface Forming a gate electrode through the gate insulating film on the surface insulating film from which the insulating film has been removed, and forming a source or drain by introducing impurities into the second semiconductor layer on both sides of the gate electrode; , Further comprising.

  According to such a method, for example, the second semiconductor layer having compressive strain can be formed on the semiconductor substrate in the pMOS region, and a pMOS transistor with improved hole mobility can be formed. In addition, for example, a second semiconductor layer having tensile strain can be formed on the semiconductor substrate in the nMOS region, and an nMOS transistor with improved electron mobility can be formed.

  [Invention 7] A semiconductor device of Invention 7 includes a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate via a first insulating film, the semiconductor layer in a region where a pMOS transistor is formed, and an nMOS transistor. A second insulating film provided on the semiconductor substrate so as to surround the semiconductor layer in a region to be formed in plan view, and the semiconductor layer in the region in which the pMOS transistor is formed has a compressive strain The semiconductor layer in the region where the nMOS transistor is formed has a tensile strain. That is, it is possible to form the second semiconductor layer having the optimum strain for each of various devices.

Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, parts having the same configuration are denoted by the same reference numerals, and redundant description thereof is omitted.
(1) First Embodiment [Example of Semiconductor Device Manufacturing Method and Configuration]
1 to 12 are views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIGS. 1A to 12A are plan views, and FIGS. (B) is sectional drawing when Fig.1 (a)-FIG.12 (a) are each cut | disconnected by X1-X'1-X12-X'12 line | wire.

First, as shown in FIGS. 1A and 1B, a region where a pMOS transistor is formed (hereinafter referred to as a pMOS region) and a region where an nMOS transistor is formed (hereinafter referred to as an nMOS region). A single crystal silicon buffer (Si-buffer) layer (not shown) is formed on a bulk Si substrate 1 having the following structure, a single crystal silicon germanium (SiGe) layer 3 is formed thereon, and a single crystal is formed thereon. The silicon (Si) layer 5 is formed. The Si-buffer layer, the SiGe layer 3 and the Si layer 5 are continuously formed by, for example, an epitaxial growth method. Next, a silicon oxide (SiO ₂ ) film 7 is formed on the Si layer 5, and a silicon nitride (Si ₃ N ₄ ) film 9 is formed thereon. Here, the Si ₃ N ₄ film 9 is a film having a compressive stress in the horizontal direction (that is, the vertical direction and the horizontal direction in plan view). The SiO ₂ film 7 and the Si ₃ N ₄ film 9 are formed by, for example, CVD (Chemical Vapor Deposition).

Next, as shown in FIGS. 2A and 2B, the Si ₃ N ₄ film 9 is partially etched (that is, patterned) by the photolithography technique and the etching technique, so that the SiO ₂ film in the nMOS region is obtained. 7, the Si ₃ N ₄ film 9 is removed, and the Si ₃ N ₄ film 9 is left on the SiO ₂ film 7 in the pMOS region. Such patterning of the Si ₃ N ₄ film 9 may be carried out in either dry etching or wet etching, in any case, the Si ₃ N ₄ film 9 SiO ₂ film 7 below serves as an etching stopper.

Next, as shown in FIGS. 3A and 3B, an SiO ₂ film 11 is formed on the Si substrate 1 after the Si ₃ N ₄ film 9 is patterned. Then, a Si ₃ N ₄ film 13 is formed on the Si substrate 1 after the SiO ₂ film 11 is formed. Here, the Si ₃ N ₄ film 13 is a film having a tensile stress in the horizontal direction. The SiO ₂ film 11 and the Si ₃ N ₄ film 13 are formed by, for example, CVD.
Next, as shown in FIG. 4 (a) and (b), by a photolithography technique and an etching technique, Si ₃ the N ₄ film 13 is partially etched, Si ₃ from the top SiO ₂ film 7 in the pMOS region The N ₄ film 13 is removed and the Si ₃ N ₄ film 13 is left on the SiO ₂ film 7 in the nMOS region. Patterning such the Si ₃ N ₄ film 13 may be carried out in either dry etching or wet etching, in any case, the Si ₃ N ₄ film 13 SiO ₂ film 7 and 11 below serves as an etching stopper .

After patterning of the Si ₃ N ₄ film 9 and 13, together with the compressive load corresponding to the direction and magnitude of the compressive stress the Si ₃ N ₄ film 9 has works from the Si ₃ N ₄ film 9 on the Si layer 5 in the pMOS region , the Si ₃ N ₄ film 13 tensile load corresponding to the direction and magnitude of a tensile stress is to work from the Si ₃ N ₄ film 13 to the Si layer 5 in the nMOS region. Thereby, compressive strain is generated in the Si layer 5 in the pMOS region, and tensile strain is generated in the Si layer 5 in the nMOS region. However, at the stage shown in FIGS. 4A and 4B, the Si layer 5 has a Cubic structure, and the lower side thereof is in contact with the SiGe layer 3 and its crystal structure is fixed. Strain and tensile strain are negligible.

Next, as shown in FIGS. 5A and 5B, the SiO ₂ film 7, the Si layer 5, the SiGe layer 3, and the Si-buffer layer (not shown) are partially formed by photolithography technique and etching technique, respectively. Etch. Thus, a support hole h having the Si substrate 1 as a bottom surface is formed in a region overlapping with the element isolation region (that is, a region where the SOI structure is not formed) in plan view. In this etching step, the etching may be stopped on the surface of the Si substrate 1, or the Si substrate 1 may be over-etched to form a recess.

Next, as shown in FIGS. 6A and 6B, a SiO ₂ film 21 is formed on the Si substrate 1 so as to fill the support hole h. This SiO ₂ film 21 is formed by, for example, CVD. Then, as shown in FIGS. 7A and 7B, the SiO ₂ films 21, 7, the Si layer 5, the SiGe layer 3, and the Si-buffer layer (not shown) are respectively formed by photolithography technique and etching technique. In sequence, partial etching is performed. As a result, a support made of the SiO ₂ film 21 is formed, and a groove H having the bottom surface of the Si substrate 1 is formed in a region overlapping the element isolation region in plan view. In the step of forming the groove H, the etching may be stopped on the surface of the Si substrate 1, or the Si substrate 1 may be over-etched to form a recess.

Next, for example, a hydrofluoric acid solution is brought into contact with the respective side surfaces of the Si layer 5 and the SiGe layer 3 through the groove H, and the SiGe layer 3 is selectively etched and removed. Thereby, as shown in FIGS. 8A and 8B, a cavity 25 is formed between the Si layer 5 and the Si substrate 1. In wet etching using a hydrofluoric acid solution, the etching rate of SiGe is higher than that of Si (that is, the etching selectivity with respect to Si is large), so only the SiGe layer is etched and removed while leaving the Si layer 5. Is possible. After the formation of the cavity 25, the Si layer 5 is supported by the support 21. Further, at the stage shown in FIGS. 8A and 8B, since the lower side of the Si layer 5 is not in contact with another film (that is, not supported), the Si ₃ N ₄ films 9 and 13 Due to the load acting on the Si film 5, the strain of the Si film 5 increases. That is, the compressive strain increases in the SiGe layer 3 in the pMOS region, and the tensile strain increases in the SiGe layer 3 in the nMOS region.

Note that, in the step of etching the SiGe layer 3 described above, hydrofluoric acid overwater, ammonia overwater, or hydrofluoric acid overwater may be used instead of the hydrofluoric acid solution. Overwater is hydrogen peroxide water. Also in this case, since the etching rate of SiGe is higher than that of Si, the SiGe layer 3 can be selectively removed.
Next, as shown in FIGS. 9A and 9B, a SiO ₂ film 27 is formed on the Si substrate 1 to completely fill the cavity. The SiO ₂ film 27 is formed by, for example, thermal oxidation or CVD, or a film forming process that combines thermal oxidation and CVD. When the SiO ₂ film 27 is formed by CVD or a film forming process combining thermal oxidation and CVD, the SiO ₂ film 27 can be formed thick and both the cavity and the groove H are completely buried. Can do.

In the step of forming the cavity 25 shown in FIGS. 8A and 8B and the process of embedding the cavity 25 shown in FIGS. 9A and 9B, the Si ₃ N ₄ films 9 and 13 are used to form the Si layer. Stress is transferred to 5 (ie, a load is applied), compressive strain increases in the Si layer 5 in the pMOS region, and tensile strain increases in the Si layer 5 in the nMOS region. This increased strain can be maintained by filling the cavity 25 formed under the Si layer 5 with the SiO ₂ film 27. That is, by filling the cavity 25 with the SiO ₂ film 27, the lower side of the Si layer 5 comes into contact with the SiO ₂ film 27, and the strain of the Si layer 5 is fixed by the SiO ₂ film 27.

Next, the SiO ₂ film 27 and the support 21 are removed while being planarized by, for example, CMP (Chemical Mechanical Polish), and the Si ₃ N ₄ films 9 and 13 are removed as shown in FIGS. Expose the surface. In this planarization step, the Si ₃ N ₄ films 9 and 13 function as stoppers for the CMP polishing pad. Subsequently, the Si ₃ N ₄ films 9 and 13 are removed by wet etching, for example, with hot phosphoric acid, and the SiO ₂ film 7 is removed by wet etching, for example, using a dilute hydrofluoric acid solution. Expose the surface. As a result, as shown in FIGS. 10A and 10B, an SOI composed of a SiO ₂ film (ie, BOX layer) 27 and a Si layer 5 (ie, SOI layer) on the bulk Si substrate 1. The SOI substrate 10 having the structure is completed. As described above, since the compressive strain of the Si layer 5 in the pMOS region and the tensile strain of the Si layer 5 in the nMOS region are fixed from the lower side by the SiO ₂ film 27, even after the removal of the Si ₃ N ₄ film. The compressive strain and tensile strain described above can be maintained.

Incidentally, as shown in FIG. 11 (a), the periphery of the Si layer 5 in the pMOS region, and the SiO ₂ film 21, 27 surrounding the Si layer 5 in a plan view are formed, these SiO ₂ films 21, 27 functions as an element isolation layer. In addition, SiO ₂ films 21 and 27 surrounding the Si layer 5 in plan view are also formed around the Si layer 5 in the nMOS region, and the SiO ₂ films 21 and 27 function as element isolation layers. Become.

Next, a pMOS transistor and an nMOS transistor are formed on the SOI substrate 10 shown in FIGS. That is, as shown in FIGS. 13A and 13B, the gate insulating film 31 is formed on the surface of the Si layer 5. The gate insulating film 31 is, for example, a silicon oxide film (SiO ₂ ) or silicon oxynitride film (SiON) formed by thermal oxidation, or a High-k material film. Next, a polysilicon (poly-Si) film is formed on the entire surface of the SOI substrate 10 on which the gate insulating film 31 is formed. The polysilicon film is formed by, for example, a CVD method. Here, impurities are introduced into the polysilicon film by ion implantation or in-situ to make the polysilicon film conductive.

Specifically, p-type impurities are ion-implanted into the polysilicon film in the pMOS region while the entire nMOS region is covered with the photoresist, and then the nMOS region is covered in the state where the entire pMOS region is covered with the photoresist. N-type impurities are ion-implanted into the polysilicon film. Thereafter, the entire SOI substrate 10 is subjected to heat treatment to simultaneously diffuse p-type impurities and n-type impurities. As a result, the polysilicon film in the pMOS region can have p-type conductivity, and the polysilicon film in the nMOS region can have n-type conductivity.
Next, the polysilicon film is partially etched by a photolithography technique and an etching technique. Thereby, the gate electrode 33 is formed on the gate insulating film 31 in the pMOS region, and the gate electrode 33 is formed on the gate insulating film 31 in the nMOS region.

  Next, impurities are ion-implanted into the Si layer 5 using the gate electrodes 33 and 34 as a mask, heat treatment is performed, and a p-type source or drain (hereinafter referred to as an S / D layer) is applied to the Si layer 5 in the pMOS region. 35, and an n-type S / D layer 36 is formed on the Si layer 5 in the nMOS region. Specifically, p-type impurities are ion-implanted into the Si layer 5 in the pMOS region while the entire nMOS region is covered with the photoresist, and then the nMOS region is covered in the state where the entire pMOS region is covered with the photoresist. An n-type impurity is ion-implanted into the Si layer 5. Thereafter, the entire SOI substrate 10 is subjected to heat treatment to simultaneously diffuse p-type impurities and n-type impurities. Thereby, the p-type S / D layer 35 can be formed on the Si layer 5 in the pMOS region, and the n-type S / D layer 36 can be formed on the Si layer 5 in the nMOS region.

  Next, an interlayer insulating film (not shown) is formed on the SOI substrate 10, and this interlayer insulating film is partially etched to form a first contact hole (not shown) having the gate electrodes 33 and 34 as bottom surfaces. ) And a second contact hole (not shown) having the S / D layers 35 and 36 as bottom surfaces. Then, an Al wiring or a plug electrode is formed inside the contact hole. In this way, the pMOS transistor 60 and the nMOS transistor 70 are completed.

  In FIGS. 12A and 12B, a so-called LDD layer (Lightly Doped Drain) is not shown, but an LDD layer may be formed in this embodiment mode. In that case, before forming the S / D layer 35, a p-type LDD layer is formed in the Si layer 5 in the pMOS region by ion-implanting p-type impurities into the Si layer 5 using the gate electrode 33 as a mask. be able to. Similarly, before forming the S / D layer 36, an n-type LDD layer is formed in the Si layer 5 in the nMOS region by ion-implanting n-type impurities into the Si layer 5 using the gate electrode 34 as a mask. Can do. Then, after forming the LDD layer, sidewalls (not shown) made of an insulating film are formed on the side walls of the gate electrodes 33 and 34, and p-type impurities and n-type are formed using the sidewalls and the gate electrodes 33 and 34 as masks. Each impurity is selectively ion-implanted. Thereby, the S / D layers 35 and 36 can be formed adjacent to the LDD layer.

[Relationship between stress and mobility]
Next, the relationship between the stress of the surface insulating film (for example, the Si ₃ N ₄ films 9 and 13) and the mobility of the MOS transistor will be described.
FIG. 18 is a diagram schematically showing the relationship between the stress [MPa] possessed by the surface insulating film and the ratio [%] of the mobility improvement of the MOS transistor. It is schematically shown that the mobility of electrons is improved in the biaxial tensile stress in the plane direction and the mobility of holes is improved by the biaxial compressive stress in the plane direction. The horizontal axis of FIG. 18 shows the stress that the surface insulating film has. On the horizontal axis, the closer to (+), the greater the compressive stress, and the closer to (−), the greater the tensile stress. Also, the vertical axis in FIG. 18 indicates the rate of mobility improvement. On the vertical axis, the closer to (+), the higher the mobility, and the closer to (−), the lower the mobility. Note that, on the vertical axis in FIG. 18, the mobility when the strain is not generated in the crystal lattice of the SOI layer is a reference value (that is, 0%).

  As shown in FIG. 18, in the pMOS transistor, the mobility improves as the compressive stress of the surface insulating film increases. This is because the compressive stress of the surface insulating film acts on the SOI layer (for example, the Si layer 5) as a compressive load, and compressive strain is generated in the SOI layer in response to the compressive load. When compressive strain is generated in the SOI layer, the interstitial distance is reduced and holes are easily moved. For this reason, the mobility of the pMOS transistor is improved.

On the other hand, in an nMOS transistor, the mobility increases as the tensile stress of the surface insulating film increases. This is because the tensile stress of the surface insulating film acts on the SOI layer (for example, the Si layer 5) as a tensile load, and compressive strain is generated in the SOI layer (for example, the Si layer 5) by receiving this tensile load. . When tensile strain occurs in the SOI layer, the interstitial distance increases and electrons move easily. For this reason, the mobility of the nMOS transistor is improved.
Therefore, in the present invention, at the design stage of the pMOS transistor 60, the relationship between the Si ₃ N ₄ film 9 and the mobility of the pMOS transistor 60 is investigated by conducting experiments or simulations in advance, and the desired mobility is supported. It is desirable to obtain the compressive stress. Similarly, in the present invention, at the design stage of the nMOS transistor 70, the relationship between the Si ₃ N ₄ film 13 and the mobility of the pMOS transistor 70 is investigated by conducting experiments or simulations in advance, and the desired mobility is supported. It is desirable to determine the tensile stress

Further, the stress characteristics of the surface insulating film vary depending on the film forming conditions. For example, to form a Si ₃ N ₄ film 9 and 13 by the CVD, the presence of plasma at the time of film formation, gas species to be used, the mixing ratio of the gas, the pressure in the chamber such as, the Si ₃ N ₄ film 9 , 13 varies in the tensile or compressive direction. In addition, the tendency of this variation varies depending on the type of film forming apparatus used. Therefore, for example, with respect to the Si ₃ N ₄ films 9 and 13, experiments or simulations are performed in advance for each type of film forming apparatus to obtain target stress characteristics (that is, stress characteristics corresponding to desired mobility). It is desirable to find such optimum film forming conditions. Thereby, a semiconductor device in which the mobility of both the pMOS transistor 60 and the nMOS transistor 70 is improved can be manufactured with high reproducibility.

As described above, according to the first embodiment of the present invention, the strained SOI structure with high carrier mobility can be formed only in necessary places (for example, the pMOS region and the nMOS region) on the Si substrate 1. it can. Since it is not necessary to use an expensive SOI wafer having a strained SOI structure on the entire surface of the Si substrate 1, the manufacturing cost of the semiconductor device can be reduced.
Further, when forming the strained SOI structure, for example, it is not necessary to form a thick SiGe layer or perform a high-temperature oxidation process, and the strained SOI layer is formed in an island shape not on the entire wafer surface but on the entire wafer. Therefore, generation of crystal defects in the Si layer 5 can be suppressed.

In the first embodiment, the Si substrate 1 corresponds to the “semiconductor substrate” of the present invention, the SiGe layer 3 corresponds to the “first semiconductor layer” of the present invention, and the Si layer 5 corresponds to the “second semiconductor of the present invention. It corresponds to “layer”. The Si ₃ N ₄ film 9 corresponds to the “first surface insulating film” of the present invention, and the Si ₃ N ₄ film 13 corresponds to the “second surface insulating film” of the present invention. Further, the support hole h corresponds to the “first groove” of the present invention, and the groove H corresponds to the “second groove” of the present invention. The SiO ₂ film 27 corresponds to the “insulating film” or “first insulating film” of the present invention, and the combination of the SiO ₂ film 21 and the SiO ₂ film 27 corresponds to the “second insulating film” of the present invention. ing.

(2) Second Embodiment In the first embodiment described above, the case where the Si layer 5 is disposed on the Si substrate 1 via the SiO ₂ film 27 has been described. However, the present invention is not limited to the SOI structure. For example, an SOI structure in which the SiO ₂ film 51, the polysilicon film 53, the SiO ₂ film 51, and the Si layer 5 are sequentially arranged on the Si substrate 1 may be used. With such a structure, the polysilicon film 53 can be used for the back gate electrode.

13 to 17 are views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention, in which FIGS. 13 (a) to 17 (a) are plan views, and FIGS. 13 (b) to 17 are shown. (B) is sectional drawing when Fig.13 (a)-FIG.17 (a) are each cut | disconnected by X13-x'13-X17-X'17 line | wire.
13A and 13B, the process up to the step of forming the cavity 25 between the Si layer 5 and the Si substrate 1 is the same as that in the first embodiment. In the second embodiment, after forming the cavity 25, the Si substrate 1 is thermally oxidized to form SiO ₂ films 51 on the upper surface of the Si substrate 1 facing the inside of the cavity 25 and the lower surface of the Si layer 5. . Subsequently, as shown in FIGS. 14A and 14B, for example, a polysilicon film 53 is formed on the Si substrate 1 to completely fill the cavity, and the p-type impurity or n is added to the polysilicon film 53. Type impurities are introduced. The polysilicon film 53 is formed by, for example, CVD, and p-type impurities or n-type impurities are introduced into the polysilicon film 53 by, for example, in-situ.

In the step of forming the cavity portion 25 and the step of filling the cavity portion 25, stress is transferred from the Si ₃ N ₄ films 9 and 13 to the Si layer 5 (ie, a load is applied), and the Si layer in the pMOS region. 5, the compressive strain increases, and the tensile strain increases in the Si layer 5 in the nMOS region. The increased strain can be maintained by filling the cavity 25 formed under the Si layer 5 with the polysilicon film 53. That is, by filling the cavity 25 with the polysilicon film 53, the lower side of the Si layer 5 comes into contact with the polysilicon film 53 via the SiO ₂ film 51, and the strain of the Si layer 5 is caused by the polysilicon film 53. Fixed.
In the present invention, the cavity 25 may be embedded using, for example, a metal film instead of the polysilicon film. Thereby, a back gate electrode made of the polysilicon film 53 or the metal film can be formed in the cavity 25.

Next, for example, anisotropic etching is performed on the polysilicon film 53 to remove the polysilicon film 53 from the Si substrate 1 other than the cavity. Then, a SiO ₂ film 55 (see FIG. 15A) is formed on the Si substrate 1 to completely fill the groove H. Next, the SiO ₂ films 55 and 21 on the Si substrate 1 are removed while being flattened by CMP, for example, and the surfaces of the Si ₃ N ₄ films 9 and 13 are exposed. In this planarization step, the Si ₃ N ₄ films 9 and 13 function as stoppers for the CMP polishing pad. Subsequently, the Si ₃ N ₄ films 9 and 13 are removed by wet etching, for example, with hot phosphoric acid, and the SiO ₂ film 7 is removed by wet etching, for example, using a dilute hydrofluoric acid solution. ) And (b), the surface of the Si layer 5 is exposed. As a result, the SiO ₂ film 51, the polysilicon film 53, the SiO ₂ film (that is, the BOX layer) 51, and the Si layer (that is, the SOI layer) 5 are formed on the bulk Si substrate 1, the Si substrate 1. An SOI substrate 10 'having an SOI structure consisting of

As described above, since the compressive strain of the Si layer 5 in the pMOS region and the tensile strain of the Si layer 5 in the nMOS region are fixed from the lower side by the polysilicon film 53, the Si ₃ N ₄ films 9 and 13 Even after the removal, the compression strain and the tensile strain can be maintained.
Incidentally, as shown in FIG. 15 (a), the periphery of the Si layer 5 in the pMOS region, and the SiO ₂ film 21,55 surrounding the Si layer 5 in a plan view are formed, these SiO ₂ films 21 , 55 function as element isolation layers. In addition, SiO ₂ films 21 and 55 surrounding the Si layer 5 in plan view are also formed around the Si layer 5 in the nMOS region, and these SiO ₂ films 21 and 55 function as element isolation layers. It becomes.

  Next, a pMOS transistor and an nMOS transistor are formed on the SOI substrate 10 'shown in FIGS. That is, as shown in FIGS. 16A and 16B, the gate insulating film 31 is formed on the surface of the Si layer 5. Next, a polysilicon film is formed on the entire surface of the SOI substrate 10 ′ on which the gate insulating film 31 is formed. As in the first embodiment, p-type impurities are introduced into the polysilicon film in the pMOS region and n-type impurities are introduced into the polysilicon film in the nMOS region, for example, by selective ion implantation using photolithography.

  Next, the polysilicon film is partially etched by a photolithography technique and an etching technique to form a gate electrode 33 on the gate insulating film 31 in the pMOS region and a gate electrode on the gate insulating film 31 in the nMOS region. 34 is formed. Thereafter, as in the first embodiment, for example, impurities are ion-implanted into the Si layer 5 using the gate electrodes 33 and 34 as a mask, and a heat treatment is performed to form a p-type S / D layer 35 in the Si layer 5 in the pMOS region. At the same time, an n-type S / D layer 36 is formed on the Si layer 5 in the nMOS region. Although the LDD layer is not shown in FIGS. 16A and 16B, LDD layers may be formed in the pMOS region and the nMOS region, respectively, as in the first embodiment. The LDD formation method is the same as that of the first embodiment, for example.

Next, as shown in FIGS. 16A and 16B, at least one of the S / D layers 35 and 36 is partially etched by photolithography and etching techniques to form the polysilicon film 53 on the bottom surface. An opening h1 is formed as a part. Next, as shown in FIGS. 17A and 17B, an interlayer insulating film 61 is formed on the SOI substrate 10 ′ so as to fill the opening. The interlayer insulating film 61 is, for example, a SiO ₂ film. Then, the surface of the interlayer insulating film 61 is planarized by, for example, CMP. Next, the interlayer insulating film 61 is partially etched to form a first contact hole (not shown) having the gate electrodes 33 and 34 as bottom surfaces, and a second contact having the S / D layers 35 and 36 as bottom surfaces. A contact hole (not shown) and a third contact hole H1 having the polysilicon film 53 as a bottom surface are formed. Thereafter, an Al wiring or a plug electrode or the like is formed inside the contact hole H1 or the like. As a result, the polysilicon film 53 can be drawn on the interlayer insulating film 61, and the potential of the polysilicon film 53 can be set to a desired value via the Al wiring or the plug electrode.

As described above, according to the second embodiment of the present invention, similarly to the first embodiment, a strained SOI structure having a high carrier mobility can be formed only at a necessary place on the Si substrate 1 and is expensive. Since it is not necessary to use an SOI wafer, the manufacturing cost of the semiconductor device can be reduced.
Further, when forming the strained SOI structure, for example, it is not necessary to form a thick SiGe layer or perform a high-temperature oxidation process, so that the generation of crystal defects in the Si layer 5 can be suppressed. Further, the polysilicon film 53 can be used as, for example, a back gate electrode. In this case, the threshold voltages of the MOS transistors 60 and 70 can be controlled by the back gate bias.
In the second embodiment, the SiO ₂ film 51 corresponds to the “insulating film” or “first insulating film” of the present invention, and the combination of the SiO ₂ film 21 and the SiO ₂ film 55 is the “second insulating film” of the present invention. Corresponds to "membrane". The polysilicon film 53 corresponds to the “conductive film” of the present invention. Other correspondences are the same as those in the first embodiment.

(3) Others In the first and second embodiments described above, the Si layer 5 is distorted or increased in the cavity 25 forming process and the cavity 25 filling process. explained. However, the stress characteristics of the surface insulating films (for example, Si ₃ N ₄ films 9 and 13) may vary depending on the thermal history of the process.
FIG. 19 is a diagram illustrating an example of fluctuations in stress characteristics of the Si ₃ N ₄ film. The horizontal axis of FIG. 19 shows the manufacturing process of the semiconductor device. Further, the vertical axis of FIG. 19 shows the stress characteristics of the Si ₃ N ₄ film. On the vertical axis, the closer to (+), the greater the compressive stress, and the closer to (−), the greater the tensile stress.

As shown in FIG. 19, when the Si ₃ N ₄ film is formed at 450 ° C., for example, even if the stress immediately after the film formation is a compressive stress, the compressive stress is increased by performing a heat treatment at 1000 ° C. Or change from compressive stress to tensile stress. Further, even if the stress immediately after film formation is zero (0), a heat treatment at 1000 ° C. may cause a compressive stress or a tensile stress. Such tendency of the stress characteristic varies depending on the type of surface insulating film exemplified by the Si ₃ N ₄ film and the film quality. Therefore, in the present invention, it is preferable to conduct experiments or simulations at the stage of designing or prototyping a semiconductor device and to grasp in advance the relationship between the thermal history and stress characteristics for each surface insulating film.

In the first and second embodiments described above, the stress characteristics may be adjusted by using the fluctuation of the stress characteristics due to the thermal history. That is, the stress characteristics of the surface insulating film may be adjusted not in the film forming process but in a process with subsequent heat (but before the cavity filling process). For example, in the first and second embodiments described above, a heat treatment step is provided between the step of forming the cavity portion 25 and the step of filling the cavity portion 25, and in this heat treatment step, the stress of the Si ₃ N ₄ films 9 and 13 is provided. The characteristics may be adjusted to the target stress characteristics. With such a method, the degree of freedom of film forming conditions for the Si ₃ N ₄ film can be increased, and the controllability of the stress characteristics can be improved.

In the first and second embodiments, the case where the surface insulating film having compressive stress or tensile stress is formed on the Si layer 5 has been described. However, in the present invention, in addition to this, the SiO ₂ film 27 (or the SiO ₂ film 51 and the polysilicon film 53) having compressive stress or tensile stress may be formed in the cavity 25. For example, to form an SiO ₂ film 27 having a compressive stress in the cavity 25 of the pMOS region, a SiO ₂ film 27 having a tensile stress in the cavity 25 in the nMOS region. When such a method is used, stress can be transferred (that is, a load is applied) to the second semiconductor layer from both the upper side and the lower side, so that each region has high mobility. A strained SOI structure can be realized, and a high-performance CMOS semiconductor device can be provided.

FIG. 3 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 1). FIG. 6 is a diagram (No. 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 3A and 3B are diagrams illustrating the method for manufacturing a semiconductor device according to the first embodiment (No. 3). 4A and 4B are diagrams illustrating the method for fabricating a semiconductor device according to the first embodiment (No. 4). FIG. 5 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 5). 6A and 6B are diagrams illustrating the method for manufacturing a semiconductor device according to the first embodiment (No. 6). FIG. 7 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 7). FIG. 8 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 8). FIG. 9 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 9). FIG. 10 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 10). FIG. 11 is a view (No. 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 12 is a view (No. 12) illustrating the method for manufacturing the semiconductor device according to the first embodiment; The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment (the 1). FIG. 6 is a view (No. 2) showing the method for manufacturing a semiconductor device according to the second embodiment. FIG. 9 is a diagram (No. 3) for illustrating a method for manufacturing a semiconductor device according to the second embodiment. FIG. 8 is a diagram (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 6 is a diagram (No. 5) for explaining a method for manufacturing a semiconductor device according to the second embodiment; The figure which shows typically the relationship between stress and mobility. It illustrates an example of a variation of the stress characteristics of the Si ₃ N ₄ film. The figure which shows typically the relationship between stress and a load.

Explanation of symbols

1 Si substrate, 3 SiGe layer, 5 Si layer, 7, 13, 27, 51, 55 SiO ₂ film, 9 (with compressive stress) Si ₃ N ₄ film, 10, 10 ′ SOI substrate, 13 (with tensile stress Si ₃ N ₄ film, 21 SiO ₂ film (support), 31 gate insulating film, 33, 34 gate electrode, 35 p-type S / D layer, 36 n-type S / D layer, 53 polysilicon film , 60 pMOS transistor, 61 interlayer insulating film, 70 nMOS transistor, h support hole, h1 opening, H groove, H1 contact hole

Claims (7)

Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer on the first semiconductor layer;
Forming a surface insulating film on the second semiconductor layer for causing strain in the second semiconductor layer;
Etching the surface insulating film, the second semiconductor layer and the first semiconductor layer to form a first groove penetrating the surface insulating film, the second semiconductor layer and the first semiconductor layer;
Forming a support in the first groove;
Etching the surface insulating film and the second semiconductor layer to form a second groove exposing the first semiconductor layer;
Etching the first semiconductor layer through the second groove to form a cavity between the second semiconductor layer and the semiconductor substrate;
Applying the force of the surface insulating film to the second semiconductor layer;
Forming an insulating film in the cavity. A method for manufacturing a semiconductor device, comprising: Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer on the first semiconductor layer;
Forming a surface insulating film on the second semiconductor layer for causing strain in the second semiconductor layer;
Etching the surface insulating film, the second semiconductor layer and the first semiconductor layer to form a first groove penetrating the surface insulating film, the second semiconductor layer and the first semiconductor layer;
Forming a support in the first groove;
Etching the surface insulating film and the second semiconductor layer to form a second groove exposing the first semiconductor layer;
Etching the first semiconductor layer through the second groove to form a cavity between the second semiconductor layer and the semiconductor substrate;
Applying the force of the surface insulating film to the second semiconductor layer;
Forming an insulating film on the upper surface of the semiconductor substrate facing the inside of the cavity and the lower surface of the second semiconductor layer while leaving the cavity,
And a step of forming a conductive film in the cavity where the insulating film is formed.   3. The semiconductor device according to claim 1, wherein the step of forming the hollow portion and the step of applying the force of the surface insulating film to the second semiconductor layer are performed in parallel. Production method. After the step of forming the cavity,
3. The method according to claim 1, further comprising a step of applying a heat treatment to the surface insulating film to change a force of the surface insulating film and causing the changed force to act on the second semiconductor layer. The manufacturing method of the semiconductor device of description. A region where a pMOS transistor is formed on the semiconductor substrate and a region where an nMOS transistor is formed;
The step of forming the surface insulating film includes
Forming a first surface insulating film having compressive stress on the second semiconductor layer in a region where the pMOS transistor is formed;
And forming a second surface insulating film having a tensile stress on the second semiconductor layer in a region where the nMOS transistor is to be formed. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. Removing the surface insulating film from on the second semiconductor layer;
Forming a gate electrode through the gate insulating film on the surface insulating film from which the surface insulating film has been removed;
The semiconductor device according to claim 1, further comprising a step of introducing an impurity into the second semiconductor layer on both sides of the gate electrode to form a source or a drain. Manufacturing method. A semiconductor substrate, a semiconductor layer formed on the semiconductor substrate via a first insulating film,
a second insulating film provided on the semiconductor substrate so as to surround the semiconductor layer in the region where the pMOS transistor is formed and the semiconductor layer in the region where the nMOS transistor is formed in a plan view, respectively. ,
The semiconductor layer in the region where the pMOS transistor is formed has a compressive strain;
The semiconductor device, wherein the semiconductor layer in a region where the nMOS transistor is formed has tensile strain.

Images