JP2009152392A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of preventing a thin portion of an oxide film from being generated at the edge of an active region when a surface layer portion of the active region is thermally oxidized.
An active region is defined by forming, on a surface layer portion of a semiconductor substrate, an element isolation insulating film protruding upward from the surface of the semiconductor substrate. The oxidation rate of the surface layer portion of the semiconductor substrate is reduced to the surface layer portion of the semiconductor substrate under the condition that a part of the surface of the active region that is in contact with the element isolation insulating film is behind the protruding portion of the element isolation insulating film. The element to be made is implanted from an oblique direction. After the implantation of this element, the surface of the active region is thermally oxidized to form a first oxide film.
[Selection] Figure 3-3

Description

  The present invention relates to a method for manufacturing a semiconductor device having an insulated gate structure, and a semiconductor device.

  Inside a semiconductor device in which a semiconductor integrated circuit is formed, a shallow trench isolation (STI) method is used for electrical isolation between elements. When the STI method is used, a fine and deep element isolation region can be formed as compared with the case where the silicon local oxidation (LOCOS) method is used.

  After forming an element isolation insulating film by the STI method, when an oxide film is formed on the surface of the semiconductor substrate, wet etching, etc. are repeated, a step is generated at the boundary between the element isolation insulating film embedded in the trench and the semiconductor substrate. . When forming a MOS transistor in the active region, the gate insulating film in the stepped portion tends to be thinner than the target thickness. The portion where the gate insulating film is thin acts as a parasitic transistor having a low threshold voltage. In addition, the dielectric breakdown resistance of the gate insulating film is reduced.

  Patent Document 1 below discloses a method for preventing the gate insulating film in the stepped portion from becoming thin. In this method, after adding nitrogen to the flat portion of the semiconductor substrate, the surface layer portion is thermally oxidized. In the region where nitrogen is added, the thermal oxidation rate decreases. Since the side surface of the step portion to which nitrogen is not added has a high thermal oxidation rate, a thick oxide film is formed on the side surface as compared with the oxide film on the flat surface. Thereby, it is possible to prevent the gate insulating film from being thinned at the stepped portion.

JP 2000-223562 A

  When the method disclosed in Patent Document 1 is applied, it is possible to prevent the thickness of the gate insulating film formed on the side surface of the step portion generated at the edge of the active region from becoming thinner than the target value. However, a ridge (corner portion) is formed at the boundary between the side surface of the stepped portion and the flat surface at an angle of approximately 90 °. Since nitrogen is introduced in the vicinity of this ridge, the thermal oxidation rate is relatively slow. According to the experiment by the inventors of the present application, it has been found that a region where the gate insulating film becomes thin is generated along this ridge.

  An object of the present invention is to provide a method of manufacturing a semiconductor device and a semiconductor device capable of preventing a thin portion of an oxide film from being generated at the edge of the active region when the surface layer portion of the active region is thermally oxidized. That is.

The manufacturing method of this semiconductor device is as follows:
Defining an active region on the surface layer portion of the semiconductor substrate by forming an element isolation insulating film protruding above the surface of the semiconductor substrate;
Of the surface of the active region, a portion of the surface of the semiconductor substrate that is in contact with the element isolation insulating film is located on the surface layer of the semiconductor substrate under the condition that it is behind the protrusion of the element isolation insulating film. Injecting an element that reduces the oxidation rate of the material from an oblique direction;
A step of thermally oxidizing the surface of the active region after the implantation of the element to form a first oxide film.

This semiconductor device
An element isolation insulating film that is formed in a surface layer portion of a semiconductor substrate and defines an active region;
A gate electrode disposed on the semiconductor substrate so as to intersect the active region;
In the active region, the thickness of a portion that is disposed between the gate electrode and the semiconductor substrate and includes silicon and oxygen and is in contact with the element isolation insulating film is larger than the thickness of the inner portion. A gate insulating film including a thick oxide film,
The oxide film constituting the gate insulating film contains an element that decreases the oxidation rate of the surface layer portion of the semiconductor substrate at least in a relatively thin portion, and does not contain the element in a relatively thick portion. Alternatively, the element is contained so as to have a concentration lower than the concentration of the element in a relatively thin portion.

Other semiconductor devices
An element isolation insulating film that is formed in a surface layer portion of a semiconductor substrate and defines an active region;
A gate electrode disposed on the semiconductor substrate so as to intersect the active region;
In the active region, having a gate insulating film disposed between the gate electrode and the semiconductor substrate,
An interface between the gate insulating film and the semiconductor substrate is lower in a part of the region in contact with the element isolation insulating film than in an inner region.

  The element concentration in the shaded region when the element is implanted from an oblique direction is lower than the element concentration in the central portion of the active region. For this reason, oxidation proceeds rapidly and a relatively thick oxide film is formed. As a result, a phenomenon in which the oxide film is locally thinned in the vicinity of the edge of the active region can be avoided. The semiconductor device can be manufactured using this method.

  FIG. 1 is a plan view of a semiconductor device according to the first embodiment. An element isolation insulating film 11 is formed on the surface layer portion of the semiconductor substrate. An active region 12 surrounded by the element isolation insulating film 11 is defined. The gate electrode 50 is disposed so as to intersect the active region 12. A source region 51 is disposed on one side of the gate electrode 50 in the active region 12, and a drain region 52 is disposed on the other region. Conductive plugs 65 and 66 are disposed in the source region 51 and the drain region 52, respectively.

  2A and 2B are cross-sectional views taken along one-dot chain lines 2A-2A and 2B-2B in FIG. 1, respectively.

  An element isolation insulating film 11 is formed on the surface layer portion of the semiconductor substrate 10 made of silicon by the STI method. A well 15 is formed in the surface layer portion of the active region 12 surrounded by the element isolation insulating film 11. A MOS transistor 58 is formed in the active region 12. The MOS transistor 58 includes a gate insulating film 53, a gate electrode 50, a source region 51, and a drain region 52. Sidewall spacers 59 are formed on the side surfaces of the gate electrode 50. Metal silicide films 55, 56, and 57 are formed on the upper surfaces of the gate electrode 50, the source region 51, and the drain region 52, respectively.

  An interlayer insulating film 60 covers the MOS transistor 58. Conductive plugs 65 and 66 are filled in the two via holes penetrating the interlayer insulating film 60, respectively. The conductive plugs 65 and 66 are connected to the source region 51 and the drain region 52, respectively. On the interlayer insulating film 60, wirings 67 and 68 are formed. The wirings 67 and 68 are connected to the conductive plugs 65 and 66, respectively.

As shown in FIG. 2A, the gate electrode 50 extends from the element isolation insulating film 11 in contact with one edge of the active region 12 to the element isolation insulating film 11 in contact with the opposite edge. A gate insulating film 53 is disposed between the gate electrode 50 and the semiconductor substrate 10 in the active region 12. The gate insulating film 53 is made of, for example, silicon oxide (SiO ₂ ), and the thickness of the portion 53B in contact with the element isolation insulating film 11 is thicker than the thickness of the inner portion 53A.

  Next, with reference to FIGS. 3A to 3N, description will be made on a semiconductor device manufacturing method according to the first embodiment. 3A to 3N correspond to a cross section taken along one-dot chain line 2A-2A in FIG.

As shown in FIG. 3A, a pad oxide film 30 having a thickness of 10 nm is formed by thermally oxidizing the surface of the substrate 10 made of silicon. A mask film 31 made of SiN is formed on the pad oxide film 30. The mask film 31 can be formed by, for example, chemical vapor deposition (CVD) using disilane (Si ₂ H ₆ ) and ammonia (NH ₃ ) as source gases. The thickness of the mask film 31 is about 50 nm to 100 nm. Note that SiN, SiO ₂ , SiON, or the like may be used as the material of the mask film 31, or the mask film 31 may have a laminated structure including films made of these materials.

  As shown in FIG. 3B, an opening 31 A is formed in the mask film 31. The opening 31A matches the planar shape of the element isolation insulating film 11 shown in FIG.

As shown in FIG. 3C, the trench 32 is formed by anisotropically etching the pad oxide film 30 and the surface layer portion of the semiconductor substrate 10 using the mask film 31 as an etching mask. For this anisotropic etching, for example, dry etching using Cl ₂ gas can be employed. The depth of the trench 32 is, for example, 280 nm.

As shown in FIG. 3D, an embedded film 11 a made of SiO ₂ is deposited on the mask film 31. The trench 32 is completely filled with the buried film 11a. The buried film 11a can be deposited by, for example, high density plasma chemical vapor deposition (HDP-CVD) using silane (SiH ₄ ) and phosphine (PH ₃ ) as raw materials. SiN, SiO ₂ , SiON, or the like can be used as the material of the buried film 11a. Further, the embedded film 11a may have a laminated structure including films made of these materials.

  The embedded film 11a is subjected to chemical mechanical polishing (CMP) until the mask film 31 is exposed. At this time, the mask film 31 is used as a stopper. In order for the mask film 31 to function as a stopper, the mask film 31 and the buried film 11a are formed of materials having different polishing rates.

  As shown in FIG. 3E, the mask film 31 is exposed. In the trench 32, the element isolation insulating film 11 made of the material of the buried film 11a remains. Further, the surface layer portion of the mask film 31 is also thinly removed by CMP. After CMP, annealing is performed at a high temperature of about 1000 ° C., for example, to reduce the stress inherent in the element isolation insulating film 11.

  As shown in FIG. 3F, the mask film 31 and the pad oxide film 30 are removed by wet etching. For example, phosphoric acid is used for etching the mask film 31, and hydrofluoric acid is used for etching the pad oxide film 30, for example. A structure in which the surface of the semiconductor substrate 10 is exposed in the active region 12 surrounded by the element isolation insulating film 11 and the upper end of the element isolation insulating film 11 protrudes from the surface of the semiconductor substrate 10 is obtained. The height of the protruding portion 11 b is substantially equal to the total thickness of the mask film 31 after CMP and the pad oxide film 30.

  As shown in FIG. 3G, the sacrificial oxide film 35 is formed by thermally oxidizing the surface of the semiconductor substrate 10. The thickness of the sacrificial oxide film 35 is, for example, 10 nm.

  As shown in FIG. 3H, the well 15 is formed by implanting impurities into the surface layer portion of the active region 12 through the sacrificial oxide film 35.

  As shown in FIG. 3I, nitrogen ions are implanted into the surface layer portion of the semiconductor substrate 10 from an oblique direction through the sacrificial oxide film 35. FIG. 3I shows a case where nitrogen ions are implanted from the upper left to the lower right. That is, the ion beam is parallel to a straight line in which the normal line of the substrate is inclined in one direction in which the gate electrode 50 shown in FIG. 1 extends. At this time, in FIG. 3I, a part of the region 19 in contact with the left element isolation insulating film 11 (that is, the part on which the gate electrode 50 rides) on the surface of the semiconductor substrate 10 is Become a shade. Nitrogen is not implanted into the shaded area 19. Nitrogen is implanted into the regions that are not shaded, and nitrogen doped regions 18 are formed.

  As shown in FIG. 3J, the ion beam is tilted to the opposite side, and a second nitrogen ion implantation is performed. At this time, a part of the region in contact with the element isolation insulating film 11 on the right side of the drawing is behind the protruding portion 11b.

  By injecting nitrogen ions twice while changing the tilt direction of the ion beam, a low nitrogen concentration region 18B having a relatively low nitrogen concentration is formed in a part of the region in contact with the element isolation insulating film 11, thereby In the inner portion, a high nitrogen concentration region 18A having a relatively high nitrogen concentration is formed.

Further, the ion beam is tilted in the direction orthogonal to the extending direction of the gate electrode 50 shown in FIG. 1, and nitrogen ions are implanted twice. That is, nitrogen ions are implanted a total of four times from the oblique direction. Nitrogen ions are introduced into the nitrogen low concentration region 18B by three implantations, and nitrogen ions are introduced into the nitrogen high concentration region 18A by four implantations. The acceleration energy and the dose amount of the four nitrogen ion implantations are all equal. For this reason, the nitrogen concentration in the low nitrogen concentration region 18B is 75% of the nitrogen concentration in the high nitrogen concentration region 18A. The implantation conditions are, for example, such that the total dose of the high nitrogen concentration region 18A is 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² . The depth of implantation and the incident angle of the ion beam will be described in detail later.

  Further, after performing channel implantation for threshold control, the sacrificial oxide film 35 is removed.

As shown in FIG. 3K, the high nitrogen concentration region 18A and the low nitrogen concentration region 18B on the substrate surface are exposed. Since channel implantation is performed under optimum conditions for each transistor, the resist pattern formation and stripping steps are repeated a plurality of times. The element isolation insulating film 11 made of SiO ₂ formed by CVD has a higher etching rate than the sacrificial oxide film 35 formed by thermal oxidation. When the resist film is peeled off, the exposed surface of the element isolation insulating film 11 is etched. Further, over-etching is performed when the sacrificial oxide film 35 is removed. When the height of the protruding portion 11b, the resist film peeling condition, the overetching condition, and the like are adjusted, the height of the surface of the semiconductor substrate 10 and the upper surface of the element isolation insulating film 11 is reduced after the sacrificial oxide film 35 is removed. It's aligned.

  FIG. 3L shows a cross-sectional view of the boundary portion between the element isolation insulating film 11 and the active region 12. In some cases, a recess 20 formed by etching the surface layer portion of the element isolation insulating film 11 may be generated at a boundary portion between the element isolation insulating film 11 and the active region 12. On the side surface of the recess 20, the surface layer portion of the semiconductor substrate 10 is exposed. For this reason, the corner | angular part 22 which the surface of the semiconductor substrate 10 and the surface exposed to the side surface of the recessed part 20 cross | intersects generate | occur | produces. The crossing angle between them is approximately 90 °.

As shown in FIGS. 3M and 3N, the surface layer portion of the semiconductor substrate 10 is thermally oxidized to form a gate insulating film 53 made of SiO ₂ . As the concentration of nitrogen introduced into silicon increases, the oxidation rate decreases. For this reason, the oxidation rate of the high nitrogen concentration region 18A is slower than the oxidation rate of the low nitrogen concentration region 18B. Thereby, the gate insulating film 53B formed in the low nitrogen concentration region 18B is thicker than the gate insulating film 53A formed in the high nitrogen concentration region 18A. The nitrogen concentration of the relatively thin gate insulating film 53A is higher than the nitrogen concentration of the relatively thick gate insulating film 53B.

  The corner 22 where the upper surface of the semiconductor substrate 10 and the surface exposed at the side surface of the recess 20 intersect is located in the low nitrogen concentration region 18B. For this reason, the gate insulating film 53B formed in the vicinity of the corner portion 22 is also thicker than the gate insulating film 53A formed in the high nitrogen concentration region 18A.

  Thereafter, the MOS transistor 58 shown in FIGS. 2A and 2B is fabricated by a known method. The process until the MOS transistor 58 is completed will be briefly described below.

  A polycrystalline silicon film is formed on the gate insulating film 53 and the element isolation insulating film 11. The polycrystalline silicon film and the gate insulating film 53 are patterned into the shape of the gate electrode 50 shown in FIG. Using the gate electrode 50 as a mask, ion implantation is performed to form source and drain extension portions. Sidewall spacers 59 are formed on the side surfaces of the gate electrode 50. Using the gate electrode 50 and the sidewall spacer 59 as a mask, ion implantation for forming deep source and drain regions is performed. Metal silicide films 55, 56, and 57 are formed on the surfaces of the gate electrode 50, the source region 51, and the drain 52 using a self-aligned silicide (salicide) process, respectively.

  Thereafter, an interlayer insulating film 60 is formed on the entire surface of the substrate. Via holes penetrating the interlayer insulating film 60 are formed above the source region 51 and the drain region 52, respectively. The via holes are filled with conductive plugs 65 and 66, respectively. Wirings 67 and 68 are formed on the interlayer insulating film 60.

  FIG. 5 shows a cross-sectional view of the vicinity of the boundary between the active region 12 and the element isolation insulating film 11 when the gate insulating film 53 is formed without introducing nitrogen into the surface layer portion of the active region. Since nitrogen is not introduced into the surface layer portion, the oxidation rate of the flat region in the active region 12 is uniform. It has been experimentally confirmed that when the surface layer portion of the active region 12 is thermally oxidized in this state, a thin portion of the gate insulating film 53 is generated in the vicinity of the corner portion 22. A parasitic transistor having a relatively low threshold voltage is formed in the thin portion. Furthermore, due to the concentration of the electric field, the dielectric breakdown resistance of the gate insulating film is lowered.

  In the first embodiment, since the oxidation rate in the vicinity of the corner portion 22 is faster than the oxidation rate in the central portion of the active region 12, the gate insulating film 53 has a portion with a smaller film thickness than the central portion. Does not occur. As a result, it is possible to prevent formation of an undesirable parasitic transistor and a decrease in dielectric breakdown resistance of the gate insulating film.

In the first embodiment, a single-layer SiO ₂ film is used as the gate insulating film 53, but a laminated structure of a SiO ₂ film and a film made of another insulating material may be used. For example, the other insulating material includes an oxide or oxynitride of one or more metals selected from the group consisting of Hf, Ga, Al, La, Zr, Y, Bi, Ba, Ru, and Cu. It is done. When the gate insulating film 53 has a laminated structure, another insulating film may be deposited by CVD on the SiO ₂ film formed by thermal oxidation. In this case, by introducing nitrogen by the method according to the first embodiment, it is possible to prevent the lowermost SiO ₂ film of the gate insulating film having a laminated structure from becoming thin at the edge of the active region 12. Can do.

Further, a two-layer structure of a SiO ₂ film and a SiON film may be formed by nitriding the surface layer portion of the SiO ₂ film formed by thermal oxidation. For the nitriding treatment, for example, plasma nitriding using plasma of N ₂ gas or gas nitriding using NH ₃ gas or N ₂ O gas can be employed. Further, plasma nitriding and gas nitriding may be combined.

When the two-layer structure of the SiO ₂ film and the SiON film is adopted, the two layers are considered as “a gate insulating film containing silicon and oxygen”. This gate insulating film has a film thickness distribution in which the thickness of a part in contact with the element isolation insulating film is thicker than the inner part thereof, similarly to the gate insulating film composed of a single layer of SiO ₂ .

  In the first embodiment, the nitrogen ions shown in FIGS. 3I and 3J were implanted from four directions. It is possible to perform from two orientations where shadowing is caused by the element isolation insulating film 11 overlapping the gate electrode 50 shown in FIG. 1, and to omit nitrogen ion implantation from the orientation orthogonal thereto. When nitrogen ions are implanted only from two directions, the nitrogen concentration of the low nitrogen concentration region 18B is 50% of the high nitrogen concentration region 18A.

  If the width of the nitrogen grade region 18B shown in FIG. 3L is too narrow, the vicinity of the edge of the nitrogen altitude region 18A is affected by the corner portion 18B due to the corner portion 22, and an oxide film is formed in that portion. May be thinner than the thickness of the oxide film formed in the central portion of the active region 12. In order to prevent the formation of an oxide film thinner than the thickness of the oxide film formed in the central portion of the active region 12, the width of the nitrogen low concentration region 18B is preferably set to 25 nm or more. The incident angle of the ion beam at the time of oblique implantation of nitrogen ions can be determined from the height of the protruding portion 11b of the element isolation insulating film 11 and the desired width of the nitrogen low concentration region 18B.

  If the width of the low nitrogen concentration region 18B becomes too large, the effective gate width of the MOS transistor becomes narrow, and the electrical characteristics of the transistor will not be ignored. In order not to significantly affect the characteristics of the MOS transistor, it is preferable that the dimension of the high nitrogen concentration region 18A in the gate width direction is 95% or more of the dimension of the active region 12.

  Since the high nitrogen concentration region 18A and the low nitrogen concentration region 18B formed in the steps shown in FIGS. 3I and 3J are too thin, the thermal oxidation step shown in FIG. As this progresses, the difference in thickness of the oxide film between the central portion and the peripheral portion of the active region 12 becomes small. Therefore, a sufficient effect for preventing the gate insulating film 53 formed on the edge of the active region 12 from being thinned cannot be obtained. In order to obtain a sufficient effect, the thicknesses of the high nitrogen concentration region 18A and the low nitrogen concentration region 18B are set so that the gate insulating film 53 formed by thermal oxidation does not reach a position deeper than the bottom surface of the high nitrogen concentration region 18A. It is preferable to set the length.

  In the first embodiment, nitrogen is used as an impurity for slowing down the oxidation rate of silicon. However, other impurities having an action of slowing down the oxidation rate of silicon may be used instead of nitrogen.

  Next, with reference to FIGS. 4A to 4J, a method for fabricating a semiconductor device according to the second embodiment will be described.

  The process up to the structure shown in FIG. 4A is the same as the process up to the structure shown in FIG. 3E in the first embodiment.

  As shown in FIG. 4B, the mask film 31 is removed and the underlying pad oxide film 30 is exposed. In the first embodiment, the pad oxide film 30 is also removed at this stage, but in the second embodiment, the pad oxide film 30 is left.

  As shown in FIG. 4C, nitrogen ions are obliquely implanted through the pad oxide film 30 to form the nitrogen doped region 18. A part of the region 19 in contact with one element isolation insulating film 11 is behind the protrusion 11 b of the element isolation insulating film 11.

  As shown in FIG. 4D, nitrogen ions are obliquely implanted through the pad oxide film 30 from the opposite direction. Further, nitrogen ions are obliquely implanted from two directions orthogonal to the extending direction of the gate electrode 50 shown in FIG. Thereby, the nitrogen high concentration region 18A and the nitrogen low concentration region 18B are formed as in the case shown in FIG. 3J. Thereafter, the pad oxide film 30 is removed.

As shown in FIG. 4E, the surface layer portion of the semiconductor substrate 10 is thermally oxidized to form a sacrificial oxide film 35A made of SiO ₂ . Since the oxidation rate of the low nitrogen concentration region 18B is higher than the oxidation rate of the high nitrogen concentration region 18A, the sacrificial oxide film 35A in a part of the region in contact with the element isolation insulating film 11 is thicker than the sacrificial oxide film 35A in the central portion. Become. The thickness of the sacrificial oxide film 35A is, for example, about 10 nm in the central portion of the active region 12.

  As shown in FIG. 4F, the well 15 is formed by implanting impurities into the surface layer portion of the semiconductor substrate 10 through the sacrificial oxide film 35A. Further, channel injection for adjusting the threshold voltage is performed. Thereafter, the sacrificial oxide film 35A is removed.

  As shown in FIGS. 4G and 4H, the surface of the semiconductor substrate 10 is exposed. As in the case of the first embodiment, the upper surface of the element isolation insulating film 11 is substantially the same height as the upper surface of the semiconductor substrate 10. The upper surface 33 of the region where the relatively thick sacrificial oxide film 35A has been formed is lower than the upper surfaces of the other regions. That is, the upper surface 33 of a part of the region in contact with the element isolation insulating film 11 is lower than the upper surface of the region inside it.

  As shown in FIG. 4H, the step 34 is formed by etching the edge of the upper surface of the element isolation insulating film 11 as in the case shown in FIG. In the example shown in FIG. 5, the corner 22 is formed by the surface of the semiconductor substrate exposed on the side surface of the recess 20 and the upper surface of the semiconductor substrate 10 intersecting at approximately 90 °. In the second embodiment, the upper surface 33 of the semiconductor substrate 11 in the region in contact with the element isolation insulating film 11 is lowered. When the bottom end of the step 34 formed in the element isolation insulating film 31 and the height of the lower upper surface 33 are matched, no corner is formed at the boundary between the active region 12 and the element isolation insulating film 11. Moreover, the area | region which connects the lower upper surface 33 and the flat surface inside it becomes a gentle slope.

  The low nitrogen concentration region 18B remains in the region where the lower upper surface 33 is formed, and the high nitrogen concentration region 18A remains in the region inside it. When the sacrificial oxide film 35A reaches the bottom surface of the low nitrogen concentration region 18B, the low nitrogen concentration region 18B does not remain, and the surface of the semiconductor substrate 11 into which nitrogen is not introduced is present on the low top surface 33. Exposed. When the sacrificial oxide film 35A reaches the bottom of the high nitrogen concentration region 18A, the high nitrogen concentration region 18A does not remain, and the surface of the semiconductor substrate 10 into which nitrogen is not introduced is entirely present on the active region 12. Exposed.

As shown in FIGS. 4I and 4J, the surface insulating layer 53 of the semiconductor substrate 10 is thermally oxidized to form a gate insulating film 53 made of SiO ₂ . Since the surface layer portion of the lower upper surface 33 has an oxidation rate faster than that of the high nitrogen concentration region 18A, the gate insulating film 53 formed on the lower upper surface 33 is relatively thick. Since the lower upper surface 33 and the inner upper surface are connected by a gentle slope, the phenomenon that the gate insulating film 53 is locally thinned does not occur in this portion. Subsequent steps are the same as those in the first embodiment.

  Since the upper surface of the edge of the active region 12 is low, the step on the active region 12 side formed at the boundary between the active region 12 and the element isolation insulating film 11 is compared with the step of the structure shown in FIG. Low. If the thickness of the gate insulating film 53 at the edge of the active region 12 is equal to or higher than the height of the step, the phenomenon that the gate insulating film 53 is locally thinned does not occur.

  In the step of forming the sacrificial oxide film 35A shown in FIG. 4E, when the sacrificial oxide film 35 reaches the bottom surface of the high nitrogen concentration region 18A and the high nitrogen concentration region 18A does not remain after the sacrificial oxide film 35A is removed. The oxidation rate is almost equal over the entire surface in the active region 12.

  FIG. 4K shows a cross-sectional view when the high nitrogen concentration region 18A does not remain. A gate insulating film 53 having a substantially uniform thickness is formed on the entire surface of the active region 12. Also in this case, since the lower upper surface 30 and the inner upper surface are connected with a gentle slope, the phenomenon that the gate insulating film 53 becomes locally thin does not occur.

  Even in the second embodiment, a region where the gate insulating film 53 is locally thinned does not occur. For this reason, it is possible to prevent formation of a parasitic transistor and a reduction in dielectric breakdown resistance of the gate insulating film.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

  The following additional notes are further disclosed with respect to the embodiment including the first and second examples.

(Appendix 1)
Defining an active region on the surface layer portion of the semiconductor substrate by forming an element isolation insulating film protruding above the surface of the semiconductor substrate;
Of the surface of the active region, a portion of the surface of the semiconductor substrate that is in contact with the element isolation insulating film is located on the surface layer of the semiconductor substrate under the condition that it is behind the protrusion of the element isolation insulating film. Injecting an element that reduces the oxidation rate of the material from an oblique direction;
Forming a first oxide film by thermally oxidizing the surface of the active region after implanting the element.

(Appendix 2)
The method for manufacturing a semiconductor device according to appendix 1, wherein the element is nitrogen.

(Appendix 3)
The method for manufacturing a semiconductor device according to appendix 1 or 2, wherein in the step of implanting the element from an oblique direction, the implantation is performed under a condition that a width of a region behind the protruding portion of the element isolation insulating film is 25 nm or more.

(Appendix 4)
The method for manufacturing a semiconductor device according to any one of appendices 1 to 3, further comprising a step of forming a gate electrode on the first oxide film so as to intersect the active region.

(Appendix 5)
After forming the first oxide film,
Removing the first oxide film;
Forming a second oxide film by thermally oxidizing a surface layer portion of the semiconductor substrate in a region where the first oxide film has been removed;
4. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a gate electrode on the second oxide film so as to cross the active region. 5.

(Appendix 6)
6. The method for manufacturing a semiconductor device according to any one of appendices 1 to 5, wherein at least a surface layer portion of the semiconductor substrate is formed of silicon.

(Appendix 7)
An element isolation insulating film that is formed in a surface layer portion of a semiconductor substrate and defines an active region;
A gate electrode disposed on the semiconductor substrate so as to intersect the active region;
In the active region, a portion of the active region, which is disposed between the gate electrode and the semiconductor substrate and includes silicon and oxygen and is in contact with the element isolation insulating film, has a thickness greater than a thickness of an inner portion thereof. A gate insulating film including a thick oxide film,
The oxide film constituting the gate insulating film contains an element that reduces the oxidation rate of the surface layer portion of the semiconductor substrate at least in a relatively thin portion, and does not contain the element in a relatively thick portion. Or a semiconductor device containing the element so as to have a concentration lower than the concentration of the element in a relatively thin portion.

(Appendix 8)
The semiconductor device according to appendix 7, wherein an upper surface of a relatively thick portion of the oxide film constituting the gate insulating film is lower than an upper surface of a relatively thin portion.

(Appendix 9)
The semiconductor device according to appendix 7 or 8, wherein the element is nitrogen.

(Appendix 10)
An element isolation insulating film that is formed in a surface layer portion of a semiconductor substrate and defines an active region;
A gate electrode disposed on the semiconductor substrate so as to intersect the active region;
In the active region, having a gate insulating film disposed between the gate electrode and the semiconductor substrate,
The semiconductor device in which an interface between the gate insulating film and the semiconductor substrate is lower than a region inside the partial region in contact with the element isolation insulating film.

1 is a plan view of a semiconductor device according to a first embodiment. (2A) and (2B) are cross-sectional views of the semiconductor device according to the first embodiment. (3A) to (3D) are cross-sectional views of the semiconductor device according to the first embodiment in the course of manufacturing. (3E) to (3G) are cross-sectional views of the semiconductor device according to the first embodiment in the course of manufacturing. (3H) to (3J) are cross-sectional views of the semiconductor device according to the first embodiment in the course of manufacturing. (3K) is a cross-sectional view of the semiconductor device according to the first embodiment in the course of manufacturing, and (3L) is a cross-sectional view in the vicinity of the boundary between the active region and the element isolation insulating film. (3M) is a cross-sectional view of the semiconductor device according to the first embodiment in the course of manufacturing, and (3N) is a cross-sectional view in the vicinity of the boundary between the active region and the element isolation insulating film. (4A) to (4D) are cross-sectional views of the semiconductor device according to the second embodiment in the course of manufacturing. (4E) to (4G) are cross-sectional views of the semiconductor device according to the second embodiment in the course of manufacturing, and (4H) is a cross-sectional view in the vicinity of the boundary between the active region and the element isolation insulating film. (4I) is a cross-sectional view of the semiconductor device according to the second embodiment in the course of manufacturing, and (4J) and (4K) are cross-sectional views in the vicinity of the boundary between the active region and the element isolation insulating film. It is sectional drawing of the boundary vicinity of the active region and element isolation insulating film of the semiconductor device produced by the method by a reference example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Substrate 11 Element isolation insulating film 11a Embedded film 11b Protruding part 12 Active region 15 Well 18 Nitrogen doped region 18A Nitrogen high concentration region 18B Nitrogen low concentration region 20 Recess 22 Edge 30 Pad oxide film 31 Mask film 32 Trench 33 Low upper surface 34 Step 35, 35A Sacrificial oxide film 50 Gate electrode 51 Source region 52 Drain region 53 Gate insulating film 55, 56, 57 Metal silicide film 58 MOS transistor 59 Side wall spacer 60 Interlayer insulating film 65, 66 Conductive plugs 67, 68 Wiring

Claims (5)

Defining an active region on the surface layer portion of the semiconductor substrate by forming an element isolation insulating film protruding above the surface of the semiconductor substrate;
Of the surface of the active region, a portion of the surface of the semiconductor substrate that is in contact with the element isolation insulating film is located on the surface layer of the semiconductor substrate under the condition that it is behind the protrusion of the element isolation insulating film. Injecting an element that reduces the oxidation rate of the material from an oblique direction;
Forming a first oxide film by thermally oxidizing the surface of the active region after implanting the element.   The method for manufacturing a semiconductor device according to claim 1, wherein the element is nitrogen.   3. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of implanting the element from an oblique direction, the implantation is performed under a condition that a width of a region behind the protruding portion of the element isolation insulating film is 25 nm or more. An element isolation insulating film that is formed in a surface layer portion of a semiconductor substrate and defines an active region;
A gate electrode disposed on the semiconductor substrate so as to intersect the active region;
In the active region, a portion of the active region, which is disposed between the gate electrode and the semiconductor substrate and includes silicon and oxygen and is in contact with the element isolation insulating film, has a thickness greater than a thickness of an inner portion thereof. A gate insulating film including a thick oxide film,
The oxide film constituting the gate insulating film contains an element that decreases the oxidation rate of the surface layer portion of the semiconductor substrate at least in a relatively thin portion, and does not contain the element in a relatively thick portion. Or a semiconductor device containing the element so as to have a concentration lower than the concentration of the element in a relatively thin portion. An element isolation insulating film that is formed in a surface layer portion of a semiconductor substrate and defines an active region;
A gate electrode disposed on the semiconductor substrate so as to intersect the active region;
In the active region, having a gate insulating film disposed between the gate electrode and the semiconductor substrate,
The semiconductor device in which an interface between the gate insulating film and the semiconductor substrate is lower than a region inside the partial region in contact with the element isolation insulating film.

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