JP2009146544A - Optical disk device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To lower a possibility that an address pattern is erroneously detected as a synchronization pattern. <P>SOLUTION: An optical disk device includes a pickup (14) which reads a wobble signal from an optical disk where synchronization information constituted of a prescribed bit pattern in a prescribed position, and address information in a position deviated from the synchronization information by a prescribed position are repeatedly recorded, a pattern determination section (76) which detects a synchronization pattern from the read wobble signal, and a gate (78) which does not permit the outputting of the pattern determination section (76) when the read wobble signal is a similar pattern of the synchronization pattern. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an optical disc apparatus, and more particularly to improvement of synchronization signal detection and physical address detection in an optical disc apparatus.

  Recently, an optical disc such as a DVD (Digital Versatile Disc) has been widely used as a digital recording medium, and high reliability is desired in an optical disc apparatus for reproducing these. In such an optical disc, a storage area is provided on a spiral track, and the track information is included in the address information. In processing such as fast-forward and fast-reverse during reproduction, fine adjustment for each track is performed by appropriately tilting the objective lens with an actuator after feeding an optical pickup with a motor drive. Also in the case of track jump, it is determined whether or not the track number is a desired number when it is determined whether or not the target address has been accurately jumped.

  By the way, the DVD itself has evolved and the HD DVD standard for high-definition has been made. In the HD DVD standard, since the recording density is higher than in the DVD standard, the CN ratio of the reproduction signal tends to decrease. When extracting the synchronization signal and address information from the reproduction signal, the influence of disturbances such as noise is relatively affected. It is easy to receive. In Patent Document 1, a 1-bit input signal is shifted by a shift register, and a synchronization signal is obtained by collating with a pattern.

However, since Patent Document 1 is a 1-bit input signal, it is easily affected by disturbances such as noise. Furthermore, in the case of the HD DVD standard, the synchronization (SYNC) pattern and the physical address pattern may be similar, and for example, a physical address may be erroneously detected as synchronization, and malfunctions may frequently occur. In the circuit configuration of Patent Document 1, when there is no disturbance such as noise, a portion unique to the synchronization pattern can be properly recognized in the wobble signal at a predetermined synchronization pattern position, and synchronization indicating that synchronization is detected at the predetermined position. A signal is output. On the other hand, when a part of the address pattern at a predetermined address position collapses due to disturbance such as noise, it may be erroneously detected as synchronization. If the synchronization is erroneously detected in this way, a signal following the erroneously detected synchronization is erroneously recognized as a physical address, so that a correct physical address cannot be obtained, and the correct position on the disk is not known, resulting in a malfunction.
JP2003-187457 (paragraph 0054)

  As described above, there is a possibility that the address pattern is erroneously detected as the synchronization pattern in the synchronization detection of the conventional optical disc apparatus.

  An object of the present invention is to reduce the possibility of erroneously detecting an address pattern as a synchronization pattern.

  An optical disc apparatus according to an aspect of the present invention includes a synchronization information including a predetermined bit pattern at a predetermined position, and a motor that rotationally drives an optical disc in which address information is repeatedly recorded at a position shifted by a predetermined position from the synchronization information; Means for reading a wobble signal from the optical disk rotated by the motor; means for detecting a predetermined bit pattern from the read wobble signal; and if the read wobble signal is not a similar bit pattern of the predetermined bit pattern, the detection means And a means for permitting output of the detection result.

  A synchronization detection circuit according to another aspect of the present invention reads a wobble signal from an optical disc in which synchronization information having a predetermined bit pattern at a predetermined position and address information is repeatedly recorded at a position shifted from the synchronization information by a predetermined position. Means for detecting a predetermined bit pattern from the read wobble signal, and means for eliminating the output of the detection result of the detection means when the read wobble signal is a similar bit pattern of the predetermined bit pattern. To do.

  A synchronization detection method according to another aspect of the present invention reads a wobble signal from an optical disc in which synchronization information having a predetermined bit pattern at a predetermined position and address information is repeatedly recorded at a position shifted from the synchronization information by a predetermined position. A step of detecting a predetermined bit pattern from the read wobble signal, and a step of eliminating the output of the detection result of the detection step when the read wobble signal is a similar bit pattern of the predetermined bit pattern. To do.

  As described above, according to the present invention, it is possible to reduce the possibility of erroneous detection of an address pattern as a synchronization pattern by excluding an address pattern similar to the synchronization pattern from the target of synchronization detection.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a relationship between a wobble and a signal when a recording track is wobble-modulated as an addressing method for an optical disc recording medium. Digital data is played back from the meandering recording track (or digital data is recorded on the meandering recording track), but the recorded data is recorded at the specified position and determined. The physical address information obtained can be obtained by reading and demodulating the wobble signal of the recording track. FIG. 1 shows a bit modulation rule when information is embedded by phase-modulating a read beam 4 on a track, a detected wobble signal, and a wobble signal. Address information is recorded using the unmodulated portion (normal phase wobble: NPW) of the wobble signal as bit information “0” and the modulated portion (inverted phase wobble: IPW) as bit information “1”.

  FIG. 2 shows a physical address format of the HD DVD-R standard as an example of the phase modulation method. The wobble bit modulation data NPW (= “0”) and IPW (= “1”) shown in FIG.

  The physical address field is composed of 33 bits in total including segment information (3 bits), physical segment block address (18 bits), physical segment order (3 bits), and CRC (9 bits). The 33-bit physical address data is divided into 3 bits, distributed to each WDU (Wobble Data Unit), and embedded in the optical disk recording medium by modulation processing. Therefore, the 33 bits of physical address data are composed of 11 WDUs. Each 1 bit of the physical address data of each WDU corresponds to 4 wobbles as shown in FIG. For this reason, even if the information of all four wobbles cannot be read, the address can be reproduced if the information of one wobble is read.

  In the case of the primary segment type, the top 4 wobbles of each WDU preceding 3 bits of physical address data are configured by IPW, and the configuration is such that the top identification of each WDU is easy. Since 1 WDU is composed of 84 wobbles, 68 wobbles after embedding physical address data are defined as NPW.

  In the case of the secondary segment type, the configuration of the physical address data 3 bits is the same as that of the primary segment type, but 42 wobble NPW is arranged before the 4 wobble IPW for identifying the head of each WDU, and the physical address data 26 wobbles after embedding are different from each other in that they are defined as NPW.

  In the physical address data, one address is composed of an aggregate called WAP (Wobble Address Periodic Position) composed of 17 WDUs. Since the WAP is connected and a track wobble is completed, the period determined by the WAP becomes a period in which physical address data is embedded. In each 1 WAP, a SYNC (synchronization signal) is arranged in the first 1 WDU, a physical address is arranged in the next 11 WDU, and a non-modulation unit (Unity field) is arranged in the rear 5 WDU.

  The WDU in which the address information is embedded constitutes the address information with 3 bits, and each 1 bit corresponds to 4 wobbles. For this reason, the top four wobbles of the WDU have an IPW configuration that makes it easy to identify the head of the WDU. As a result, 68 wobbles after embedding address information of each WDU are defined as NPW. Since the entire address data is 33 bits, the required WDU is 11 units, the WAP synchronization signal SYNC is arranged in the head side WDU, and the 5 units on the back side are composed of unmodulated units (Unity field). The With this convention, information data is recorded at a location specified using physical segment address data. For this reason, accurate address data reading of the physical segment is important.

  FIG. 3 shows a physical address format of an HD DVD-RAM as another example of the phase modulation method. The wobble bit modulation data NPW (= “0”) and IPW (= “1”) shown in FIG. Physical address data includes segment information (3 bits), segment address (6 bits), zone address (5 bits), parity address (1 bit), groove track address (12 bits), and land track address (12 bits). It consists of 39 bits. The 39-bit physical address data is divided into 3 bits, distributed to each WDU (Wable Data Unit), and embedded in an optical disc recording medium by modulation processing. Therefore, the physical address data 39 bits are composed of 13 WDUs. Each bit of physical address data of each WDU is associated with 4 wobbles.

  The leading 4 wobbles of each WDU preceding 3 bits of physical address data are configured by IPW, and the configuration is such that the leading identification of each WDU is easy. Since 1 WDU is composed of 84 wobbles, 68 wobbles after embedding physical address data are defined as NPW.

  Information data is recorded on the recording track in which the physical address is embedded by such track wobble modulation. In this case, the recording data has a VFO (playback operation of 71 bytes) at the head with respect to 77376 bytes of data. A constant frequency signal for facilitating the generation of a data demodulation channel clock) is sometimes recorded, and a PA (post amble) field, a reserve field, and a buffer field for performing data block connection processing are recorded behind the total 22 bytes. The A total of 77469 bytes are recorded in 7 physical segments (9996 wobbles). With this convention, information data is recorded at a location specified using physical segment address data. For this reason, accurate address data reading of the physical segment is important.

  FIG. 4 is a diagram exemplifying a layout of physical address information for a structure in which a recording track of an optical disk recording medium is used for both land / groove. In this example, since addressing by wobble modulation is performed on a groove track, correct addressing must be configured even for recording / reproduction on a land track. Therefore, a structure called the zone method is adopted, and the optical disk is divided into a plurality of zones in the radial direction, and each zone forms segment packets with a constant recording capacity, and there are “zone numbers” and “track numbers” which are physical address information. “,“ Segment number ”are embedded by wobble modulation of the groove track. When the zone is changed, the recording capacity is optimized by changing the division angle so that the segments are formed in units with substantially the same recording density. With the configuration as shown in FIG. 4, even in the land / groove method, the address information by the groove wobble becomes the same value between adjacent tracks except for the track number, and the physical address information can be read also in the land track. Since the track number is configured so that information can be obtained for both the land and the groove by arranging the land and the groove, there is no problem.

  FIG. 5 is a diagram for explaining a configuration example of an optical disc apparatus according to an embodiment of the present invention. FIG. 6 is a diagram for explaining a configuration example of the pickup 14 of the optical disc apparatus according to the embodiment of the present invention. FIG. 7 is a diagram illustrating a configuration example of the wobble PLL unit / address detecting unit 34 of the optical disc apparatus according to the embodiment of the present invention. Here, the optical disk 11 will be described as a phase modulation optical disk capable of recording (or rewriting) user data.

  Examples of recordable / rewritable phase modulation optical disks include, for example, HD DVD-RAM, HD DVD-RW, HD DVD-R, and the like using blue laser light having a wavelength of about 405 nm, or red having a wavelength of about 650 nm. DVD + R using a system laser beam.

  On the surface of the optical disc 11, land tracks and groove tracks are formed in a spiral shape. The tracks meander in the radial direction. The optical disk 11 is rotationally driven by a spindle motor 12. The rotation speed of the spindle motor 12 is controlled by a motor control circuit 13.

  Information is recorded on and reproduced from the optical disk 11 by the pickup 14. The pickup 14 is connected to the thread motor 15 through a gear. The thread motor 15 is controlled by a thread motor driver 17 connected to the data bus 16. A permanent magnet (not shown) is provided at the fixed portion of the thread motor 15, and the pickup 14 moves in the radial direction of the optical disk 11 by exciting a drive coil (not shown).

  The pickup 14 is provided with an objective lens 18 as shown in FIG. The objective lens 18 can be moved in the focusing direction (the optical axis direction of the lens) by driving the drive coil 19 and moved in the tracking direction (the direction orthogonal to the optical axis of the lens) by driving the drive coil 20. The track jump can be performed by moving the beam spot of the laser beam.

  The modulation circuit 21 generates EFM data by performing, for example, 8-14 modulation (EFM) on user data supplied from the host device 22 via the interface circuit 23 during information recording. The laser control circuit 24 provides a write signal to the semiconductor laser diode 25 based on the EFM data supplied from the modulation circuit 21 during information recording (mark formation). The laser control circuit 24 provides a read signal smaller than the write signal to the semiconductor laser diode 25 when reading information.

  The semiconductor laser diode 25 generates laser light in accordance with the write signal supplied from the laser control circuit 24. Laser light emitted from the semiconductor laser diode 25 is irradiated onto the optical disk 11 through the collimator lens 26, the half prism 27, the optical system 28, and the objective lens 18. The reflected light from the optical disk 11 is guided to the photodetector 30 through the objective lens 18, the optical system 28, the half prism 27, and the condenser lens 29.

  The photodetector 30 is composed of four photodetection cells, and supplies output signals A, B, C, and D of each cell to the RF amplifier 31. The RF amplifier 31 supplies the tracking error signal TE corresponding to (A + D) − (B + C) to the tracking control unit 32 and supplies the focus error signal FE corresponding to (A + C) − (B + D) to the focusing control unit 33. .

  Further, the RF amplifier 31 supplies the wobble signal WB corresponding to (A + D) − (B + C) to the wobble PLL unit / address detecting unit 34 and the RF signal corresponding to (A + D) + (B + C) is the data reproducing unit 35. To supply.

  On the other hand, the output signal of the focusing control unit 33 is supplied to the driving coil 19 in the focusing direction. As a result, the laser beam is controlled to be always just focused on the recording film of the optical disc 11. Further, the tracking control unit 32 generates a track drive signal in accordance with the tracking error signal TE and supplies it to the drive coil 20 in the tracking direction.

  By performing the focusing control and the tracking control, the sum signal RF of the output signal of the light detection cell of the light detector 30 is reflected from the pits formed on the track of the optical disk 11 corresponding to the recording information. Changes are reflected. This signal is supplied to the data reproducing unit 35.

  The data reproducing unit 35 reproduces recorded data based on the reproduction clock signal from the PLL circuit 36. The data reproducing unit 35 has a function of measuring the amplitude of the signal RF, and the measured value is read by the CPU 37.

  When the objective lens 18 is controlled by the tracking control unit 32, the pickup 14 is controlled by controlling the sled motor 15 so that the objective lens 18 is at the optimum position of the optical disc 11.

  The motor control circuit 13, the laser control circuit 24, the focusing control unit 33, the tracking control unit 32, the data reproduction unit 35, the PLL circuit 36, and the like can be configured in one LSI chip as a servo control circuit.

  These circuit units are controlled by the CPU 37 via the bus 16. The CPU 37 comprehensively controls the optical disk device based on operation commands provided from the host device 22 via the interface circuit 23.

  The CPU 37 uses the RAM 38 as a work area and performs a predetermined operation according to a program recorded in the ROM 39.

  The data reproduced by the data reproduction unit 35 is subjected to error correction processing by the error correction circuit 40, and is then used for reproduction of video, sub-video, audio and the like.

  FIG. 7 shows a specific example of a circuit configuration (including a configuration for generating a physical address from a wobble signal) corresponding to the wobble PLL unit / address detection unit 34 of FIG. The wobble PLL unit / address detection unit 34 is divided into three blocks: a wobble PLL unit 51, a synchronization detection (detailed block diagram is FIG. 8) / physical address detection unit 52, and a flywheel counter 53.

  The wobble PLL unit 51 includes an A / D converter 55 to which a wobble signal is input, a phase detection unit 56 that compares the phase of the output wobble signal, hold of a previous value when the phase of the wobble signal is ± 90 ° or more, or A phase control unit 57 that performs loop compensation and the like, a D / A converter 58 to which an output of the phase control unit 57 is input, and a VCO 59 that supplies an oscillation signal having a frequency corresponding to the output to the A / D converter 55.

  The phase detection unit 56 performs integration operation in units of one wobble of a wobble signal and a reference sine wave / reference cosine wave, and a sine correlation detection value signal and a cosine correlation detection value as illustrated in FIGS. 10 and 11 to be described later. Each signal is made. The cosine correlation detection value signal is supplied to the phase control unit 57, and the sine correlation detection value signal is supplied to the phase control unit 57, the synchronization detection / physical address detection unit 52, and the flywheel counter 53.

  The phase control unit 57 uses the cosine correlation detection value signal as a phase error signal for PLL acquisition, generates a single clock that follows the phase of the input signal (wobble signal), and supplies it to the D / A converter 58. To do. In the sine correlation detection value signal, the modulation part (IPW part) is output as a “+” value (multi-value), and the non-modulation part (NPW part) is output as a “−” value (multi-value). From this multilevel signal, a synchronization pattern and an address pattern are detected.

  The synchronization detection / physical address detection unit 52 has an IPW (6 wobbles) -NPW (NPW () which is a part unique to the synchronization pattern among 84 wobble signals at a predetermined synchronization pattern position (WAP “0” in FIGS. 2 and 3). (4 wobbles) -IPW (6 wobbles) is detected, and the subsequent physical address is detected. The block includes a synchronization detection unit 62, a physical address head detection unit 64, and a physical address holding unit 66.

  Although all the circuit blocks (or at least the synchronization / address detection unit 52) in FIG. 7 can be constituted by discrete electronic components, it is desirable to make an IC (controller LSI) at the time of mass production.

  A detailed block of the synchronization detector 62 is shown in FIG. The synchronization detection unit 62 includes a shift register 72 to which a sine correlation detection value signal is supplied, a data detection / four-wave calculation unit 74 to which an output of the shift register 72 is supplied, a pattern calculation unit (edge / state level detection) 80, The pattern determination unit 76 to which the output of the data detection / four-wave operation unit 74 is supplied, and the output of the pattern determination unit 76 are supplied to generate an exclusion gate signal for eliminating a physical address pattern similar to the synchronization pattern The exclusion gate signal generation unit 78, the comparison determination unit (synchronization detection) 82 to which the output of the pattern calculation unit 80 is supplied, and the output of the comparison determination unit 82 are supplied and only when the exclusion gate signal is generated. It consists of a conducting AND gate 84. The output of the flywheel counter 53 is supplied to circuits other than the AND gate 84.

  The shift register 72, the pattern calculation unit 80, and the comparison / determination unit 82 are IPW (6) which is a portion unique to the synchronization pattern among 84 wobble signals at a predetermined synchronization pattern position (WAP “0” in FIGS. 2 and 3). This is a circuit that detects a (wobble) -NPW (4 wobble) -IPW (6 wobble) portion (unique pattern portion). First, the sine correlation detection value signal is shifted by a 20-stage shift register 72. The processing result is input to the pattern calculation unit 80, where the difference calculation of the sign change point (IPW → NPW / NPW → IPW: edge detection) of the shifted signal and the sign comparison of the signal other than the edge change point are performed. State stability (sign match) detection is performed. The comparison determination unit 82 determines that the synchronization signal is detected when the edge detection value in the pattern calculation unit 80 is greater than or equal to the threshold value and it is determined that the state matches synchronization. Output.

  FIG. 9 is an example (six patterns) of physical address patterns that are very similar to the synchronization patterns. These physical address patterns have an IPW (at least 4 wobbles) -NPW (at least 4 wobbles) -IPW (at least 4 wobbles) configuration, and each of the two wobbles surrounded by two circles in the figure is erroneously detected (for example, If the polarity is detected, the synchronization pattern (IPW (6 wobbles) −NPW (4 wobbles) −IPW (6 wobbles)) can be recognized. Therefore, by identifying and eliminating these physical address patterns at the time of synchronization detection, erroneous detection of the synchronization pattern is reduced, and reliable synchronization detection is possible.

  The exclusion gate signal generation unit 78 that excludes a physical address pattern that is easily erroneously detected as a synchronization pattern is a circuit for eliminating these six patterns of physical addresses. For the data (Dn) shifted by the shift register 72, the data detection / four-wave operation unit 74 detects the signal state of the part circled in FIG. As a detection method, in order to lower the detection error probability, two wobbles of each part of IPW and NPW are added, and the difference between the two added values is obtained. If the address pattern is correctly detected, this difference is a positive value. However, if even one of the four wobbles is detected with a fluctuation from the normal level, this difference may become a negative value. Therefore, if the difference becomes a negative value, the address pattern may be erroneously detected as a synchronization pattern. For example, in the physical address pattern P1, when (shift register “D0” data + shift register “D1” data) − (shift register “D16” data + shift register “D17” data) <0, the synchronization pattern is erroneously detected. there's a possibility that. If there is a possibility of such erroneous detection, the AND gate 84 is closed so that such a pattern is not detected as a synchronization pattern. Only when there is no possibility of erroneous detection, the exclusion gate signal generation unit 78 generates an exclusion gate signal and makes the AND gate 84 conductive (see FIGS. 10 and 11). As another detection method, detection may be performed simply by using a 4-wobble binary code of IPW and NPW.

  The principle by which the pattern determination unit 76 determines physical address patterns (FIGS. 9C to 9H) that may be erroneously detected as synchronization patterns will be described. If the level of the circled portion of each address pattern in FIGS. 9C to 9H deviates from the normal level (thick line in FIG. 9), there is a possibility that it matches the synchronization pattern. For this reason, if any of the following conditions is satisfied, the address pattern is likely to cause a false detection, so that the exclusion gate signal is not generated and the AND gate 84 is turned off.

Physical address pattern P1: (D0 + D1)-(D16 + D17)> 0
Physical address pattern P2: (D18 + D19)-(D2 + D3)> 0
Physical address pattern P3:-(D2 + D3)-(D16 + D17)> 0
Physical address pattern P4:-(D6 + D7)-(D12 + D13)> 0
Physical address pattern P5: (D8 + D9)-(D12 + D13)> 0
Physical address pattern P6: (D10 + D11)-(D6 + D7)> 0
On the other hand, when all the conditions of the six patterns are not satisfied, that is, under the “NOR” condition of the determination result of the six patterns, the exclusion gate signal is generated and the AND gate 84 is turned on.

  On the optical disk 11, the physical address is recorded by modulating the track wobble with the above configuration. When a physical address is read from the wobble of such an optical disc 11, a synchronization signal (SYNC in FIGS. 2 and 3) is detected from the wobble signal, a timing signal corresponding to the synchronization signal is generated, and the timing signal is The physical address is extracted from the address area and demodulated and acquired.

  Next, an example of detection of a synchronization signal based on the above wobble signal will be described.

  FIG. 10 shows the generation timing of the normal synchronization detection and the exclusion gate signal for eliminating the physical address pattern. 10A is data of the shift register 72, FIG. 10B is a wobble signal, FIG. 10C is a sine correlation detection value signal, FIG. 10D is a synchronization pattern detection signal (output of the comparison determination unit 82), and FIG. The gate signal for exclusion, (f), indicates synchronization detection (output of the AND gate 84). In the true synchronization pattern portion, since the synchronization pattern does not apply to all six conditions of the physical address pattern to be excluded, an exclusion gate signal (FIG. 10 (e)) is generated simultaneously with the synchronization pattern detection timing. Correct synchronization detection (FIG. 10 (f)) is performed by taking "AND" of the synchronization pattern detection signal (FIG. 10 (d)), which is an output 1-wobble width pulse, and the exclusion gate signal.

  Next, since the physical address pattern portion corresponds to the physical address patterns P1 and P5 in FIG. 9, the physical address pattern exclusion condition of (D0 + D1) − (D16 + D17)> 0, (D8 + D9) − (D12 + D13)> 0. Therefore, the exclusion gate signal is not generated and the AND gate 84 is closed. Therefore, even if the comparison / determination unit 82 generates the synchronization pattern detection signal (FIG. 10D), the physical address pattern is not detected as synchronization.

  FIG. 11 shows a timing at which a physical address pattern is excluded when a physical address pattern is erroneously detected as a synchronization pattern. 11A is data of the shift register 72, FIG. 11B is a wobble signal, FIG. 11C is a sine correlation detection value signal, FIG. 11D is a synchronization pattern detection signal (output of the comparison determination unit 82), and FIG. The gate signal for exclusion, (f), indicates synchronization detection (output of the AND gate 84). In the physical address pattern, D9 data and D13 data (dotted line portion), which are part of the physical address pattern P5 in FIG. 10, are erroneously detected for some reason.

  The pattern calculation unit 80 performs state determination and edge level determination. The state determination is performed at a portion where the signal state is stable except for two waves before and after the signal sign (plus value or minus value) changes. Speaking of the synchronization pattern (IPW (6 wobbles) -NPW (4 wobbles) -IPW (6 wobbles)), the codes of the central 4 wobbles of the IPW and the 2 wobbles of the center of the NPW match the synchronization pattern. If the four waves at the center of the IPW have a positive value and the two waves at the center of the NPW have a negative value, it can be determined as a synchronization pattern. Therefore, when D9 of the physical address pattern in FIG. 11 is a negative value and D13 is a positive value, IPW (D2 to D7) −NPW (D8 to D11) −IPW (D12 to D17), which is a pattern similar to the synchronization pattern It becomes. At this time, synchronization pattern detection state determination positions are D9 to D10 and D13 to D16. In the physical address pattern P5, the state determination conditions D9 to D10 and D13 to D16 of the synchronization pattern detection are satisfied, and thus are regarded as synchronization patterns, and the comparison determination unit 82 receives the synchronization pattern detection signal (FIG. 11 (d)). ). However, even in this case, since the exclusion condition of the physical address pattern P5: (D8 + D9) − (D12 + D13)> 0 is satisfied, the exclusion gate signal is not generated, the AND gate 84 is closed, and the synchronization pattern is erroneously detected. Is prevented. FIG. 12 is a flowchart showing the physical address detection operation. In block B12, the wobble signal is read. In block B14, the phase detection unit 56 detects the phase of the wobble signal and outputs a sine correlation detection value signal. In block B16, the sine correlation detection value signal is input to the shift register 72 in the synchronization detection unit 62. The block B18 pattern calculation unit 80 performs edge level / state determination, and the comparison determination unit 82 detects a synchronization pattern (IPW6 wave-NPW4 wave-IPW6 wave). On the other hand, in block B20, the data detection / 4-wave operation unit 74 performs addition / subtraction of 4 wobbles circled in FIG. 9 to determine the condition. The order of blocks B18 and B20 may be reversed. In block B22, it is determined whether or not one of the six conditions is satisfied. If all the conditions are not satisfied, the address pattern is not erroneously detected as a synchronization pattern. Therefore, in block B24, the gate signal generation unit 78 generates a gate signal, the AND gate 78 is turned on, and synchronization detection is performed at the head of the physical address. It is output to the detection unit 64. In block B26, the acquisition of the physical address is started after a predetermined timing.

  If even one of the six conditions is satisfied, the address pattern is erroneously detected as a synchronization pattern, and the AND gate 78 is non-conductive in block B28, so that synchronization detection is output to the physical address head detection unit 64. There is nothing.

  As described above, according to the present embodiment, it is easy to realize a circuit that detects a physical address pattern to be excluded from synchronization detection targets by narrowing down the physical address pattern similar to the synchronization pattern to six patterns (circuit scale). As very small as possible). Further, since only a physical address pattern similar to the synchronization pattern is detected, it can be detected without synchronizing with a flywheel counter or the like. Therefore, it is very effective even when asynchronous and can be used at any time. Furthermore, the influence of disturbances such as noise can be suppressed by setting the input to a plurality of bits and performing, for example, level detection and state detection of edge change points.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

  Further, the present invention provides a computer-readable recording recording a program for causing a computer to execute predetermined means (or for causing a computer to function as predetermined means or for causing a computer to realize predetermined functions). It can also be implemented as a medium.

The figure which shows the addressing method of the optical disk of one Embodiment of this invention. The figure which shows the physical address format of HD DVD-R specification. The figure which shows the physical address format of HD DVD-RAM specification. Explanatory drawing which shows an example of the periphery layout of the recording track of the optical disk of one Embodiment of this invention. The figure which shows the structural example of the optical disk apparatus of one Embodiment of this invention. The figure which shows the structural example of the pick-up of the optical disk apparatus of one Embodiment of this invention. The figure which shows the structural example of the wobble PLL part / address detection part 34 of the optical disk apparatus of one Embodiment of this invention. The figure which shows the structural example of the synchronous detection part 62 of the optical disk apparatus of one Embodiment of this invention. The figure which illustrates the physical address pattern which may be misdetected with a synchronous pattern in the optical disk of one Embodiment of this invention. The timing chart which shows an example of the detection operation | movement of the synchronous pattern in one Embodiment of this invention. The timing chart which shows the other example of the detection operation | movement of the synchronous pattern in one Embodiment of this invention. The flowchart which shows an example of the detection operation | movement of the physical address in one Embodiment of this invention.

Explanation of symbols

  34 ... Wobble PLL unit / address detection unit, 51 ... Wobble PLL unit, 52 ... Synchronization / address detection unit, 53 ... Flywheel counter, 56 ... Phase detection unit, 57 ... Phase control unit, 62 ... Synchronization detection unit, 64 ... Physical address head detection unit, 66 ... Physical address holding unit, 72 ... Shift register, 74 ... Data detection / four wave calculation unit, 76 ... Pattern determination unit, 78 ... Gate signal generation unit, 80 ... Pattern calculation unit, 82 ... Comparison Judgment part, 84 ... AND gate.

Claims (10)

Synchronization information consisting of a predetermined bit pattern at a predetermined position, and means for reading a wobble signal from an optical disc in which address information is repeatedly recorded at a position shifted from the synchronization information by a predetermined position;
Means for detecting a predetermined bit pattern from the read wobble signal;
Means for eliminating the output of the detection result of the detection means when the read wobble signal is a similar bit pattern of a predetermined bit pattern;
A synchronization information detection circuit comprising:   The exclusion means includes a means for generating a gate signal when the read wobble signal is not similar to a predetermined bit pattern, and a gate that is rendered conductive by the gate signal and outputs a detection result of the detection means. The synchronization information detection circuit according to claim 1. The wobble signal is modulated such that the unmodulated portion represents bit information “0” and the modulated portion represents bit information “1”.
The predetermined bit pattern is a bit pattern including six bit information “1”, four bit information “0”, and six bit information “1”.
The similar bit pattern includes a plurality of bit information “1”, at least four bit information “0”, and a plurality of bit information “1”. If any four bit information is erroneously detected, the predetermined bit pattern is changed to the predetermined bit pattern. 3. The synchronization information detection circuit according to claim 1, wherein the synchronization information detection circuit is a matching bit pattern. The similar bit pattern is:
A first bit pattern comprising eight bit information “1”, four bit information “0”, and four bit information “1”;
A second bit pattern comprising four bit information “1”, four bit information “0”, and eight bit information “1”;
A third bit pattern comprising four bit information “1”, four bit information “0”, and four bit information “1”;
A fourth bit pattern comprising four bit information “1”, eight bit information “0”, and four bit information “1”;
A fifth bit pattern comprising eight bit information “1”, four bit information “0”, and four bit information “1”;
A sixth bit pattern comprising four bit information “1”, four bit information “0”, and eight bit information “1”;
Consists of
The exclusion means includes a 20-stage shift register, a circuit that generates a gate signal when all of the following conditions are not satisfied,
(D0 + D1)-(D16 + D17)> 0,
(D18 + D19)-(D2 + D3)> 0,
-(D2 + D3)-(D16 + D17)> 0,
-(D6 + D7)-(D12 + D13)> 0,
(D8 + D9)-(D12 + D13)> 0,
(D10 + D11)-(D6 + D7)> 0,
Here, D0, D1, D2, D3, D6, D7, D8, D9, D10, D11, D12, D13, D16, D17, D18, D19 are shift registers 0, 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 16, 17, 18, 19
The synchronization information detection circuit according to claim 3, further comprising: A step of reading wobble signals from an optical disc in which address information is repeatedly recorded at a position shifted by a predetermined position from the synchronization information, and synchronization information consisting of a predetermined bit pattern at a predetermined position;
Detecting a predetermined bit pattern from the read wobble signal;
If the read wobble signal is a similar bit pattern of a predetermined bit pattern, eliminating the output of the detection result of the detection step;
A synchronization information detection method comprising:   6. The synchronization information detection according to claim 5, wherein in the exclusion step, when the read wobble signal does not resemble a predetermined bit pattern, a gate signal is generated and a gate for outputting the detection result of the detection step is turned on. Method. The wobble signal is modulated such that the unmodulated portion represents bit information “0” and the modulated portion represents bit information “1”.
The predetermined bit pattern is a bit pattern including six bit information “1”, four bit information “0”, and six bit information “1”.
The similar bit pattern includes a plurality of bit information “1”, at least four bit information “0”, and a plurality of bit information “1”. If any four bit information is erroneously detected, the predetermined bit pattern is changed to the predetermined bit pattern. 7. The synchronization information detecting method according to claim 5, wherein the matching bit patterns are the same. The similar bit pattern is:
A first bit pattern comprising eight bit information “1”, four bit information “0”, and four bit information “1”;
A second bit pattern comprising four bit information “1”, four bit information “0”, and eight bit information “1”;
A third bit pattern comprising four bit information “1”, four bit information “0”, and four bit information “1”;
A fourth bit pattern comprising four bit information “1”, eight bit information “0”, and four bit information “1”;
A fifth bit pattern comprising eight bit information “1”, four bit information “0”, and four bit information “1”;
A sixth bit pattern comprising four bit information “1”, four bit information “0”, and eight bit information “1”;
Consists of
The exclusion step generates a gate signal when all of the following conditions are not satisfied:
(D0 + D1)-(D16 + D17)> 0,
(D18 + D19)-(D2 + D3)> 0,
-(D2 + D3)-(D16 + D17)> 0,
-(D6 + D7)-(D12 + D13)> 0,
(D8 + D9)-(D12 + D13)> 0,
(D10 + D11)-(D6 + D7)> 0,
Here, D0, D1, D2, D3, D6, D7, D8, D9, D10, D11, D12, D13, D16, D17, D18, and D19 are 0 of the 20-stage shift register to which the read wobble signal is input. 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 16, 17, 18, 19
The synchronization information detecting method according to claim 7, wherein: Synchronization information consisting of a predetermined bit pattern at a predetermined position, and a motor for rotationally driving an optical disc in which address information is repeatedly recorded at a position shifted from the synchronization information by a predetermined position
Means for reading a wobble signal from an optical disk rotated by the motor;
Means for detecting a predetermined bit pattern from the read wobble signal;
Means for permitting output of the detection result of the detection means when the read wobble signal is not a similar bit pattern of a predetermined bit pattern;
An optical disc apparatus comprising: The wobble signal is modulated such that the unmodulated portion represents bit information “0” and the modulated portion represents bit information “1”.
The predetermined bit pattern is a bit pattern including six bit information “1”, four bit information “0”, and six bit information “1”.
The similar bit pattern is:
A first bit pattern comprising eight bit information “1”, four bit information “0”, and four bit information “1”;
A second bit pattern comprising four bit information “1”, four bit information “0”, and eight bit information “1”;
A third bit pattern comprising four bit information “1”, four bit information “0”, and four bit information “1”;
A fourth bit pattern comprising four bit information “1”, eight bit information “0”, and four bit information “1”;
A fifth bit pattern comprising eight bit information “1”, four bit information “0”, and four bit information “1”;
A sixth bit pattern comprising four bit information “1”, four bit information “0”, and eight bit information “1”;
Consists of
The permission means permits the output of the detection signal when all of the following conditions are not satisfied,
(D0 + D1)-(D16 + D17)> 0,
(D18 + D19)-(D2 + D3)> 0,
-(D2 + D3)-(D16 + D17)> 0,
-(D6 + D7)-(D12 + D13)> 0,
(D8 + D9)-(D12 + D13)> 0,
(D10 + D11)-(D6 + D7)> 0,
Here, D0, D1, D2, D3, D6, D7, D8, D9, D10, D11, D12, D13, D16, D17, D18, D19 are 0, 1 of the 20-stage shift register to which the wobble signal is input. 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 16, 17, 18, 19
The optical disc apparatus according to claim 9.

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