JP2009141990A - Motor drive device and electronic apparatus using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a motor drive device for always controlling the rotation speed of a motor highly accurately in accordance with the drive state of the motor. <P>SOLUTION: This motor drive device is configured so that, when the rotation speed of the motor M is constant in correcting periods of motor drive signals U, V, and W, frequency of the correction is reduced, and if the rotation speed of the motor M is changed, the frequency of the correction is increased. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a motor drive device that performs drive control of a motor, and electrical equipment using the motor drive device (general appliances such as a printer and an air conditioner).

  Conventionally, in the field of motor drive devices, a technology that detects the rotation state of a motor using a hall sensor or the like and feeds back the detection result to the drive control of the motor has been put into practical use. This is a very important technology for applications that must be controlled (for example, printers and copiers that require high-precision paper feed control).

As an example of the related art related to the above, Patent Document 1 by the applicant of the present application can be cited.
JP-A-9-163790

  By the way, when drive control of a three-phase motor is performed, the motor drive signal cycle correction is performed for each cycle of the Hall signal (electrical angle 360 degrees) based on the Hall signal of one phase (for example, U phase). If there is a slight variation in the mounting position of the Hall sensors of each phase, the motor drive signal waveform error is less likely to occur, and the rotation unevenness is relatively small, but on the other hand, when the motor rotation speed fluctuates rapidly There is a problem that the motor drive signal waveform correction is not in time, and the waveform of the motor drive signal tends to collapse.

  On the other hand, based on the synthesized hall signal obtained by synthesizing the hall signals of the three phases, the motor drive signal every 1/6 period (electrical angle 60 degrees) or 1/3 period (electrical angle 120 degrees) of the hall signal. If it is a configuration that performs the period correction of the motor, even when the rotational speed of the motor suddenly fluctuates, the period of the motor drive signal can be corrected without delay. When the mounting positions of the hall sensors of the respective phases vary, there are problems that the waveform error of the motor drive signal is likely to occur and the rotation unevenness is relatively large.

  In view of the above problems, the present invention provides a motor drive device capable of always controlling the rotational speed of a motor with high accuracy in accordance with the drive state of the motor, and an electric device using the same. With the goal.

  In order to achieve the above object, a motor drive device according to the present invention is a motor drive device that performs drive control of a motor, and that when the period of a motor drive signal is corrected, the rotation speed of the motor is constant. When it is determined, the frequency of the cycle correction is decreased, and conversely, when it is determined that the rotation speed of the motor is fluctuating, the frequency of the cycle correction is increased (first configuration).

  The motor driving device having the first configuration includes an interpolation pulse signal generation circuit that receives a plurality of phase Hall signals and generates an interpolation pulse signal using at least one phase Hall signal; A motor drive signal generation circuit for generating a waveform of the motor drive signal in a cycle based on the insertion pulse signal, wherein the interpolation pulse signal generation circuit has a number of pulses generated in one cycle of the Hall signal. When adjusting the pulse generation interval of the interpolated pulse signal so as to be a predetermined target value, when it is determined that the rotation speed of the motor is constant, the adjustment frequency of the pulse generation interval is decreased, and the motor When it is determined that there is a fluctuation in the rotation speed, a configuration (second configuration) for increasing the adjustment frequency of the pulse generation interval may be used.

  In the motor driving device having the second configuration, the interpolation pulse signal generation circuit generates a first interpolation pulse signal, and the number of pulses generated in one cycle of the Hall signal is a predetermined target. A first interpolation pulse signal generation unit that adjusts a pulse generation interval of the first interpolation pulse signal for each period of the Hall signal so as to be a value; The pulse generation interval of the second interpolated pulse signal is adjusted every 1 / m cycle (where m> 1) of the Hall signal so that the number of pulses generated in one cycle of the Hall signal becomes a predetermined target value. A second interpolation pulse signal generation unit that performs; a selector that outputs one of the first interpolation pulse signal and the second interpolation pulse signal as the interpolation pulse signal in response to a predetermined switching signal; and the motor The rotation speed is constant Better to comprising a configuration (third configuration); for determining whether the judge, the the switching signal generating unit for generating a switching signal.

  Further, in the motor drive device having the third configuration, the first interpolation pulse signal generation unit divides the reference clock signal sufficiently faster than the hall signal by n (where n> m) and performs the first division. A first frequency divider that generates a frequency-divided clock signal; a first counter that counts the number of pulses of the first frequency-divided clock signal and clears the count value at the pulse edge of the hall signal; and at the pulse edge of the hall signal A first register for holding the count value of the first counter; a second counter for counting the number of pulses of the reference clock signal and clearing the count value at the pulse edge of the first interpolation pulse signal or the pulse edge of the Hall signal And a first comparator that generates a pulse of the first interpolated pulse signal when the hold value of the first register and the count value of the second counter coincide with each other. A second interpolated pulse signal generator that synthesizes a hall signal of a plurality of phases and generates a synthesized hall signal whose logic is inverted at each phase pulse edge; and the reference clock signal A second frequency divider that divides the signal by n / m to generate a second frequency-divided clock signal; counts the number of pulses of the second frequency-divided clock signal, and clears the count value at the pulse edge of the synthesized Hall signal A third counter; a second register for holding the count value of the third counter at the pulse edge of the combined Hall signal; and counting the number of pulses of the reference clock signal and the pulse edge of the second interpolation pulse signal or the combined A fourth counter that clears the count value at the pulse edge of the Hall signal; and a second counter when the hold value of the second register matches the count value of the fourth counter. A second comparator for generating a pulse of interpolation pulse signal; a has made structure better to (fourth configuration).

  Further, in the motor driving device having the second configuration, the interpolated pulse signal generation circuit synthesizes a hall signal of a plurality of phases and generates a synthesized hall signal whose logic is inverted at each pulse edge of each phase. A hall signal generation unit; a first frequency divider that divides a reference clock signal sufficiently faster than the hall signal by n (where n> 1) to generate a first divided clock signal; and the reference clock signal a second frequency divider that divides n / m (where n> m> 1) to generate a second frequency-divided clock signal; according to a predetermined switching signal, a one-phase Hall signal and the combined Hall signal A first selector that outputs one of them as a first selection signal; a second selector that outputs one of a first divided clock signal and a second divided clock signal as a second selection signal in response to the switching signal; The selector; the second selection signal pulse A first counter that counts the number and clears the count value at the pulse edge of the first selection signal; a register that holds the count value of the first counter at the pulse edge of the first selection signal; and the number of pulses of the reference clock signal A second counter that clears the count value at the pulse edge of the interpolation pulse signal or the pulse edge of the first selection signal; and when the hold value of the register and the count value of the second counter match each other, A comparison unit that generates a pulse of the interpolation pulse signal; and a switching signal generation unit that determines whether or not the rotation speed of the motor is constant and generates the switching signal. A fifth configuration may be used.

  Further, in the motor drive device having the fourth configuration, the switching signal generation unit counts the number of pulses of the second interpolation pulse signal and clears the count value at the pulse edge of the composite Hall signal. A third register for holding the count value of the fifth counter at the pulse edge of the composite Hall signal; and determining whether the hold value of the third register is within a predetermined target range; And a determination unit to be generated (sixth configuration).

  Alternatively, in the motor driving device having any one of the third to fifth configurations, the switching signal generation unit includes an FG signal generation unit that generates an FG signal having a frequency corresponding to a rotation speed of the motor; A ready signal generation unit that determines whether or not the frequency of the signal falls within a target range instructed by the microcomputer and returns a ready signal to the microcomputer, and diverts the ready signal as the switching signal. You may make it the structure (7th structure) to do.

  An electric device according to the present invention is an electric device comprising a motor and a motor drive device that performs drive control of the motor, and the motor drive device is any one of the first to seventh items. It is set as the structure (8th structure) which has the motor drive device which consists of these structures.

  With the motor drive device according to the present invention and an electric device using the same, it is possible to always control the rotation speed of the motor with high accuracy in accordance with the drive state of the motor.

  Hereinafter, a detailed description will be given by exemplifying a case where the present invention is applied to a motor drive device that performs drive control of a three-phase motor (energization control of a sine wave or wide angle wave).

  FIG. 1 is a block diagram showing a first embodiment of a motor driving apparatus according to the present invention.

  The motor drive device of the present embodiment is means for controlling the drive of the motor M by supplying drive currents to the three-phase (U-phase, V-phase, W-phase) coils forming the motor M, respectively. This is a semiconductor device (so-called motor driver IC) in which an interpolation pulse signal generation circuit A and a motor drive signal generation circuit B are integrated.

  The interpolation pulse signal generation circuit A receives three-phase (U-phase, V-phase, and W-phase) Hall signals HU, HV, and HW, and generates an interpolation pulse signal DIVCLK using at least one-phase Hall signal. This means includes a first interpolation pulse signal generation unit A1, a second interpolation pulse signal generation unit A2, a selector A3, and a switching signal generation unit A4.

  The motor drive signal generation circuit B is a means for generating a waveform of the motor drive signal (U, V, W) at a period based on the interpolation pulse signal DIVCLK. The motor B signal generation circuit B is a digital B / W, a decoder B2U, a decoder B2V, It comprises analog converters B3U, B3V, B3W and a driver B4.

  Although not explicitly shown in the figure, the motor driving device of the present embodiment has a three-phase (U-phase, V-phase, W-phase) Hall sensor externally attached as means for detecting the rotational state of the motor M. Has been. In addition, the motor drive device of the present embodiment compares the sinusoidal signals that are differentially input from the Hall sensors of each phase with each other to generate pulsed Hall signals HU, HV, and HW, 1, Hall comparators for sending to the second interpolation pulse generators A1 and A2 are incorporated. Note that the phase difference between the hall signals HU, HV, and HW is 120 degrees.

  Moreover, as an example of an electric device on which the motor driving device of the present embodiment is mounted, there can be mentioned all home appliances on which the motor M is mounted, such as a printer and an air conditioner.

  The first interpolation pulse signal generation unit A1 is a means for receiving the input of the hall signal HU and generating a first interpolation pulse signal DIVCLK1, and includes a first frequency divider A11, a first counter A12, It has a register A13, a second counter A14, and a first comparison unit A15.

  Note that the first interpolation pulse signal generation unit A1 generates the first interpolation pulse signal DIVCLK1 so that the number of pulses generated in one cycle of the Hall signal becomes a predetermined target value. The pulse generation interval of the first interpolation pulse signal DIVCLK1 is adjusted for each cycle. The generation operation of the first interpolation pulse signal DIVCLK1 will be described in detail later.

  The second interpolation pulse signal generation unit A2 is a means for receiving the input of the hall signals HU, HV, HW for three phases and generating the second interpolation pulse signal DIVCLK2, and the combined hall signal generation unit A20, A second frequency divider A21, a third counter A22, a second register A23, a fourth counter A24, and a second comparison unit A25 are included.

  Note that the second interpolation pulse signal generation unit A2 generates the second interpolation pulse signal DIVCLK2 so that the number of pulses generated in one cycle of the Hall signal becomes a predetermined target value. The pulse generation interval of the second interpolation pulse signal DIVCLK2 is adjusted every / 6 cycle or every 1/3 cycle. The generation operation of the second interpolation pulse signal DIVCLK2 will be described later. Detailed explanation is given.

  The selector A3 selects one of the first interpolation pulse signal DIVCLK1 and the second interpolation pulse signal DIVCLK2 as the interpolation pulse signal DIVCLK based on the switching signal SW input from the switching signal generator A4. Is sent to the counter B1.

  The switching signal generator A4 is a means for determining whether or not the rotational speed of the motor M is constant and generating the switching signal SW.

  The counter B1 is means for incrementing the count value WCS every time the number of pulses of the interpolation pulse signal DIVCLK reaches a predetermined value.

  Decoders B2U, B2V, and B2W are means for generating three-phase (U-phase, V-phase, and W-phase) logic waveform signals DECU, DECV, and DECW that are 120 degrees out of phase with each other based on count value WCS. .

  The digital / analog converters B3U, B3V, and B3W convert the logic waveform signals DECU, DECV, and DECW into analog signals, thereby generating three-phase (U-phase, V-phase, and W-phase) motor drive signals U, V, and W. Is a means for generating

  The driver B4 uses three-phase (U-phase, V-phase, W-phase) PWM [Pulse Width Modulation] signals generated by comparing the motor drive signals U, V, W with predetermined triangular wave signals, respectively. This is means for supplying a drive current to the coils of each phase forming the motor M by driving the push-pull output stage of the phase.

  Next, a detailed description will be given of the cycle correction operation of the motor drive signals U, V, and W.

  First, the operation of the first interpolation pulse signal generation unit A1 will be described in detail with reference to FIG.

  FIG. 2 is a timing chart showing how the period of the motor drive signal is corrected for each period of the Hall signal (electrical angle 360 degrees). In FIG. 2, in order from the top, the three-phase hall signals HU, HV, HW, the reference clock signal CLK, the output signal (first divided clock signal) D11 of the first divider A11, and the first counter A12 The count value C12, the hold value R13 of the first register A13, the count value C14 of the second counter A14, the first interpolation pulse signal DIVCLK1, and the three-phase motor drive signals U, V, and W are shown. Regarding the three-phase motor drive signals U, V, and W, the solid line indicates an actual waveform, and the broken line indicates an ideal waveform.

  In the first interpolation pulse signal generation unit A1, the first frequency divider A11 performs the first division by dividing the reference clock signal CLK by n (in the example of FIG. 2, 360 division (n = 360)). A peripheral clock signal D11 is generated. Further, the first frequency divider A11 resets the frequency dividing operation for each rising edge of the U-phase hall signal HU.

  The reference clock signal CLK is a clock signal sufficiently faster than the hall signals HU, HV, HW (for example, the frequency of the hall signals HU, HV, HW is several [kHz], whereas the reference clock signal CLK The frequency is several tens [MHz]).

  Referring to the example of FIG. 2, during the period T1, 1080 (= 360 × 3) pulses are generated as the reference clock signal CLK. As the first divided clock signal D11, Three pulses are generated. Further, during the period T2 or the period T3, 1440 (= 360 × 4) pulses are generated as the reference clock signal CLK, and four pulses are generated as the first divided clock signal D11. Has been. That is, the period T2 and the period T3 are extended by about 33 [%] compared to the period T1.

  The first counter A12 counts the number of pulses of the first divided clock signal D11 and clears the count value C12 at the rising edge of the U-phase hall signal HU. Referring to the example of FIG. 2, during the period T1, the count value C12 is incremented to “3” and then cleared at the rising edge of the U-phase hall signal HU. Further, during the period T2 or the period T3, the count value C12 is incremented to “4” and then cleared at the rising edge of the U-phase hall signal HU.

  The first register A13 holds the count value C12 of the first counter A12 (final count value immediately before clearing) at the rising edge of the U-phase hall signal HU. That is, the hold value R13 of the first register A13 is a value reflecting one cycle length of the U-phase hall signal HU. Referring to the example of FIG. 2, between the period T1 and the period T2, the last count value “3” of the first counter A12 in the period T0 (not shown) and the period T1 is held as the hold value R13. ing. Further, during the period T3, the final count value “4” of the first counter A12 in the period T2 is held as the hold value R13.

  Second counter A14 counts the number of pulses of reference clock signal CLK, and clears count value C14 at the rising edge of first interpolation pulse signal DIVCLK1 or the rising edge of U-phase hall signal HU. Referring to the example of FIG. 2, during the period T1 and the period T2, the count value C14 is incremented to “3”, and then the rising edge of the first interpolation pulse signal DIVCLK1 or the U-phase hall signal HU Cleared on the rising edge. During the period T3, after the count value C14 is incremented to “4”, it is cleared at the rising edge of the first interpolation pulse signal DIVCLK1 or the rising edge of the U-phase hall signal HU.

  The first comparison unit A15 generates a pulse of the first interpolation pulse signal DIVCLK1 when the hold value R13 of the first register A13 and the count value of the second counter A14 match each other. Referring to the example of FIG. 2, during the period T1 and the period T2, every time three pulses of the reference clock signal CLK are generated, one pulse of the first interpolation pulse signal DIVCLK1 is generated. Further, during the period T3, every time four pulses of the reference clock signal CLK are generated, one pulse of the first interpolation pulse signal DIVCLK1 is generated.

  That is, when the first interpolation pulse signal generation unit A1 generates the first interpolation pulse signal DIVCLK1, the number of pulses generated in one cycle of the Hall signals HU, HV, and HW is a predetermined target value (in FIG. 2). In the example, the pulse generation interval of the first interpolated pulse signal DIVCLK1 is adjusted for each cycle of the U-phase Hall signal HU so as to be 360 pulses.

  More specifically, the first interpolation pulse signal generation unit A1 reversely increases the pulse generation interval of the first interpolation pulse signal DIVCLK1 in the current cycle as the cycle length of the previous cycle is longer. As the cycle length is shorter, the pulse generation of the first interpolation pulse signal DIVCLK1 is performed for each cycle of the U-phase Hall signal HU so that the pulse generation interval of the first interpolation pulse signal DIVCLK1 in the current cycle is adjusted to be shorter. The interval is adjusted.

  Next, the operation of the second interpolation pulse signal generation unit A2 will be described in detail with reference to FIG.

  FIG. 3 is a timing chart showing how the period of the motor drive signal is corrected every 1/6 period (electrical angle 60 degrees) of the Hall signal. 3, in order from the top, the three-phase hall signals HU, HV, HW, the synthesized hall signal MIX, the reference clock signal CLK, the output signal (second divided clock signal) D21 of the second divider A21, The count value C22 of the third counter A22, the hold value R23 of the second register A23, the count value C24 of the fourth counter A24, the second interpolation pulse signal DIVCLK2, and the three-phase motor drive signals U, V, W are shown. Has been. Regarding the three-phase motor drive signals U, V, and W, the solid line indicates an actual waveform, and the broken line indicates an ideal waveform.

  In the second interpolated pulse signal generation unit A2, the combined Hall signal generation unit A20 combines the three-phase Hall signals HU, HV, and HW, and generates a combined Hall signal MIX whose logic is inverted at each phase pulse edge. To do. Referring to the example of FIG. 3, the combined Hall signal MIX is at a low level at the rising edges of the Hall signals HU, HV, and HW, and is at a high level at the falling edges of the Hall signals HU, HV, and HW. It becomes.

  The second frequency divider A21 divides the reference clock signal CLK by n / m (in the example of FIG. 3, the frequency is divided by 60 (m = 6, n = 360)), thereby generating the second frequency-divided clock signal D21. Generate. The second frequency divider A21 resets the frequency dividing operation for each rising edge and falling edge of the composite Hall signal MIX.

  Referring to the example of FIG. 3, during the cycle T1, 1080 (= 60 × 18) pulses are generated as the reference clock signal CLK, and the second divided clock signal D21 is as follows: Eighteen pulses are generated. Further, during the period T2 and the period T3, 1440 (= 60 × 24) pulses are generated as the reference clock signal CLK, and 24 pulses are generated as the second divided clock signal D21. Has been. That is, the period T2 and the period T3 are extended by about 33 [%] compared to the period T1.

  The third counter A22 counts the number of pulses of the second frequency-divided clock signal D21 and clears the count value C22 at the rising edge and the falling edge of the composite hall signal MIX. Referring to the example of FIG. 3, during the period T11 to the period T16 and the period T21, after the count value C22 is incremented to “3”, the rising edge and the rising edge of the composite Hall signal MIX are respectively obtained. Cleared on the falling edge. Also, between the period T22 to the period T26 and the period T31 to the period T36, after the count value C22 is incremented to “4”, it is cleared at the rising edge and the falling edge of the composite hall signal MIX. Yes.

  The second register A23 holds the count value C22 (the final count value immediately before the clear) of the third counter A22 at the rising edge and the falling edge of the composite hall signal MIX. That is, the hold value R23 of the second register A23 is a value reflecting the 1/2 cycle length of the combined Hall signal MIX (1/6 cycle length of the Hall signals HU, HV, HW). Referring to the example of FIG. 3, the final count value “3” of the third counter A22 in the immediately preceding cycle is held as the hold value R23 between the cycle T11 to the cycle T16 and the cycle T21. ing. Further, between the period T22 to the period T26 and the period T31 to the period T36, the final count value “4” of the third counter A22 in the immediately preceding period is held as the hold value R23, respectively.

  The fourth counter A24 counts the number of pulses of the reference clock signal CLK, and clears the count value C24 at the rising edge of the second interpolation pulse signal DIVCLK2 or the rising edge of the composite hall signal MIX. Referring to the example of FIG. 3, the rising edge of the second interpolation pulse signal DIVCLK2 after the count value C24 is incremented to “3” between the period T11 to the period T16 and the period T21, respectively. Alternatively, it is cleared at the rising edge of the composite hall signal MIX. Further, between the period T22 to the period T26 and the period T31 to the period T36, the count value C24 is incremented to “4”, and then the rising edge of the second interpolation pulse signal DIVCLK2 or the composite Hall signal MIX Cleared on the rising edge.

  The second comparison unit A25 generates a pulse of the second interpolation pulse signal DIVCLK2 when the hold value R23 of the second register A23 and the count value of the fourth counter A24 match each other. Referring to the example of FIG. 3, during the period T11 to the period T16 and the period T21, the second interpolation pulse signal DIVCLK2 is one pulse every time three pulses of the reference clock signal CLK are generated. Has been generated. Further, between the period T22 to the period T26 and between the period T31 to the period T36, one pulse of the second interpolation pulse signal DIVCLK2 is generated every time four pulses of the reference clock signal CLK are generated.

  That is, when the second interpolation pulse signal generation unit A2 generates the second interpolation pulse signal DIVCLK2, the number of pulses generated in one cycle of the Hall signals HU, HV, and HW is a predetermined target value (in FIG. 3). In the example, the pulse of the second interpolated pulse signal DIVCLK2 every 1/2 cycle of the combined Hall signal MIX (and thus every 1/6 cycle of the Hall signals HU, HV, HW). The generation interval is adjusted.

  Specifically, the second interpolated pulse signal generation unit A2 is configured to increase the pulse generation interval of the second interpolated pulse signal DIVCLK2 in the current cycle as the cycle length of the previous cycle is longer. The shorter the cycle length, the shorter the pulse generation interval of the second interpolated pulse signal DIVCLK2 in the current cycle is adjusted every 1/2 cycle of the composite Hall signal MIX (by extension, the Hall signals HU, HV, The pulse generation interval of the second interpolation pulse signal DIVCLK2 is adjusted every 1/6 cycle of the HW.

  Next, switching control between the first interpolation pulse signal DIVCLK1 and the second interpolation pulse signal DIVCLK2 will be described.

  As described above, the pulse generation interval of the first interpolated pulse signal DIVCLK1 is adjusted for each period (electrical angle 360 degrees) of the Hall signals HU, HV, and HW. Therefore, if the motor drive signals U, V, and W are generated in a cycle based on the first interpolation pulse signal DIVCLK1, the motor drive signals U, V, W waveform errors are less likely to occur, and rotation unevenness can be kept relatively small. However, when the rotational speed of the motor M suddenly fluctuates, the period correction of the motor drive signals U, V, and W is not in time, and the motor drive signals U, V, and W are likely to be corrupted.

  Referring to the example of FIG. 2, in the period T1 and the period T3 in which the rotation speed of the motor M is stable, the period length of the previous period and the current period coincide with each other, so that a pulse generated in one period The number becomes a predetermined target value (360 pulses), and ideal waveforms can be output as the motor drive signals U, V, W, but the period T2 in which the rotational speed of the motor M fluctuates (decreases). Then, the pulse generation interval of the first interpolated pulse signal DIVCLK1 is adjusted so as to reflect the cycle length of the shorter cycle T1, so that the number of pulses generated in one cycle is larger than a predetermined target value. Thus, the phase advances to the motor drive signals U, V, W, and a phase is generated.

  On the other hand, the pulse generation interval of the second interpolated pulse signal DIVCLK2 is adjusted every 1/6 period (electrical angle 60 degrees) of the hall signals HU, HV, HW. In other words, the pulse generation interval of the second interpolation pulse signal DIVCLK2 is adjusted with a frequency six times higher than that of the first interpolation pulse signal DIVCLK1. Therefore, if the motor drive signals U, V, and W are generated in a cycle based on the second interpolation pulse signal DIVCLK2, even when the rotation speed of the motor M changes rapidly, the motor drive signals U, V, Since the period of W can be corrected, it is difficult for the motor drive signals U, V, and W to be corrupted.

  Referring to the example of FIG. 3, even when the rotational speed of the motor M fluctuates (decreases) in the cycle T21, the next cycle T22 reflects the cycle length of the cycle T21 and is delayed. Since the pulse generation interval of the second interpolation pulse signal DIVCLK2 can be adjusted without any delay, the advance phase of the motor drive signals U, V, W is minimized (the advance phase generated when the first interpolation pulse signal DIVCLK1 is used). 1/6).

  However, since the second interpolation pulse signal DIVCLK2 is generated from the synthesized Hall signal MIX obtained by synthesizing the three-phase Hall signals HU, HV, and HW, when the mounting position of the Hall sensor of each phase varies, Waveform errors of the motor drive signals U, V, W are likely to occur, and the pulse generation interval is adjusted at a frequency higher than that of the first interpolation pulse signal DIVCLK1, so that the rotation unevenness is also relatively large.

  Therefore, in view of the above trade-off, when it is determined that the rotational speed of the motor M is constant, the motor drive device of the present embodiment selects the first interpolation pulse signal DIVCLK1 as the interpolation pulse signal DIVCLK. Conversely, when it is determined that the rotational speed of the motor M has changed, the second interpolation pulse signal DIVCLK2 is selected as the interpolation pulse signal DIVCLK.

  That is, in the motor drive device of the present embodiment, the interpolation pulse signal generation circuit A has the interpolation pulse signal so that the number of pulses generated in one cycle of the hall signals HU, HV, and HW becomes a predetermined target value. When adjusting the pulse generation interval of DIVCLK, if it is determined that the rotational speed of the motor M is constant, the frequency of adjusting the pulse generation interval is decreased, and conversely, it is determined that the rotational speed of the motor M is fluctuating. In this case, the frequency of adjusting the pulse generation interval is increased.

  By adopting such a configuration, the pulse generation interval of the interpolation pulse signal DIVCLK is adjusted at an appropriate frequency according to the driving state of the motor M, and the frequency correction frequency of the motor driving signals U, V, W is optimized. Therefore, the rotational speed of the motor M can always be controlled with high accuracy.

  In the above embodiment, the second interpolation pulse signal generation unit A2 generates the pulse of the second interpolation pulse signal DIVCLK2 every 1/6 period (electrical angle 60 degrees) of the hall signals HU, HV, HW. The configuration for adjusting the interval has been described as an example, but the configuration of the present invention is not limited to this. For example, as shown in FIG. 4, the frequency dividing ratio of the second frequency divider A21 is By performing the clearing of the third counter A22 and the fourth counter A24 and the holding of the second register A23 only at the rising edge of the composite hall signal MIX, the hall signals HU, HV, HW are set to 1/120. The pulse generation interval of the second interpolation pulse signal DIVCLK2 may be adjusted every 1/3 period (electrical angle 120 degrees).

  Next, the configuration and operation of the switching signal generation unit A4 will be described in detail.

  FIG. 5 is a block diagram illustrating a configuration example of the switching signal generation unit A4.

  As shown in FIG. 5, the switching signal generation unit A4 of this configuration example includes a fifth counter A41, a third register A42, and a determination unit A43.

  The fifth counter A41 counts the number of pulses of the second interpolation pulse signal DIVCLK2, and clears the count value C41 at the rising edge and falling edge of the composite Hall signal MIX. Referring to the example of FIG. 3, during the period T11 to the period T36 (excluding the period T21), after the count value C41 is incremented to “60”, the rising edge of the composite Hall signal MIX and Cleared on falling edge. On the other hand, during the period T21 in which the rotation speed of the motor M fluctuates (decreases), the count value C41 is incremented to “80” and then cleared at the rising and falling edges of the composite hall signal MIX. Yes.

  The third register A42 holds the count value C41 (final count value immediately before clear) of the fifth counter A41 at the rising edge and falling edge of the composite hall signal MIX. That is, the hold value R42 of the third register A42 is a value reflecting the 1/2 cycle length of the combined Hall signal MIX (1/6 cycle length of the Hall signals HU, HV, HW). Referring to the example of FIG. 3, after the expiration of the period T11 to the period T36 (excluding the period T21), the final count value “60” of the fifth counter A41 is held as the hold value R42, respectively. On the other hand, after the expiration of the period T21 in which the rotational speed of the motor M has changed (decreased), the final count value “80” of the fifth counter A41 is held as the hold value R42.

  The determination unit A43 determines whether or not the hold value R42 of the third register A42 is within a predetermined target range (for example, “50” to “70”), and generates the switching signal SW.

  Referring to the example of FIG. 3, the hold value “60” obtained after the expiration of the period T11 to the period T36 (excluding the period T21) is within the predetermined target range. It is determined that the rotation speed of the motor M is constant, and the first logic switching signal SW is generated so that the first interpolation pulse signal DIVCLK1 is selected as the interpolation pulse signal DIVCLK.

  On the other hand, the hold value “80” obtained after the expiration of the cycle T21 does not fall within the predetermined target range, so that it is determined that the rotational speed of the motor M has fluctuated, and the second value is set as the interpolation pulse signal DIVCLK. A second logic switching signal SW is generated so as to select the interpolation pulse signal DIVCLK2.

  With such a configuration, the switching signal SW can be generated with a very simple configuration. Further, if the second interpolation pulse signal DIVCLK2 is monitored and the switching signal SW is generated, it is possible to detect early whether or not the rotational speed of the motor M has changed. Switching control between the interpolation pulse signal DIVCLK1 and the second interpolation pulse signal DIVCLK2 can be executed without delay.

  FIG. 6 is a block diagram illustrating another configuration example of the switching signal generation unit A4.

  As shown in FIG. 6, the switching signal generation unit A4 of the present configuration example includes an FG signal generation unit A44 and a ready signal generation unit A45.

  The FG signal generation unit A44 generates an FG signal having a pulse frequency corresponding to the rotational speed of the motor M (a rotational speed pulse signal indicating the rotational speed of the motor M).

  The ready signal generator A45 determines whether or not the pulse frequency of the FG signal is within the target range indicated by the rotation speed control signal CTRL from the microcomputer, and returns a ready signal READY to the microcomputer.

  The above-described FG signal generation unit A45 and ready signal generation unit A45 are also mounted in a conventional motor drive device as means for notifying the microcomputer that the motor M has reached a constant rotational speed. In the switching signal generator A4, the ready signal READY is used as the switching signal SW.

  With such a configuration, the switching signal SW can be generated without unnecessarily increasing the circuit scale. In addition, since the process for determining whether or not the pulse frequency of the FG signal is within a predetermined target range is performed in a cycle shorter than one cycle of the hall signals HU, HV, and HW, the rotational speed of the motor M varies. Thus, it is possible to detect whether or not the occurrence of the error has occurred at an early stage, and to perform switching control between the first interpolation pulse signal DIVCLK1 and the second interpolation pulse signal DIVCLK2 without delay.

  In the above embodiment, the configuration in which the first interpolation pulse signal generation unit A1 and the second interpolation pulse signal generation unit A2 are individually provided has been described. However, the configuration of the present invention is not limited to this. As shown in FIG. 7, the first counter A12 and the third counter A22, the first register A13 and the second register A23, the second counter A14 and the fourth counter A24, and the first comparison The configuration may be such that the part A15 and the second comparison part A25 are shared, and the first frequency divider A11 and the second frequency divider A21 are switched and used.

  FIG. 7 is a block diagram showing a second embodiment of the motor drive device according to the present invention.

  As shown in FIG. 7, in the motor drive device of this embodiment, the interpolation pulse signal generation circuit A ′ combines the three-phase hall signals HU, HV, and HW, and the logic is inverted for each phase pulse edge. A combined hall signal generator A20 that generates a combined hall signal MIX; a first part that divides the reference clock signal CLK sufficiently faster than the hall signals HU, HV, and HW by 360 to generate the first divided clock signal D11 A frequency divider A11; a second frequency divider A21 that generates a second frequency-divided clock signal D21 by dividing the reference clock signal CLK by 60 (or 120); and a U-phase according to a predetermined switching signal SW A first selector A31 that outputs one of the hall signal HU and the synthesized hall signal MIX as the first selection signal SEL1, and the first frequency-divided clock signal D11 and the second frequency-divided according to the switching signal SW A second selector A32 that outputs any one of the lock signals D21 as the second selection signal SEL2, and counts the number of pulses of the second selection signal SEL2, and clears the count value C12 at the pulse edge of the first selection signal SEL1. 1 counter A12; register A13 holding the count value C12 of the first counter A12 at the pulse edge of the first selection signal SEL1, and counting the number of pulses of the reference clock signal CLK, and the pulse edge of the first selection signal SEL1 A second counter A14 that clears the count value C14 at the pulse edge of the insertion pulse signal DIVCLK; and a pulse of the interpolation pulse signal DIVCLK when the hold value R13 of the register A13 and the count value C14 of the second counter A14 match each other. Comparison unit A15 to be generated; Comprising a; speed to determine whether or not a constant, the switching signal generator unit A4 for generating a switching signal SW.

  With this configuration, the circuit scale of the interpolation pulse signal generation circuit A ′ can be reduced. When the configuration of the present embodiment is employed, it is desirable to employ the configuration shown in FIG. 6 as the switching signal generation unit A4 and use the ready signal READY as the switching signal SW.

  The configuration of the present invention can be variously modified within the scope of the present invention in addition to the above embodiment.

  That is, the technical scope of the present invention is not limited to the above embodiment, and when performing the period correction of the motor drive signals U, V, W, when determining that the rotational speed of the motor M is constant, When the frequency of the cycle correction is decreased and, conversely, when it is determined that the rotational speed of the motor M is fluctuating, the configuration of increasing the cycle correction frequency is widely included.

  The present invention is a useful technique for controlling the rotational speed of a motor (for example, a paper feed motor used in a printer or a copier) with high accuracy.

These are block diagrams which show 1st Embodiment of the motor drive device which concerns on this invention. These are timing charts showing how the period of the motor drive signal is corrected for each period of the Hall signal (electrical angle of 360 degrees). These are timing charts showing how the period of the motor drive signal is corrected every 1/6 period (electrical angle 60 degrees) of the Hall signal. These are timing charts showing how the period of the motor drive signal is corrected every 1/3 period (electrical angle of 120 degrees) of the Hall signal. These are block diagrams which show the example of 1 structure of switching signal generation part A4. These are block diagrams which show another structural example of switching signal generation part A4. These are block diagrams which show 2nd Embodiment of the motor drive device which concerns on this invention.

Explanation of symbols

A, A ′ interpolation pulse signal generation circuit A1 first interpolation pulse generation unit A11 first frequency divider A12 first counter A13 first register A14 second counter A15 first comparison unit A2 second interpolation pulse generation unit A20 Synthetic Hall signal generator A21 Second frequency divider A22 Third counter A23 Second register A24 Fourth counter A25 Second comparator A3 Selector A31 First selector A32 Second selector A4 Switching signal generator A41 Fifth counter A42 Third Register A43 Determination unit A44 FG signal generation unit A45 Ready signal generation unit B Motor drive signal generation circuit B1 Counter B2U, B2V, B2W Decoder B3U, B3V, B3W Digital / analog converter B4 Driver M Motor

Claims (8)

  A motor drive device that performs drive control of a motor, and when performing cycle correction of a motor drive signal, when it is determined that the rotation speed of the motor is constant, the frequency of the cycle correction is decreased, and conversely, A motor drive device characterized by increasing the frequency of the period correction when it is determined that the rotational speed of the motor is fluctuated. An interpolation pulse signal generation circuit that receives a plurality of phase Hall signals and generates an interpolation pulse signal using at least one phase Hall signal; and generates a waveform of the motor drive signal in a cycle based on the interpolation pulse signal A motor drive signal generation circuit to perform,
The interpolation pulse signal generation circuit adjusts the pulse generation interval of the interpolation pulse signal so that the number of pulses generated in one cycle of the Hall signal becomes a predetermined target value. The frequency of adjusting the pulse generation interval is decreased when it is determined that the pulse generation interval is constant, and conversely, the frequency of adjustment of the pulse generation interval is increased when it is determined that the rotational speed of the motor is fluctuating. The motor driving device according to claim 1.   The interpolation pulse signal generation circuit generates a first interpolation pulse signal so that the number of pulses generated in one period of the Hall signal becomes a predetermined target value for each period of the Hall signal. A first interpolation pulse signal generation unit for adjusting a pulse generation interval of the first interpolation pulse signal; and when generating the second interpolation pulse signal, the number of pulses generated in one cycle of the Hall signal is a predetermined number A second interpolation pulse signal generation unit for adjusting a pulse generation interval of the second interpolation pulse signal every 1 / m period (where m> 1) of the Hall signal so as to be a target value; A selector that outputs one of the first interpolation pulse signal and the second interpolation pulse signal as the interpolation pulse signal according to the signal; and determines whether or not the rotational speed of the motor is constant , A switching signal for generating the switching signal Motor driving device according to claim 2, characterized by comprising a; a formed unit. A first frequency divider for generating a first frequency-divided clock signal by dividing a reference clock signal sufficiently faster than the hall signal by n (where n>m); A first counter that counts the number of pulses of the one-frequency-divided clock signal and clears the count value at the pulse edge of the hall signal; a first register that holds the count value of the first counter at the pulse edge of the hall signal; A second counter that counts the number of pulses of the reference clock signal and clears the count value at the pulse edge of the first interpolation pulse signal or the pulse edge of the Hall signal; the hold value of the first register and the count of the second counter A first comparator for generating a pulse of the first interpolated pulse signal when the values match each other;
A second interpolation pulse signal generation unit configured to synthesize a hall signal of a plurality of phases and generate a synthesis hall signal whose logic is inverted at each pulse edge of each phase; a second frequency divider that divides the frequency by m and generates a second frequency-divided clock signal; a third counter that counts the number of pulses of the second frequency-divided clock signal and clears the count value at the pulse edge of the composite Hall signal A second register for holding a count value of a third counter at the pulse edge of the composite Hall signal; and counting the number of pulses of the reference clock signal to detect the pulse edge of the second interpolation pulse signal or the composite Hall signal A fourth counter that clears the count value at the pulse edge; a second interpolation pulse when the hold value of the second register matches the count value of the fourth counter Motor driving device according to claim 3, characterized by comprising a; a second comparator for generating an issue of pulses.   The interpolated pulse signal generation circuit synthesizes a hall signal of a plurality of phases and generates a synthesized hall signal whose logic is inverted every pulse edge of each phase; and a sufficiently high speed than the hall signal A first divider for dividing the reference clock signal by n (where n> 1) to generate a first divided clock signal; and dividing the reference clock signal by n / m (where n> m> 1) A second frequency divider for generating a second frequency-divided clock signal; a first selector for outputting one of the one-phase hall signal and the synthesized hall signal as the first selection signal in response to a predetermined switching signal; And a second selector that outputs one of the first divided clock signal and the second divided clock signal as the second selection signal according to the switching signal; and counting the number of pulses of the second selection signal; Counted at the pulse edge of the first selection signal A first counter for clearing the value; a register for holding the count value of the first counter at the pulse edge of the first selection signal; the number of pulses of the reference clock signal is counted; A second counter that clears the count value at the pulse edge of one selection signal; and a comparator that generates a pulse of the interpolated pulse signal when the hold value of the register and the count value of the second counter match each other; The motor drive device according to claim 2, further comprising: a switching signal generation unit that determines whether or not the rotation speed of the motor is constant and generates the switching signal.   The switching signal generation unit counts the number of pulses of the second interpolated pulse signal and clears the count value at the pulse edge of the composite Hall signal; and the fifth counter at the pulse edge of the composite Hall signal A third register that holds the count value; and a determination unit that determines whether the hold value of the third register is within a predetermined target range and generates the switching signal. The motor driving device according to claim 4.   The switching signal generation unit is configured to generate an FG signal having a frequency corresponding to the rotational speed of the motor; and determine whether the frequency of the FG signal is within a target range instructed by the microcomputer. 6. A motor drive according to claim 3, further comprising: a ready signal generating unit that returns a ready signal to the microcomputer, and using the ready signal as the switching signal. apparatus.   An electric apparatus comprising a motor and a motor drive device that performs drive control of the motor, wherein the motor drive device according to any one of claims 1 to 7 is provided as the motor drive device. Electrical equipment characterized by comprising.

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