JP2009141214A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to provide a semiconductor device having a small parasitic resistance in a source / drain region and a method for manufacturing the same.
A method of manufacturing a semiconductor device of the present invention includes a step of forming a gate portion on a Si layer, a step of introducing As into a Si layer sandwiching the gate portion, and a Si layer into which As has been introduced. A step of depositing a Ni layer, a step of reacting the Ni layer and the Si layer using heat treatment to form a first silicide layer, and segregating As at the interface between the first silicide layer and the Si layer; A step of introducing a Pt element into the first silicide layer and a heat treatment are used to diffuse the Pt element to the Si layer to form a second silicide layer between the first silicide layer and the Si layer. And a step of segregating As at the interface between the silicide layer and the Si layer.
[Selection] Figure 1

Description

  The present invention relates to a field effect transistor and a method for manufacturing the same.

  Silicon super integrated circuits (LSIs) are one of the fundamental technologies that will support the advanced information society in the future. In order to increase the functionality of integrated circuits, it is necessary to improve the performance of MISFET (Metal Insulator Semiconductor Field Effect Transistor), which is a component of the integrated circuit. Although device performance has basically been improved by proportional scaling (scaling), in recent years due to various physical limitations, not only device performance has been improved by ultra-miniaturization of the device, but also the operation of the device itself. Even in a difficult situation.

  One such physical limit is the problem of parasitic resistance in the source / drain regions. Generally, the source / drain region includes a silicide layer (for example, a NiSi layer), a high-concentration impurity layer, and an extension diffusion layer formed in the periphery thereof. A Schottky junction is formed between the silicide layer, the high concentration impurity layer, and the extension diffusion layer. The parasitic resistance of the source / drain region is decomposed into three parts: the resistance caused by the bulk film, that is, the resistance of the silicide layer itself (Rsh), the resistance of the high-concentration impurity layer (Rd), and the interface resistance (Rc) of the junction. Is done.

  The interfacial resistance (Rc) is the largest of the three types and does not decrease according to the proportional reduction law. Therefore, it is most important to reduce this. In order to reduce the interface resistance (Rc), it is important to effectively reduce the Schottky Barrier Height (SBH) and the electron tunnel distance at the junction interface. In order to realize this, it is effective to increase the concentration of impurities at the interface portion between the silicide layer and the high concentration impurity layer.

As a process for realizing this, an impurity segregation process is known (see Patent Document 1 and Non-Patent Document 1). In the impurity segregation process, an impurity layer formed by ion implantation before silicide formation is segregated at the interface between the silicide layer and the Si layer at the time of silicide formation, and a high concentration impurity segregation layer is formed at this interface. About 1 × 10 ²⁰ cm ^-3, according to Patent Document 1, although the concentration of As 2 × 10 about ²⁰ cm ^-3 According to Non-Patent Document 1 is realized, in recent years, with further enrichment is required Yes.

  By the way, for both n-type and p-type MISFETs, it is disclosed that a PtSi layer is interposed between the NiSi layer and the Si layer in order to flatten the NiSi layer / Si layer interface (see Patent Document 2). . However, the Schottky Barrier Height (SBH) of the PtSi layer is as small as about 0.23 eV for the p-type Si layer, but as large as about 0.87 eV for the n-type Si layer. Therefore, the interface resistance (Rc) of the n-type MISFET increases as it is.

Therefore, in Patent Document 2, the silicide layer of both the n-type and p-type MISFETs is a stacked layer of NiSi layer / PtSi layer, and an impurity segregation process is used for the n-type MISFET, and a steep nanometer is formed at the PtSi layer / Si layer interface. It also discloses forming an N-type impurity high concentration region. However, Patent Document 2 uses a method of forming a silicide after sequentially stacking a Pt layer and an Ni layer on a Si layer, and segregates at the PtSi layer / Si layer interface as in Patent Document 1 and Non-Patent Document 1. The impurity concentration to be performed was still insufficient.
US Pat. No. 7,119,402 US Patent Application Publication No. 2006/0038229 T.A. Yamauchi et al. , Extended Abstracts of SSDM, pp. 908-909 (2005)

  In view of the above circumstances, an object of the present invention is to provide a semiconductor device having a low parasitic resistance in a source / drain region and a method for manufacturing the same.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate portion on a Si layer, a step of introducing As into the Si layer sandwiching the gate portion, and a Ni layer being deposited on the Si layer into which As has been introduced. Forming a first silicide layer by reacting the Ni layer and the Si layer using heat treatment, segregating As at the interface between the first silicide layer and the Si layer, and the first silicide layer. A step of introducing a Pt element therein and a heat treatment to diffuse the Pt element to the Si layer to form a second silicide layer between the first silicide layer and the Si layer, and the second silicide layer and the Si layer; And a step of segregating As at the interface with the layer.

  The semiconductor device of the present invention is formed on a Si layer, a gate insulating film formed on the Si layer, a gate electrode formed on the gate insulating film, and a Si layer surface sandwiching the gate electrode. Formed between the first silicide layer having Pt and Pt elements, the first silicide layer and the Si layer, and formed between the second silicide layer having Ni silicide and Pt silicide, and the second silicide layer and the Si layer. And an n-type MIS transistor having an Si interface layer having As.

  The semiconductor device of the present invention includes a Si layer, a first gate insulating film formed on the Si layer, a first gate electrode formed on the first gate insulating film, and an Si sandwiching the first gate electrode. A first silicide layer having Ni silicide and Pt elements formed on the surface of the layer; a second silicide layer having Ni silicide and Pt silicide formed between the first silicide layer and the Si layer; and a second silicide layer. N-type MIS transistor formed between the Si layer and the Si interfacial layer having As, a second gate insulating film formed on the Si layer, and a second gate insulating film The second gate electrode, formed on the surface of the Si layer sandwiching the second gate electrode, formed between the third silicide layer having Ni silicide and Pt element, and between the third silicide layer and the Si layer, Characterized in that it comprises a p-type MIS transistor having a fourth silicide layer having id and Pt silicide.

  The present invention can provide a semiconductor device having a small parasitic resistance in the source / drain region and a method for manufacturing the same.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol shall be attached | subjected to a common structure through embodiment, and the overlapping description is abbreviate | omitted. Each figure is a schematic diagram for promoting explanation and understanding of the invention, and its shape, dimensions, ratio, and the like are different from those of an actual device. However, these are in consideration of the following explanation and known techniques. The design can be changed as appropriate.

  In each embodiment, a planar type single gate MISFET and a FIN type double gate MISFET will be described, but the present invention can be applied to all MISFETs. Therefore, for example, a planar double gate structure having gates above and below the channel region, a FIN trigate MISFET, and a thin line MISFET are also within the scope of the present invention.

  Also, the embodiments can be similarly applied to PROMs such as EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically EPROM), and flash memory. Furthermore, the present invention can also be applied to a memory, a logic circuit, and the like in which the above-described semiconductor elements are integrated, and a system LSI in which these are mixedly mounted on the same chip.

(Outline of the present invention)
The manufacturing method of the present embodiment is characterized by a two-stage impurity segregation process as shown in FIG. In the first stage segregation process, similar to Patent Document 1, the stacked structure of the Ni layer / impurity atom-containing Si layer is silicided, and at the same time, the impurity atoms are segregated on the Si layer side of the NiSi layer / Si layer interface. . Thereafter, a Pt element is introduced into the NiSi layer, and a second stage segregation process is performed. Here, the Pt element reaches the Si layer, and a silicide layer (for example, 1 nm to 5 nm) is newly formed. At the same time, impurity atoms further segregate on the Si layer side of the silicide layer / Si layer interface.

  This manufacturing method is particularly effective for As atoms, and high impurity segregation, that is, a large SBH modulation effect is obtained with respect to the n-type MISFET, so that reduction of interface resistance can be realized.

  First, the basic principle of the present invention will be briefly described using theoretical analysis results. As a method of first-principles calculation, a SP-GGA (Spin-Polarized Generalized Gradient Application) technique was adopted that exceeded the local density functional approximation and also considered spin polarization. Cut-offs for the wave function and the charge were 25 Ry (Rydberg: 1 Ry≈13.6 eV) and 196 Ry, respectively. The k points (lattice points in the wave number space) were calculated as 8 points.

  For NiSi, PtSi, and Si, the same calculation is performed for a unit cell including 64 atoms, and a comparison is made. The generation energy when impurities enter NiSi, PtSi, and Si is defined by the following equation.

1. Generation energy when an impurity atom enters the silicon lattice When the generation energy when an impurity atom enters between the silicon lattice is E _f ^Int ,
E _f ^Int = -E (Si64 cell structure including one impurity atom)
+ E (Si64 cell structure) + E (1 impurity atom in vacuum) (Formula 1A)
If the generation energy when an Si atom is replaced by an impurity atom is E _f ^Si , the Si atom coming out of the lattice point will return to bulk silicon again.
E _f ^Si = −E (Si63 cell structure including one impurity atom) −E (1 bulk Si atom)
+ E (Si64 cell structure) + E (1 impurity atom in vacuum) (Formula 1B)
2. Generation energy when impurity atoms enter NiSi lattice
If the generation energy when impurity atoms enter between the lattices of NiSi is E _f ^Int ,
E _f ^Int = −E (32 cell structures of NiSi each containing one impurity atom)
+ E (32 NiSi cell structures) + E (1 impurity atom in vacuum) (Formula 2A)
If the generation energy when the Si atom is replaced by an impurity atom is E _f ^Si , the Si atom coming out of the lattice point will return to bulk silicon again,
E _f ^Si = -E (cell structure in which each 32 Si atoms of NiSi are replaced by impurity atoms)
-E (one bulk Si atom)
+ E (32 NiSi cell structures) + E (1 impurity atom in vacuum) (Formula 2B)
Assuming that the generation energy when an Ni atom is substituted by an impurity atom is E _f ^Ni , the Ni atom emitted from the lattice point is combined with a bulk silicon atom to become a pair of NiSi,
E _f ^Ni = -E (cell structure in which one Ni atom is replaced by one impurity atom from 32 NiSi)
+ 31E (1 NiSi) + E (1 impurity atom in vacuum)
+ E (one bulk Si atom) (Formula 2C)
3. Generation energy when impurity atoms enter PtSi
It was considered in the same way as the generation energy when impurity atoms enter NiSi.

If the generation energy when an impurity atom enters between the lattices of PtSi is E _f ^Int ,
E _f ^Int = −E (32 cell structures each containing one impurity atom)
+ E (32 cell structures for each PtSi) + E (1 impurity atom in vacuum) (Formula 3A)
If the generation energy when an impurity atom is substituted for a Si atom is E _f ^Si ,
E _f ^Si = -E (PtSi cell structure with 32 Si atoms replaced by impurity atoms)
-E (one bulk Si atom)
+ E (32 PtSi cell structures) + E (1 impurity atom in vacuum) (Formula 3B)
Assuming that the generation energy when an impurity atom is substituted for a Pt atom is E _f ^Pt , it is assumed that the Pt atom emitted from the lattice point becomes a pair of PtSi by bonding with a bulk silicon atom.
E _f ^Pt = -E (cell structure in which one Pt atom is replaced by impurity atom from 32 PtSi)
+ 31E (1 PtSi) + E (1 impurity atom in vacuum)
+ E (one bulk Si atom) (Formula 3C)
The calculation results regarding the generated energy are summarized in FIG.

In general, the generated energy represents the energy difference between the final state and the initial state of the reaction, and it is considered that the higher the generated energy, the easier it is to be realized in an actual system. For example, as shown in FIG. 2C, in the calculation result when the B atom enters the Si lattice, E _f ^Si (5.19 eV) is larger than E _f ^Int (2.61 eV). B atoms are likely to enter Si substitution positions. Further, as shown in FIG. 2B, in the case of As atoms, since E _f ^Int (−0.61 eV) is a negative value, As atoms cannot normally enter interstitial positions, and most of them The As atom will enter the Si substitution position.

  Next, the generation energies when impurities enter NiSi, PtSi, and Si lattices are compared.

As shown in FIG. 2A, the Pt atoms introduced into the NiSi lattice have a substitution position (E _f ^Si = 5.24 eV, E _f ^Ni = 7) rather than the interstitial position (E _f ^Int = 4.12 eV). .15 eV) is more stable, and is most stable at the Ni substitution position (E _f ^Ni = 7.15 eV). This indicates that when Pt is introduced into the NiSi film and annealed, Pt is replaced with Ni and PtSi is formed.

  Furthermore, the inventors have already found that when an impurity atom having a large atomic radius such as Pt is introduced into the NiSi layer / Si layer interface, the impurity atom has a stable point at the Si side interface. This is because the strain energy at the NiSi layer / Si layer interface is relaxed by the entry of impurity atoms. For this reason, it is concluded that Pt is introduced into the NiSi layer / Si layer interface, and after annealing, a new PtSi layer is formed between the NiSi layer and the Si layer.

  When the As atom and the B atom are impurities, the most stable is the Si substitution position in any lattice of NiSi, PtSi, and Si (see FIGS. 2B and 2C). Next, the NiSi, PtSi, and Si lattices are compared at the Si substitution positions. In the case of As atoms, comparing the NiSi lattice (2.65 eV), the PtSi lattice (1.58 eV), and the Si lattice (2.33 eV), it can be seen that the NiSi lattice is the most stable, followed by the Si lattice. . Similarly, in the case of B atoms, the NiSi lattice and the Si lattice are stabilized in this order. These results indicate that As and B atoms are difficult to enter the PtSi lattice.

  Focusing on the difference in generated energy, as shown in FIG. 2B, in the case of As atoms, there is a large difference of about 1 eV between the Si substitution position of the NiSi lattice and the PtSi lattice. For this reason, it is considered that As atoms existing in the NiSi lattice are displaced from the PtSi lattice and moved to another stable point when the lattice changes from NiSi to PtSi.

  As atoms driven out of the PtSi lattice move between the lattices. At this time, the Si lattice (−0.61 eV) has higher generation energy than the NiSi lattice (−2.66 eV), and is easily moved. For this reason, As atoms are expelled to the interface on the Si layer side.

  FIG. 3 is a schematic diagram showing the behavior of atoms before and after the second-stage segregation process described above. Thus, it can be seen that the impurity atoms present on the NiSi layer side of the NiSi layer / Si layer stack are swept out to the Si layer side when a new PtSi layer is formed at the NiSi layer / Si layer interface. . In the present embodiment, this is referred to as an increase in the snow shoveling effect associated with the interface generation of the PtSi layer, or a two-stage snow shoveling effect. As a result, high impurity segregation is obtained at the Si layer side interface, a large SBH modulation effect is obtained, and the interface resistance can be reduced. This effect is particularly great for As atoms and n-type MISFETs.

  The semiconductor device of this embodiment will be described with reference to FIGS. FIG. 4 is a schematic cross-sectional view in the gate length direction of a MISFET showing an example of this embodiment. FIG. 5 is an enlarged view of the source / drain region of FIG.

  As shown in FIG. 4, an element isolation region is formed on the surface of a silicon semiconductor substrate, and the MISFET is surrounded by the element isolation region. This element isolation region is, for example, STI (Shallow Low Trench Isolation) in which a silicon oxide film is embedded. The MISFET includes a channel region on the surface of the silicon substrate, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film, and source / drain regions formed on both sides of the channel region. And a gate side wall insulating film formed on both sides of the gate insulating film and the gate electrode.

  As shown in FIG. 5, the source / drain regions are a first silicide layer (NiSi layer containing Pt element) formed on the surface of the silicon substrate, and a first silicide layer formed on the silicon substrate side from the first silicide layer. Two silicide layers (a layer in which NiSi and PtSi are mixed), a high concentration impurity layer (Si layer having a high impurity concentration) formed in an interface region on the silicon substrate side adjacent to the second silicide layer, and a high concentration impurity layer And a diffusion layer formed on the silicon substrate side.

  Both the first and second silicide layers have Ni and Pt as metal elements. Therefore, when the ratio Pt / (Ni + Pt) of Pt to the total amount of Ni and Pt is represented by x, the first and second silicide layers are two films having different x (see FIGS. 6 and 7).

  The overall thickness of the silicide layer is typically 20 nm. In the first silicide layer that is far from the Si interface and thick, the Pt concentration x1 is set to 0% to 5%. In the second silicide layer from the Si interface to about 1 nm to 5 nm (typically 3 nm), the Pt concentration x2 is set to a ratio of about 30% to 90%. Thus, the Pt concentration is low at a location far from the Si-side interface and high at a location close to it. When the average Pt concentration in the entire silicide layer is x3, it becomes 10% or less.

  Here, the upper limit value of x2 will be described. In the process of the present invention, it is assumed that a flat and steep interface is formed of NiSi / Si before introducing Pt. In general, lattice matching is important in order to obtain a flat interface between polycrystalline silicide and Si. NiSi has an orthorhombic MnP type crystal structure, and typical lattice constants are a = 0.518 nm, b = 0.334 nm, and c = 0.562 nm. It is known that the polycrystalline NiSi on Si is mostly oriented in the (010) plane. This is because the NiSi lattice constants of a = 0.518 nm and c = 0.562 nm are relatively close to the lattice constant of Si of 0.543 nm, and thus the lattice matching is good in this relation. Like NiSi, PtSi has a MnP type crystal structure, and the lattice constants are a = 0.559 nm, b = 0.360 nm, and c = 0.593 nm. The lattice constant of PtSi is larger than NiSi in all values of a, b, and c. Therefore, in the first silicide film of the present invention, the lattice constant increases in proportion to the Pt ratio. If all NiSi is replaced with PtSi at the NiSi layer / Si layer interface, the lattice energy of PtSi is large, so that the strain energy at the interface becomes large and the structure becomes unstable. That is, when PtSi having a large lattice constant is formed at a ratio of 100%, the original crystal orientation of NiSi (010) / Si (001) cannot be maintained. For example, PtSi (−101) / Si (001) , Another preferential orientation such as PtSi (−211) / Si (001) is formed. As a result, the flat and steep interface of NiSi / Si originally formed is disturbed, which is a major obstacle in forming an extremely shallow source / drain region. In order to obtain a stable interface structure, it is desirable to set the upper limit of x2 to about 50%. However, when the film thickness is reduced to about 1 nm, the strain energy of PtSi is reduced, so that the upper limit value of x2 can be set to about 90%. If the film thickness is extremely thinner than 1 nm, the properties of PtSi as a bulk may be impaired.

  However, in the manufacturing method according to the present invention, the first silicide layer is made to have a high concentration of PtSi due to the Pt diffusion phenomenon, so that a concentration distribution always exists in Pt in the film, and a 100% PtSi layer is realized at the interface. It is difficult. From this point of view, it is appropriate that the upper limit value of x2 is about 90%.

  The reason why the lower limit of x2 is about 30% will be described in the case where As is used as an impurity, which is more severe. Here, attention is paid to the Si substitution position in the generated energy shown in FIG. The difference between the case where As is put in Si (2.33) and the case where PtSi is put (1.58 eV) is taken, and ΔEf is 0.75 eV. Similarly, ΔEf = −0.32 eV when the difference between As (Si) (2.33) and NiSi (2.65 eV) is taken. When silicide is formed at the interface, the value of ΔEf needs to be positive in order for As to be swept out to the Si side. As shown in FIG. 8, when ΔEf = 0, x1 is approximately 30%, so the lower limit of x1 is 30%.

  The reason for setting x1 to 5% or less is to keep the resistivity of the first silicide layer as low as possible. The specific resistance of PtSi is 28 μΩcm to 35 μΩcm, which is about twice the specific resistance of NiSi.

  The layer thickness of the second silicide layer is optimized by the relative relationship with the layer thickness of the first silicide layer, and the specific resistance of these two layers is preferably a value comparable to that of NiSi. . This is because the specific resistance of PtSi is 28 μΩcm to 35 μΩcm, which is about twice the specific resistance of NiSi. Therefore, if the second silicide layer having a high Pt concentration is too thick, the specific resistance as a whole increases. . Considering that the typical thickness of the source / drain electrode made of NiSi is 20 nm, the thickness of the second silicide layer having a high Pt concentration is preferably 5 nm or less. Typically, it is about 3 nm.

  The Pt concentration in the first and second silicide layers and the thickness of both layers can be controlled by process conditions.

  In the above process, a basic order is necessary in which after the NiSi layer / Si layer interface containing impurities is formed, Pt is introduced into the NiSi layer and then annealed. As long as the order is not deviated, the detailed process conditions can be changed. Details will be described in the following embodiments.

(First embodiment)
In the first embodiment, a so-called complementary semiconductor device having an n-type MISFET and a p-type MISFET on a substrate and a manufacturing method thereof will be described.

  First, a manufacturing method of the semiconductor device of the first embodiment will be described with reference to FIGS.

As shown in FIG. 9, for example, an element isolation region (STI (Shallow) made of a silicon oxide film is formed on a p-type Si substrate having a plane orientation (100) plane doped with B (boron) by about 10 ¹⁵ atoms / cm ^3. Trench Isolation)). Thereafter, a first semiconductor region (p-well) and a second semiconductor region (n-well) are formed by impurity ion implantation with the element isolation region as a boundary. Through a process described later, an n-type MISFET is formed in the first semiconductor region (p-well), and a p-type MISFEST is formed in the second semiconductor region (n-well).

  Next, as shown in FIG. 10, a first gate insulating film made of, for example, a silicon oxide film is formed on the first semiconductor region with an EOT of about 1 nm. Similarly, on the second semiconductor region, for example, a second gate insulating film formed of a silicon oxide film is formed with an EOT of about 1 nm. The first gate insulating film and the second gate insulating film may be formed at the same time.

Of course, the first and second gate insulating films are not necessarily limited to the silicon oxide film, and an insulating film material (high dielectric constant insulating film) having a dielectric constant higher than that of the silicon oxide film can be applied. Specifically, for example, La ₂ O ₅ , La ₂ O ₃ , CeO ₂ , ZrO ₂ , HfO ₂ , SrTiO ₃ , PrO ₃ , LaAlO ₃ , Si ₃ N ₄ , Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ or the like can be applied. Alternatively, an insulating film in which nitrogen or fluorine is added to a silicon oxide film or a high dielectric constant insulating film can be applied. It is also possible to apply an insulating film in which the composition ratio of these compounds is changed or a composite film in which a plurality of insulating films are combined. It is also possible to apply an insulating film in which metal ions are added to silicon oxide, such as Zr silicate and Hf silicate.

  Then, a polysilicon film serving as a first gate electrode is deposited on the first gate insulating film by about 100 nm to 150 nm by a low pressure chemical vapor deposition (hereinafter also referred to as LP-CVD) method. Then, the first gate insulating film and the first gate electrode are patterned so as to have a gate length of about 30 nm or less by lithography techniques and etching techniques such as reactive ion etching (hereinafter also referred to as RIE). Similarly, a polysilicon film serving as a second gate electrode is deposited on the second gate insulating film by about 100 nm to 150 nm by the LP-CVD method. Then, the second gate insulating film and the second gate electrode are patterned so as to have a gate length of about 30 nm or less by lithography technique and etching technique such as RIE (see FIG. 11).

  The deposition of the polysilicon film and the pattern formation of the first gate insulating film and the first gate electrode, and the second gate insulating film and the second gate electrode are performed simultaneously in the n-type MISFET and the p-type MISFET. It does not matter. If necessary, post-oxidation of 1 to 2 nm is performed here.

  Similarly to the example of the gate insulating film, the material of the gate electrode is not limited to polysilicon, and a so-called metal gate material can be applied. Examples of the metal gate material include simple metals such as Ti, Ta, and W, nitrides, carbides, and oxides.

  Next, as shown in FIG. 12, a silicon nitride film is deposited by, for example, about 8 nm by the LP-CVD method, and then etched back by the RIE method, whereby the silicon nitride film is formed by the first gate electrode and the second gate electrode. Leave only on the side of the gate electrode. Thereby, a sidewall insulating film is formed.

Next, as shown in FIG. 13, the second semiconductor region is masked with a resist film by lithography (not shown), and As (arsenic) is ion-implanted using the gate electrode and the sidewall insulating film as a mask. Introduced in the semiconductor region. Thereby, for example, an n-type diffusion layer of about 1 × 10 ²¹ atoms / cm ³ is formed.

Next, as shown in FIG. 14, the first semiconductor region is masked with a resist film by lithography (not shown), and B (boron) is ion-implanted by ion implantation using the gate electrode and the sidewall insulating film as a mask. 2 is introduced into the semiconductor region. Thereby, for example, a p-type diffusion layer of about 1 × 10 ²⁰ atoms / cm ³ is formed.

  Next, as shown in FIG. 15, a Ni film having a thickness of about 10 nm is formed on the first semiconductor region by sputtering. That is, the Ni film is deposited in contact with the source / drain regions of both MISFETs.

  Thereafter, as shown in FIG. 16, as the first and second heat treatments, for example, RTA (Rapid Thermal Anneal) is sequentially performed at 350 ° C. for about 30 seconds, 500 ° C. for about 30 seconds, The surfaces of the first semiconductor region and the second semiconductor region are silicided to form a first silicide layer made of NiSi having a thickness of about 20 nm. At this time, the first gate silicide layer is also formed on the gate electrode. Thereafter, the unreacted excess Ni film is peeled off with a chemical solution.

  When the first silicide layer is formed, the diffusion layer is silicided so that As and B segregation layers of impurities are formed at the interface of the first silicide layer, that is, the NiSi layer / Si layer interface. .

  Here, it is desirable that the heat treatment during the Ni deposition is performed in two stages, and the first heat treatment is performed at a lower temperature than the second heat treatment. By making the temperature of the first heat treatment lower than the temperature of the second heat treatment, the first silicide layer undergoes an excessive thermal process, Ni in the first silicide layer is abnormally diffused, and junction leakage occurs. Can be prevented from increasing.

There are many phases in nickel silicide. Dinickel silicide (Ni ₂ Si) is formed at the lowest annealing temperature, and is formed in the order of nickel monosilicide (NiSi) and nickel disilicide (NiSi ₂ ) as the annealing temperature rises.

Of these, nickel monosilicide (NiSi) is preferred when applied to LSI. For this reason, in the second heat treatment, an annealing temperature sufficient to form nickel monosilicide (NiSi) is required. However, in the first heat treatment, nickel monosilicide (NiSi) may not be formed as the first silicide layer. In this case, in the first heat treatment, an annealing temperature for converting to dinickel silicide (Ni ₂ Si) that provides selectivity at the time of subsequent exfoliation of surplus Ni is given, and the second and third heat treatments later provide the first heat treatment. One silicide layer may be nickel monosilicide (NiSi).

  Next, as shown in FIG. 17, after the portions other than the first semiconductor region and the second semiconductor region are covered with a resist film (not shown), from the first semiconductor region and the second semiconductor region. , Pt atoms are ion-implanted. The Pt atoms are introduced into the first silicide layer.

  Thereafter, as the third heat treatment, annealing is performed at 500 ° C. for about 10 seconds, for example, by RTA. By this annealing, Pt atoms are diffused in the first silicide layer, and a second silicide layer in which NiSi and PtSi are mixed is formed near the interface between the first silicide layer / silicon layer junction formed in FIG. . As a result, the source and drain electrode portions of the MISFET of the first embodiment shown in FIG. 18 are formed.

  In the first embodiment, Pt atoms are introduced into the NiSi layer using ion implantation. The introduced Pt atoms are present in a relatively large amount in the NiSi crystal grains. On the other hand, in the NiSi layer, the present inventors have already found that impurity atoms exist in NiSi crystal grains. For this reason, when the ion implantation method is used, the impurity atoms present in the NiSi crystal grains can be physically pushed out with the diffusion of the Pt atoms during the third heat treatment. Therefore, the impurity concentration near the silicide interface can be further increased.

  The temperature of the third heat treatment is desirably 300 ° C. or higher and 550 ° C. or lower. Below this range, Pt monosilicide may not be formed or the concentration of the impurity segregation layer may not be sufficiently high. If the temperature range is exceeded, Ni in the first and second silicide layers may abnormally diffuse in the Si layer, which may increase junction leakage.

  Note that when the first semiconductor region and the second semiconductor region are silicided by the first heat treatment, the second heat treatment, or the third heat treatment described later, a region deeper than the depth of the diffusion layer before silicidation. It is desirable to silicide the first semiconductor region and the second semiconductor region. That is, it is desirable that the depth of the first second silicide layer to be finally formed is deeper than the depth of the diffusion layer immediately before the Ni film that is the first metal is deposited. This is because more As or B in the diffusion layer can be segregated at the interface between the first and second silicide layers and the semiconductor region with a steep concentration profile.

Further, it is desirable that the conditions for ion implantation of Pt atoms are set so that all of the Pt atoms immediately after the ion implantation are contained in the first silicide layer. This is because Pt atoms can be effectively diffused in the NiSi layer, and the impurity concentration of the impurity segregation layer on the Si layer side can be further increased. For example, the acceleration voltage of Pt ion implantation for the first silicide layer (NiSi) 20 nm is desirably 30 keV or less. The dose is optimized according to the desired PtSi film thickness described later. For example, when the thickness of the NiSi film formed as the first silicide layer is 20 nm and the thickness of the second silicide layer is to be 2 nm or less, the thickness of the silicide layer is different because the thickness is different by one digit. (Pt-containing NiSi). Here, since there are four Pt atoms in the PtSi unit cell (5.93 Å × 5.59 Å × 3.60 Å), the concentration is 8.4 × 10 ²¹ cm ⁻³ . Therefore, in order to produce the first silicide layer with a thickness of 2 nm, for example, ion implantation of Pt atoms may be performed with a dose amount of at least 1.68 × 10 ¹⁵ cm ⁻² . All of the implanted Pt does not need to enter the second silicide layer, and remains in the first silicide layer to have a Pt concentration of 5% or less.

  Here, the gate portion (gate insulating film and gate electrode) has been described using a gate first process in which the gate portion is formed before the source / drain region is formed. Of course, the gate portion is formed after the source / drain region is formed. A gate-last process may be used. In the gate last process, after forming the dummy gate portion, the source / drain regions are formed, and then the dummy gate portion is peeled off to create the gate portion.

  FIG. 18 is a cross-sectional view of a complementary semiconductor device showing an example of the first embodiment.

  As shown in FIG. 18, an n-type MISFET and a p-type MISFET are provided on a silicon semiconductor substrate. The n-type MISFET is formed in a p-well formed on a silicon substrate. The p-type MISFET is formed on an n-well formed on a silicon substrate. An element isolation region is formed at the boundary between the region where the n-type MISFET is formed and the region where the p-type MISFET is formed. This element isolation region is, for example, STI (Shallow Low Trench Isolation) in which a silicon oxide film is embedded.

  The n-type MISFET has a first channel region on the silicon substrate, a first gate insulating film formed on the first channel region, and a first gate insulating film formed on the first gate insulating film. A gate electrode; and a first source / drain region formed on both sides of the first channel region. The source / drain region has a source electrode and a drain electrode, an interface layer having a high concentration As formed in an interface region in contact with the source / drain electrode, and a diffusion layer. The source electrode and the drain electrode are formed by the first and second silicide layers described above. Side wall insulating films made of, for example, a silicon nitride film are formed on both side surfaces of the gate electrode.

The interface layer having a high concentration As has a concentration of 4 × 10 ²⁰ to 2 × 10 ²¹ atoms / cm ³ , for example.

  The p-type MISFET has a second channel region on the silicon substrate, a second gate insulating film formed on the second channel region, and a second gate insulating film formed on the first gate insulating film. A gate electrode; and second source / drain regions formed on both sides of the second channel region. The second source / drain region is the same as the n-type MISFET except that the interface layer having a high concentration As is replaced with B.

The interface layer having a high concentration B has a concentration of 4 × 10 ²⁰ to 2 × 10 ²¹ atoms / cm ³ , for example.

As described above, it is known that the As concentration at the NiSi / Si interface produced by the conventional impurity segregation process is 2.0 × 10 ²⁰ cm ⁻³ (see Non-Patent Document 2). On the other hand, when the two-stage snow removal effect occurs by the process of the present embodiment described above, the As concentration at the interface increases.

Further, the relationship between the interface resistance and the As concentration was calculated by the following equation 4.

The result is shown in FIG. If the As concentration at the interface is 4.0 × 10 ²⁰ cm ⁻³ , which is twice the current As concentration, the SBH is increased by the PtSi layer formed at the interface, but there is an effect that exceeds that. Resistance can be reduced.

In particular, if the As concentration at the interface is 7.0 × 10 ²⁰ cm ⁻³ , the interface resistance can be reduced to 1/5 or less of the current value, which is very useful industrially. As shown in FIG. 2, the generation energy when As atoms enter the PtSi lattice is about 1 eV higher than the case where As atoms enter the NiSi lattice. Therefore, under the silicidation temperature (500 ° C.), it is sufficiently possible to set the As concentration to 7.0 × 10 ²⁰ cm ⁻³ or more.

  As described above, SBH of PtSi is as small as about 0.23 eV with respect to p-type Si, and is well known as a promising electrode material for p-type MISFETs. However, since the present invention provides a high segregation effect even with respect to the impurity B, the interface resistance can be further reduced.

  Therefore, if the method of manufacturing the semiconductor device of the first embodiment is adopted, the interface resistance of the source / drain electrodes of the n-type MISFET and the p-type MISFET can be simultaneously reduced, and the CMIS structure semiconductor It becomes possible to realize high performance of the apparatus. Further, since the silicide layers having the same structure are used for the source / drain electrodes of the n-type MISFET and the p-type MISFET, an increase in the number of processes can be greatly suppressed as compared with the dual silicide.

(Modification of the first embodiment)
The semiconductor device and the semiconductor device manufacturing method according to the modification of the first embodiment are the same as those of the first embodiment except that each of the n-type MISFET and the p-type MISFET has an extension diffusion layer. It is the same as the manufacturing method of the apparatus.

FIG. 20 is a schematic cross-sectional view of a semiconductor device according to this modification. As shown in FIG. 20, the n-type MISFET has an As diffusion layer having an impurity concentration of about 1 × 10 ²⁰ atoms / cm ³ , for example. In addition, the p-type MISFET has, for example, an B diffusion layer having an impurity concentration of about 1 × 10 ²⁰ atoms / cm ³ .

  According to the semiconductor device and the manufacturing method of the semiconductor device of this modification, by adding the extension diffusion layer, in addition to the effects of the first embodiment, the characteristics of the MISFET are optimized, specifically, the short channel The effect that the optimization of the effect and the operating current becomes easy can be obtained.

(Second Embodiment)
As shown in FIG. 21, in the method of manufacturing the semiconductor device of the second embodiment, B ions are implanted into the second semiconductor region after forming the first silicide layer containing NiSi. Further, annealing is performed after ion implantation of B. This method is called an impurity post-coating process. The first embodiment is the same as the first embodiment except for the formation method of the first silicide (NiSi) and the impurity distribution characteristic of this method before forming the second silicide.

  According to the second embodiment, the interface resistance of the p-type MISFET can be further reduced as compared with the first embodiment.

  Conventional impurity segregation processes are useful for improving the performance of n-type MISFETs, but are not necessarily useful for improving the performance of p-type MISFETs. This is because B, which is a typical impurity of p-type Si, is incorporated into the NiSi film during silicidation, so that most of it is distributed in the NiSi film and the impurity concentration on the Si film side decreases. Yes (see Non-Patent Document 1). In order to reduce the interface resistance (Rc) of the p-type MISFET, a so-called impurity post-implantation process in which B ions are implanted after the NiSi layer is formed is effective.

  According to the impurity post-implantation process, when B is used as an impurity, the impurity concentration in the vicinity of the NiSi layer / Si layer interface can be increased, and as a result, SBH can be decreased. Therefore, this process is effective for realizing low resistance of the interface resistance (Rc) of the p-type MISFET.

  According to the second embodiment, the resistance of the interface resistance (Rc) of the p-type MISFET can be further reduced by combining the two-stage impurity segregation process and the impurity post-bake process.

(Third embodiment)
In the method of manufacturing a semiconductor device according to the third embodiment, as a method for introducing a Pt element into a first silicide layer (NiSi layer), a metal layer containing Pt is deposited on the first silicide layer instead of ion implantation. It is characterized by adopting a method of annealing after that. Other than this, the description is omitted because it is the same as the first embodiment.

  In the third embodiment, instead of the Pt ion implantation step shown in FIG. 17 in the first embodiment, a metal film containing Pt is deposited.

  Thereafter, the second silicide layer is diffused from the Pt-containing film through the crystal grains of the first silicide layer (NiSi layer) or through the crystal grain boundaries by annealing (third heat treatment) at 300 ° C. to 550 ° C. It is formed in the interface region between the NiSi layer and the Si layer.

  Note that the treatment temperature of the third heat treatment is preferably lower than the treatment temperatures of the first heat treatment and the second heat treatment. This is for suppressing Ni diffusion from the first silicide layer (NiSi layer) formed by the first heat treatment and suppressing an increase in junction leak. Moreover, it is also for suppressing that resistance of electrode itself increases by the composition change of NiSi. Furthermore, it is desirable that the temperature is low from the viewpoint of suppressing the extension of the diffusion layer in the channel direction and suppressing the deterioration of the transistor characteristics.

  However, in the step of depositing the Pt layer on the NiSi layer and then diffusing the Pt element into the NiSi film by annealing, the distribution of Pt becomes uneven due to the difference in crystallinity of the NiSi layer formed from the beginning. There is a possibility. For example, since a NiSi film on a Si (001) substrate is generally polycrystalline, a crystal grain boundary exists. It is conceivable that diffusion of Pt element occurs preferentially at this crystal grain boundary. However, by adjusting known film formation conditions, a NiSi film having large crystal grains can be produced, and diffusion at grain boundaries can be reduced. Therefore, even in the case of this embodiment, the impurity snow shoveling effect according to the present invention occurs.

  As a method for depositing the metal layer containing Pt on the NiSi layer, for example, sputtering, vacuum evaporation, metal CVD, or the like is used. By using a simple film formation method such as sputtering, there is an advantage that the process can be simplified as compared with the ion implantation of the first embodiment.

(Fourth embodiment)
The semiconductor device and the manufacturing method thereof according to the fourth embodiment, except that the first silicide layer (NiSi layer) and the second silicide layer (layer in which NiSi and PtSi are mixed) contain a Pt element that is not silicided. This is the same as in the first embodiment.

  In the semiconductor device according to the fourth embodiment, the Pt element in the atomic state exists in the crystal lattice of the first second silicide layer, and the Pt metal exists in the crystal grain boundary. For this reason, in the third heat treatment, a process at a lower temperature is possible, the versatility of the process is increased, and the process can be simplified.

(Fifth embodiment)
The manufacturing method of the semiconductor device of the fifth embodiment is the same as that of the first embodiment except that the third metal layer is included in the second silicide layer / Si layer interface of the n-type MISFET. .

  The third metal layer is made of a metal having a work function smaller than the silicon midgap, such as Er having a work function of about 3.5 eV, such as Y (yttrium: about 3.1 eV), Sr (strontium: about 2.59 eV, La (lanthanum: about 3.5 eV), Hf (hafnium: about 3.9 eV), Yb (ytterbium: about 2.9 eV), Al (aluminum: about 4.28 eV), In (indium: about 4 .12 eV) or the like, or a silicide thereof, or a mixture thereof, and is formed of a material having an effect of lowering SBH than PtSi with respect to n-type MISFET.

  As shown in FIG. 22 (a), after the NiSi layer / PtSi layer / Si layer is formed in the first embodiment, a film containing a metal element to be introduced is deposited and heat treatment is performed. The third metal layer is formed by introducing the metal element to the Si side interface through the grain boundary of the layer / PtSi layer. As a result, as shown in FIG. 22B, a low interface resistance (Rc) can be realized by the effect of band bending due to segregation at high concentration B and the synergistic effect of low SBH due to the third metal layer.

  In the fifth embodiment, contrary to the third embodiment, the crystal grain boundaries of the NiSi layer / PtSi layer are positively utilized. As described in the first embodiment, the manufacturing method of the present invention provides a high As impurity segregation effect in the Si layer of NiSi layer / PtSi layer / Si layer, but originally SBH of PtSi with respect to n-type Si is As large as about 0.87 eV. Therefore, in the present embodiment, a third metal layer that can be expected to have SBH lower than PtSi is introduced only at the interface as necessary.

(Sixth embodiment)
The semiconductor device and the manufacturing method of the semiconductor device of the sixth embodiment are the same as those of the first embodiment except that the n-type MISFET and the p-type MISFET constituting the semiconductor device are Fin-type MISFETs. Description is omitted.

  FIG. 23 is a perspective view of the semiconductor device according to the sixth embodiment.

  As shown in FIG. 23, the semiconductor device of this embodiment has, for example, a Fin-type n-type MISFET and a Fin-type p-type MISFET on a silicon semiconductor substrate.

  The n-type MISFET is formed on both sides of the first channel region between the source and drain electrodes made of NiSi layer / PtSi layer / Si layer and the As channel formed between the first channel region and the first silicide layer. It has an interface layer. The p-type MISFET has a B electrode formed on both sides of the second channel region, between the source and drain electrodes made of NiSi layer / PtSi layer / Si layer, and between the second channel region and the first silicide layer. It has a partial interface.

  The channel regions of the n-type MISFET and the p-type MISFET have a Fin shape perpendicular to the semiconductor substrate and have two opposing main surfaces. A gate insulating film is formed on each of the two main surfaces. A gate electrode is formed on the gate insulating film. As described above, the MISFET of the sixth embodiment is a Fin-type MISFET having a so-called double gate structure.

  In FIG. 23, one MISSSET has one Fin, but it goes without saying that one MISFET may have a plurality of MSFSETs.

  As a manufacturing method, the process of the first embodiment described above may be employed when forming the source / drain regions of the Fin-type MISFET.

  As mentioned above, although embodiment of this invention was described, this invention is not restricted to these, In the category of the summary of the invention as described in a claim, it can change variously. In addition, the present invention can be variously modified without departing from the scope of the invention in the implementation stage. Furthermore, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment.

The figure for demonstrating the manufacturing method of the source / drain area | region of the semiconductor device of this invention The figure which shows the production | generation energy when an impurity enters into the unit cell of NiSi, PtSi, and Si Diagram showing an example of atomic behavior before and after the second stage segregation process Schematic cross-sectional view showing an example of a semiconductor device of the present invention FIG. 4 is an enlarged view of the source / drain region shown in FIG. The figure for demonstrating Pt density | concentration of a 1st, 2nd silicide layer The figure for demonstrating Pt density | concentration of a 1st, 2nd silicide layer The figure which shows the production | generation energy when As enters in the unit cell of NiPtSi. Sectional schematic diagram which shows an example of the manufacturing process of the semiconductor device of 1st Embodiment Sectional schematic diagram which shows an example of the manufacturing process of the semiconductor device of 1st Embodiment Sectional schematic diagram which shows an example of the manufacturing process of the semiconductor device of 1st Embodiment Sectional schematic diagram which shows an example of the manufacturing process of the semiconductor device of 1st Embodiment Sectional schematic diagram which shows an example of the manufacturing process of the semiconductor device of 1st Embodiment Sectional schematic diagram which shows an example of the manufacturing process of the semiconductor device of 1st Embodiment Sectional schematic diagram which shows an example of the manufacturing process of the semiconductor device of 1st Embodiment Sectional schematic diagram which shows an example of the manufacturing process of the semiconductor device of 1st Embodiment Sectional schematic diagram which shows an example of the manufacturing process of the semiconductor device of 1st Embodiment Sectional schematic diagram showing an example of the semiconductor device of the first embodiment Diagram showing the relationship between interface resistance and As concentration Sectional model which shows the semiconductor device of the modification of 1st Embodiment The figure for demonstrating the manufacturing method of the source / drain area | region of the semiconductor device of 2nd Embodiment The figure for demonstrating the source / drain area | region of the semiconductor device of 5th Embodiment The perspective schematic diagram which shows an example of the semiconductor device of 6th Embodiment

Claims (6)

Forming a gate portion on the Si layer;
Introducing As into the Si layer sandwiching the gate portion;
Depositing a Ni layer on the Si layer introduced with As;
Forming a first silicide layer by reacting the Ni layer and the Si layer using heat treatment, and segregating the As at the interface between the first silicide layer and the Si layer;
Introducing a Pt element into the first silicide layer;
Using a heat treatment, the Pt element is diffused to the Si layer to form a second silicide layer between the first silicide layer and the Si layer, and an interface between the second silicide layer and the Si layer. And segregating the As to
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the Pt element is introduced into the first silicide layer by using an ion implantation method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the Pt element is introduced into the first silicide layer by depositing a Pt layer on the first silicide layer and performing a heat treatment. A Si layer;
A gate insulating film formed on the Si layer;
A gate electrode formed on the gate insulating film;
A first silicide layer formed on the surface of the Si layer sandwiching the gate electrode and having Ni silicide and a Pt element;
A second silicide layer formed between the first silicide layer and the Si layer and having Ni silicide and Pt silicide;
A semiconductor device comprising an n-type MIS transistor formed between the second silicide layer and the Si layer and comprising an Si interface layer having As.   The semiconductor device according to claim 4, wherein the first silicide layer and the second silicide layer have the same crystal orientation. A Si layer;
A first gate insulating film formed on the Si layer;
A first gate electrode formed on the first gate insulating film;
A first silicide layer formed on the surface of the Si layer sandwiching the first gate electrode and having Ni silicide and a Pt element;
A second silicide layer formed between the first silicide layer and the Si layer and having Ni silicide and Pt silicide;
An n-type MIS transistor formed between the second silicide layer and the Si layer and comprising an Si interface layer having As;
A second gate insulating film formed on the Si layer;
A second gate electrode formed on the second gate insulating film;
A third silicide layer formed on the surface of the Si layer sandwiching the second gate electrode and having Ni silicide and a Pt element;
And a p-type MIS transistor formed between the third silicide layer and the Si layer and including a fourth silicide layer having Ni silicide and Pt silicide.

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