JP2009141258A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an element area of a protection element without increasing a thickness of the protection element in a semiconductor device including a protection element connected to the protection target circuit in order to protect the protection target circuit from electrostatic discharge, and Provided is a semiconductor device including a protective element that can easily adjust a resistance value between an ESD signal application unit and a gate electrode.
A semiconductor device includes a protection target circuit, a pad, and a protection element. In the protection element 90, a first drain electrode 14, a source electrode 2, a second drain electrode 6, a gate electrode 4, and an element isolation trench 18 are formed. The drain electrodes 14 and 6 and the element isolation trench 18 are connected by an aluminum wiring 8. When an ESD signal is applied from the pad 10 to the first drain electrode 14, an ESD current flows from the first drain electrode 14 to the second drain electrode 6 via the element isolation trench 18.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device including a protection element connected to a circuit to be protected in order to protect a circuit to be protected from electrostatic discharge.

  An ESD protection element for protecting a circuit to be protected from electrostatic discharge (ESD) has been developed. For example, in a MOSFET type protection element, when a high voltage due to ESD is applied to the drain region connected to the circuit to be protected, the transistor is turned on, and the high voltage due to ESD is applied to the reference potential via the source region. Discharged.

FIG. 5 shows an example of a cross-sectional view of a conventional protection element 290. In the protection element 290, an n ⁺ -type first drain region 80 is formed on a part of the surface of the p-type semiconductor substrate 60. Silicide 66 is formed on part of the surface of the first drain region 80. The first drain region 80 is electrically connected to the drain electrode 78 formed on the semiconductor substrate 60 through the silicide 66. The first drain electrode 78 is connected to a protection target circuit to which a high voltage due to ESD (hereinafter referred to as an ESD signal) may be applied via a pad (not shown). An n ⁺ type source region 62 is formed on another part of the surface of the semiconductor substrate 60. Silicide 66 is formed on part of the surface of the source region 62. The source region 62 is electrically connected to the source electrode 64 formed on the semiconductor substrate 60 through the silicide 66. The source electrode 64 is connected to a reference potential (not shown). An n ⁺ -type second drain region 72 is formed between the first drain region 80 and the source region 62, which is another part of the surface of the semiconductor substrate 60. Silicide 66 is formed on part of the surface of the second drain region 72.

A gate insulating film 70 is formed on the surface of the semiconductor substrate 60 over the range between the second drain region 72 and the source region 62. A gate electrode 68 is formed on the surface of the gate insulating film 70. Although not shown, the gate electrode 68 is also connected to the reference potential. Under the gate insulating film 70, n ⁻ type extension regions 67a and 67b having a low impurity concentration are formed. The extension regions 67a and 67b are in contact with the source region 62 and the second drain region 72, respectively. In the silicide block region between the first drain region 80 and the second drain region 72, an n ⁻ type extension region 67c having a low impurity concentration is formed.

  When an ESD signal is applied to the first drain electrode 78 via the pad, a current generated by the ESD signal (hereinafter referred to as an ESD current) is supplied from the first drain region 80 to the second drain via the extension region 67c. Flow into region 78. When the ESD current reaches the second drain region 72, the voltage of the second drain region 72 rises and avalanche breakdown occurs. As a result, a parasitic transistor is formed between the second drain region 72 and the source region 62, and a current path is formed between the second drain region 72 and the source region 62. The ESD current reaching the source region 62 is discharged to the reference potential. When the ESD current is discharged, the voltage of the second drain region 72 decreases and the parasitic transistor is cut off. Such a protective element 290 is disclosed in Patent Document 1.

  If the resistance of the extension region 67c of the protection element 290 is too low, when an ESD signal is applied to the first drain region 78, an ESD current instantaneously flows to the second drain region 72, and the protection element 290 is destroyed. . In the protection element 290, it is necessary to maintain a distance from the gate electrode 64 to the first drain region 80 at a certain distance or more in order to ensure the ESD tolerance of the protection element 290. Therefore, a certain element area is required. On the other hand, when the resistance of the extension region 67c is too high, the breakdown voltage of the gate oxide film of the protection target circuit is exceeded before the parasitic transistor is turned on, and the protection target circuit is destroyed. Therefore, an appropriate resistance value for protecting both the protection target circuit and the protection element is provided between the first drain region 80 to which the ESD signal is applied and the second drain region 72 adjacent to the gate electrode 68. Need to be adjusted.

  In order to deal with such problems of the ESD protection element, a technique has been proposed that can reduce the element area and easily adjust the resistance value between the ESD signal application unit and the gate electrode. According to this technique, a ballast resistor is formed on the semiconductor substrate between the first drain region and the second drain region. A current path is formed from the first drain region to the second drain region via the ballast resistor. By adjusting the resistance value of the ballast resistor, the electric field strength between the first drain region and the second drain region is relaxed. Therefore, even if the distance between the first drain region and the second drain region is reduced, protection is achieved. The ESD tolerance of the element can be ensured. In addition, the resistance value between the first drain region and the second drain region can be easily adjusted by using the ballast resistor. Such a technique is disclosed in Patent Document 2.

Japanese Patent Laid-Open No. 2004-71799 JP-A-2005-191151

  However, according to the technique described above, the distance between the ESD signal application portion and the gate electrode can be reduced, but the thickness of the protection element is increased by forming the ballast resistor on the semiconductor substrate.

  The present invention solves the above problems. That is, in a semiconductor device including a protection element connected to a protection target circuit in order to protect the protection target circuit from electrostatic discharge, the element area of the protection element can be reduced without increasing the thickness of the protection element, and ESD It is an object of the present invention to provide a semiconductor device including a protective element that can easily adjust a resistance value between a signal applying unit and a gate electrode.

The present invention relates to a semiconductor device including a protection element connected to a protection target circuit in order to protect the protection target circuit from electrostatic discharge. The circuit to be protected and the protection element are connected in parallel to a wiring to which an ESD signal may be applied.
In the semiconductor device of the present invention, the protection element includes the second conductivity type well region formed in the semiconductor substrate.
The semiconductor device according to the present invention includes a first drain region of a first conductivity type that is formed on a part of the surface of the well region, is connected to the circuit to be protected, and is applied with a voltage due to electrostatic discharge. ing. In addition, a source region of a first conductivity type is provided which is formed on another part of the surface of the well region and connected to a reference potential. Furthermore, a second drain region of the first conductivity type formed on the surface of the well region located between the first drain region and the source region is provided. In addition, a gate electrode is provided which is opposed to the surface of the well region in a range extending from the second drain region to the source region via an insulating film and connected to a reference potential. The wiring connected to the reference potential from the source region and the wiring connected to the reference potential from the gate electrode may be conductive or may not be conductive.
The semiconductor device of the present invention further includes an element isolation trench which is formed on the outer periphery of the well region, has a wall surface covered with an insulating film and is filled with a conductive material. The element isolation trench is formed on the outer periphery of the well region so as to surround all of the source region, the gate electrode, the first drain region, and the second drain region. The conductive material filled in the element isolation trench may be, for example, a conductive material having a certain resistance value, or a conductive material whose resistance value is changed depending on the impurity concentration.
In the protective element formed in the semiconductor device of the present invention, the first drain region and the second drain region are electrically connected via the conductive material filled in the element isolation trench. The drain region and the element isolation trench are connected by, for example, metal wiring. A conduction path (hereinafter referred to as a conduction path) that electrically connects the first drain region and the second drain region passes through the element isolation trench by a certain distance. The conduction path may be connected to any position on the first drain region, and may be connected to any position on the source region. The number of conduction paths is not limited to one. Multiple lines may be formed.

According to the semiconductor device of the present invention, when an ESD signal is applied to the first drain region, a current path that travels through the conduction path from the first drain region toward the second drain region is formed. By adjusting the resistance value of the conduction path, the electric field concentration on the first drain region is alleviated. Therefore, even if the distance between the first drain region and the second drain region is reduced, the ESD resistance of the protective element is ensured. can do. The element area of the protection element can be reduced. Since the drain region and the element isolation trench are connected by a thin metal wiring or the like, the thickness of the protective element does not increase.
Further, according to the semiconductor device of the present invention, the resistance value of the conduction path can be easily adjusted by changing the resistance value of the element isolation trench, the number of conduction paths, the connection position of the wiring connected to the conduction path, and the like. Can do.

  In the semiconductor device of the present invention, a plurality of element isolation trenches are formed in multiples on the outer periphery of the protection element, and the conduction paths passing through the element isolation trenches are parallel between the first drain region and the second drain region. It may be formed. For example, when two element isolation trenches are formed, a conduction path passing through the two element isolation trenches is formed in parallel between the first drain region and the second drain region.

  According to the semiconductor device described above, since the plurality of element isolation trenches are used as the conduction paths, the total resistance value of the conduction paths can be adjusted using the plurality of element isolation trenches. The adjustment accuracy of the resistance value of the conduction path can be improved. In addition, since a plurality of conduction paths through the element isolation trench are formed, the heat generated by the ESD current flowing through the element isolation trench is easily dispersed. It is also possible to improve the thermal resistance of the protective element.

  According to the present invention, in a semiconductor device including a protection element connected to a protection target circuit in order to protect the protection target circuit from electrostatic discharge, the element area of the protection element is reduced without increasing the thickness of the protection element. be able to. In addition, the resistance value between the ESD signal applying portion and the gate electrode in the protective element can be easily adjusted.

Preferred features of the embodiments described below are listed.
(First feature) The wiring material connecting the conductive paths is made of the same material as the electrode metal.

(First embodiment)
FIG. 1 shows a schematic plan view of a semiconductor device 100 according to the first embodiment of the present invention. The semiconductor device 100 includes a protection target circuit 12 to be protected, a pad 10 to which an ESD signal may be applied, and a protection element 90 for protecting the protection target circuit. The protection target circuit 12 and the protection element 90 are connected in parallel to the pad 10.
As shown in FIGS. 1 and 2, the protection element 90 is formed inside a p-type well region 40 formed on the surface of an active layer (n-type silicon layer) of the SOI substrate 35. The first drain electrode 14 and the source electrode 2 are formed on part of the surface of the well region 40. A second drain electrode 6 is formed between the first drain electrode 14 and the source electrode 2. The first drain electrode 14 is connected to the pad 10 and the protection target circuit 12, and an ESD signal may be applied to the first drain electrode 14 from the pad 10. A gate electrode 4 is formed between the second drain electrode 6 and the source electrode 2. Each of the gate electrode 4 and the source electrode 2 is connected to a reference potential 24. Each electrode is made of aluminum.

A p ⁺ -type guard ring 22 is formed on the outer periphery of the protection element 90 so as to surround the first drain electrode 14, the second drain electrode 6, the source electrode 2, and the gate electrode 4. The guard ring 22 is formed inside the well region 40. On the outer periphery of the guard ring 22, an element isolation trench 18 that goes around the outer periphery of the protective element 90 is formed. The element isolation trench 18 makes a round around the outer periphery of the well region 40. The first drain electrode 14 and the element isolation trench 18 are connected by an aluminum wiring 8. The element isolation trench 18 and the second drain electrode 6 are also connected by the aluminum wiring 8. Reference numeral 16 indicates an insulating film formed on the surface of the protection element 90. The space from the surface of the guard ring 22 to the surface of the element isolation trench 18 is actually covered with the insulating film 16, but in FIG. 1, for the sake of clarity, the guard ring 22 and the element isolation trench 18 are interposed between them. The well region 40 is shown by a solid line.

FIG. 2 is a cross-sectional view taken along the line II-II of the protection element 90 in FIG. The protection element 90 is formed in the SOI substrate 35. The SOI substrate 35 includes silicon substrates 30 and 34 and an insulating layer 32. The silicon substrate 34 is n-type and is used for an active layer.
In the protection element 90, a p-type well region 40 formed in the SOI substrate 35 is formed. An n ⁺ -type first drain region 50 is formed on a part of the surface of the well region 40. A first drain electrode 14 is formed on the surface of the first drain region 50. On the other part of the surface of the well region 40, an n ⁺ -type source region 44 is formed. A source electrode 2 is formed on the surface of the source region 44. On the surface of the well region 40 located between the first drain region 50 and the source region 44, an n ⁺ -type second drain region 48 is formed. A second drain electrode 6 is formed on the surface of the second drain region 48. A space between the first drain region 50 and the second drain region 48 is covered with an insulating film 16.

In the protection element 90, the gate insulating film 46 is formed on the surface of the well region 40 in a range extending from the second drain region 48 and the source region 44. A gate electrode 4 is formed on the surface of the gate insulating film 46. The surface of the protective element 90 is covered with the insulating film 16 except for the area where the electrodes are formed.
A guard ring 22 is formed inside the outer periphery of the well region 40 so as to go around the inner periphery of the well region 40. On the outer periphery of the well region 40, an element isolation trench 18 that makes a round around the outer periphery of the well region 40 is formed. The element isolation trench 18 includes a trench insulating film 36 that covers the wall surface of the trench, and polysilicon 38 that is filled therein. The polysilicon 38 contains n-type impurities. The resistance value of the polysilicon 38 can be changed depending on the concentration of the implanted impurity.

In the semiconductor device 100, when an ESD signal is transmitted to the pad 10, the ESD signal is applied to the first drain electrode 14 of the protection element 90. FIG. 3 shows a breakdown waveform of the protection element 90 when an ESD signal is applied to the protection element 90. I _d indicates the drain current. V _d represents the drain voltage. V ₁ indicates a boundary with the operation region of the protection target circuit 12. V ₂ indicates the breakdown voltage of the gate oxide film of the protection target circuit 12. When an ESD signal is applied to the first drain region 50, the voltage of the first drain region 50 increases. When the voltage of the first drain region 50 increases, a large ESD current flows from the first drain region 50 to the second drain region 48 via the conduction path, and the potential of the second drain region 48 increases. When the potential of the first drain electrode 14 exceeds V _d1 , an avalanche breakdown occurs at the pn junction between the second drain region 48 and the channel region, and a drain current starts to flow (a in the figure). Then, the potential of the p-type well region 40 rises, and when the potential rises to a predetermined potential difference with respect to the potential of the guard ring 22, the pn junction between the channel region and the source region 44 is forward-biased, A snapback phenomenon occurs. As a large current flows, the drain voltage decreases (b in the figure).

When a large ESD current flows through the second drain region 48, the voltage of the second drain region 48 rises (c in the figure). At this time, if the resistance value between the first drain region 50 and the second drain region 48 is too low, an ESD current instantaneously flows through the second drain region 48, so that the protective element 90 is destroyed (in the drawing). A). If the resistance value between the first drain region 50 and the second drain region 48 is too high, exceeds the breakdown voltage V ₂ of the gate oxide film excessive ESD current flows through the protection target circuit 12, the protected circuit 12 gate oxide films cannot be protected (B in the figure).

  In the protection element 90, two conduction paths that pass through the element isolation trench are formed. By adjusting the resistance value of the conduction path, the electric field concentration on the first drain region 50 is alleviated. Therefore, even if the distance between the first drain region 50 and the second drain region 48 is reduced, the ESD resistance is ensured. can do. The element area of the protection element 90 can be reduced. Since the drain region and the element isolation trench are connected by the thin aluminum wiring 8, the thickness of the protective element 90 does not increase.

  In the protection element 90, the resistance value of the second current path can be adjusted by changing the impurity concentration of the element isolation trench 18. Also, the resistance value of the conduction path can be adjusted by changing the number of conduction paths. Further, the resistance value of the conduction path can be adjusted also by changing the connection position of the aluminum wiring 8 connecting the drain regions 50 and 48 and the element isolation trench 18. In the protection element 90, the resistance value of the conduction path can be easily adjusted according to the thickness of the gate oxide film of the circuit to be protected.

Further, in the protection element 90, since two conduction paths that pass through the element isolation trench 18 are formed, the generation of heat due to the ESD current flowing between the two conduction paths is dispersed. The thermal resistance of the protection element 90 can also be improved.
Furthermore, in the protective element 90, since the conduction path is connected using the aluminum wiring 8 made of the same material as the electrode metal, the conduction path can be easily formed. A conduction path can be formed by an existing manufacturing process.

  FIG. 4 shows a schematic plan view of a semiconductor device 200 according to the second embodiment of the present invention. The semiconductor device 200 has the same structure as the semiconductor device 100 in which the element isolation trench 19 is further formed on the outer periphery of the element isolation trench 18 of the protection element 90. Portions other than the element isolation trench 19 are the same as the structure of the semiconductor device 100.

  In the protection element 190 of the conductor device 200, two conduction paths that pass through the two element isolation trenches 18 and 19 are formed in parallel between the first drain region and the second drain region. In the protective element 190, the resistance value of the conduction path can be adjusted by adjusting the resistance values of the two conduction paths. The adjustment accuracy of the resistance value of the conduction path can be increased. Since the ESD current flows through four locations in the element isolation trench, the heat generated by the ESD current is more easily dispersed than the semiconductor device 100. It is also possible to improve the thermal resistance of the protective element.

As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

1 is a schematic plan view of a semiconductor device 100 of the present invention which is a first embodiment. Sectional drawing of the II-II cross section of FIG. 1 is shown. 6 shows a breakdown waveform when an ESD signal is applied to the semiconductor device 100. The typical top view of the semiconductor device 200 of this invention which is 2nd Example is shown. A cross-sectional view of a conventional protection element 290 is shown.

Explanation of symbols

2, 64: source electrode 4, 68: gate electrode 6: second drain electrode 8: aluminum wiring 10: pad 12: protection target circuit 14, 78: first drain electrode 16, 74: insulating film 18, 19: element isolation Trench 22: Guard ring 24: Reference potential 30, 34: Silicon substrate 32: Insulating layer 35: SOI substrate 36: Trench insulating film 38: Polysilicon (conductive material)
40: well region 66: silicide 44: source region 46, 70: gate insulating film 48, 72: second drain region 50, 80: first drain region 60: semiconductor substrates 67a, 67b, 67c: extension regions 90, 190: Protection element 100, 200: Semiconductor device 290: Conventional protection element

Claims (2)

A semiconductor device including a protection element connected to a protection target circuit to protect the protection target circuit from electrostatic discharge.
A second conductivity type well region formed in the semiconductor substrate;
A first drain region of a first conductivity type formed on a part of the surface of the well region, connected to the circuit to be protected and applied with a voltage due to the electrostatic discharge;
A source region of a first conductivity type formed on another part of the surface of the well region and connected to a reference potential;
A second drain region of a first conductivity type formed on a surface of the well region located between the first drain region and the source region;
A gate electrode facing the surface of the well region in a range extending from the second drain region and the source region via an insulating film and connected to the reference potential;
It is formed on the outer periphery of the well region, and includes an element isolation trench in which the wall surface is covered with an insulating film and the inside is filled with a conductive material,
The semiconductor device, wherein the first drain region and the second drain region are electrically connected through a conductive material filled in the element isolation trench.   The element isolation trench is formed in multiple, and a conduction path passing through each element isolation trench is formed in parallel between the first drain region and the second drain region. 1. A semiconductor device.

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