JP2009141071A - Semiconductor element for electrostatic protection - Google Patents

Abstract

An object of the present invention is to provide an electrostatic protection semiconductor element with improved surge resistance without increasing the area.
[Solution]
The element region is completely isolated from other elements by the trench-shaped trench insulating film 5 and the polysilicon film 11. A Locos oxide film 12 is formed on the element region by a thermal oxidation process. An interlayer insulating film 13 is formed on the Locos oxide layer 12, and a collector electrode 14 penetrating the interlayer insulating film 13 is formed. The base electrode 15 and the emitter electrode 16 are connected. A trench bias electrode 17 is connected to the polysilicon film 11, and a negative bias is applied to the trench bias electrode 17 from a power source 18. Due to this negative bias, holes are unevenly distributed in the n + -type buried region 3 and the n-type semiconductor layer 4 close to the trench insulating film 5, so that the center of the electron flow is not only the center of the pn junction, but also the trench insulating film 5 Shift to the side.
[Selection] Figure 1

Description

  The present invention relates to an electrostatic protection semiconductor element that is connected to input terminals of other transistor circuits and integrated circuits and protects them from static electricity.

  Conventionally, a composite IC in which a digital circuit, an analog circuit, a power element and the like are mounted together is used as an IC (Integrated Circuit) for automobiles. Such a composite IC includes a bipolar, a lateral MOS (Metal Oxide Semiconductor) transistor, a CMOS (Complementary MOS) transistor, and the like, and is required to operate normally in a severe vehicle environment where surge noise is applied. It is manufactured by an SOI (Silicon On Insulator) substrate in which circuits are completely insulated and separated by an insulation separation technique.

  In addition, in a composite IC for automobiles, a demand for a tolerance (surge tolerance) against ESD (Electrostatic-Discharge) is severe, and a high ESD tolerance guarantee of 10 KV to 15 KV is required. As the ESD protection element, a transistor element designed based on a device constituting the composite IC is used.

  Such a transistor as an ESD protection element is often used as a clamp transistor. The overvoltage of the clamp transistor results in an avalanche current from the collector to the base, and the forward bias of the base emitter further increases the collector current, resulting in a condition called snapback.

By utilizing this snapback characteristic, the clamp voltage of the clamp transistor at the time of ESD can be lowered. Therefore, an ESD protection element capable of preventing the risk of gate breakdown of a CMOS element or the like constituting an internal circuit to be protected at the time of ESD protection operation. (For example, refer to Patent Document 1).
JP 2007-194509 A

  By the way, in a transistor as an ESD protection element, a buried layer having a high impurity concentration is used as a current path in order to improve surge resistance.

  However, since the surge current does not flow with a uniform width at the pn junction at the boundary between the buried layer and the drain, but flows in a biased manner toward the center of the width of the emitter region, a very small part of the pn junction serves as a heat source. There has been a problem of device destruction.

  Further, the current can be dispersed by increasing the area of the pn junction, thereby improving the surge withstand capability. However, increasing the area causes a decrease in productivity, leading to an increase in cost. .

  Therefore, an object of the present invention is to provide a semiconductor element for electrostatic protection with improved surge resistance without increasing the area.

  The semiconductor element for electrostatic protection according to one aspect of the present invention has a periphery and a bottom surface partitioned by a side surface insulating film including a trench insulating film and a polysilicon film, and a bottom surface insulating film, and is electrically isolated from other elements. In the electrostatic protection semiconductor device for preventing electrostatic breakdown of other devices, the first conductivity type buried region formed on the bottom surface insulating film, the buried region and the buried region, A first conductivity type semiconductor region having a carrier concentration lower than that of the buried region, a first conductivity type collector region formed in a surface portion of the semiconductor region, and a surface portion of the semiconductor region spaced apart from the collector region And a first conductivity type emitter region formed on a surface portion of the second conductivity type base region, and the polysilicon film includes an inner region of the semiconductor region. Decimals of Potential polarity is applied, which may attract Yaria.

  In addition, the potential applied to the polysilicon film is such that the majority carrier in the semiconductor region is combined with the fractional carrier so that the heat generation temperature at the boundary between the base region and the buried region is higher than the melting point of silicon. You may set so that it may become low.

  The potential applied to the polysilicon film may be a bias lower than the breakdown voltage of the trench insulating film.

  According to the present invention, it is possible to provide a specific effect that it is possible to provide an electrostatic protection semiconductor element with improved surge resistance without increasing the area.

  Hereinafter, embodiments to which the semiconductor element for electrostatic protection of the present invention is applied will be described.

  1A and 1B are diagrams showing the structure of a semiconductor element for electrostatic protection according to the present embodiment, where FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along line AA in FIG.

  As shown in FIG. 1B, a buried insulating film 2, an n + -type buried region 3, and an n-type semiconductor layer 4 are formed on a p-type semiconductor substrate 1. FIG. 1 shows only one electrostatic protection semiconductor element. The element region of the electrostatic protection semiconductor element is partitioned by a trench insulating film 5 formed in a side trench, and is insulated from other elements to be protected from static electricity by the trench insulating film 5 and the buried insulating film 2. It is separated.

The n + type buried region 3 is a high electron concentration n + type buried region 3 formed in parallel to the buried insulating film 2 of the n type semiconductor layer 4 and is implanted with impurities (typically phosphine (P)). Therefore, the impurity concentration is set to about 1 × 10 ²⁰ / cm ³ .

The n-type semiconductor layer 4 is a semiconductor layer whose impurity concentration is set to about 1 × 10 ¹⁵ / cm ³ by implanting impurities (typically phosphine (P)).

The element region is formed in the n + type buried region 3 and the n type semiconductor layer 4, and an n + type collector sink region 6 and a p type base sink region 7 are formed in the element region. The n + -type collector sink region 6 has an impurity concentration set to about 1 × 10 ²⁰ / cm ³ by injecting impurities (typically phosphine (P)) from the surface of the n-type semiconductor layer 4. . The p-type base sink region 7 is a base sink region whose conductivity type is changed to p-type by injecting impurities (typically boron (B)) from the surface of the n-type semiconductor layer 4. . The impurity implantation degree of the p-type base sink region 7 is set to about 1 × 10 ¹⁷ / cm ³ .

  A high electron concentration n + collector region 8 is formed on the surface of the n + collector sink region 6, and a high electron concentration n + emitter region 9 is formed on the surface of the p type base sink region 7. A high hole concentration p + -type base region 10 is formed with a gap therebetween.

The n + -type collector region 8 and the n + -type emitter region 9 both have an impurity concentration of 1 × 10 ²⁰ by injecting impurities (typically phosphine (P)) from the surface of the n + -type collector sink region 6. / Cm ³ or so.

  The n + type buried region 3 and the n + type collector region 8 are connected by an n + type collector sink region 6 with a low resistance.

  The p-type base sink region 7 includes the n + -type emitter region 9 and the p + -type base region 10 at the surface portion, and is connected to the n + -type buried region 3 at the bottom surface portion.

  The element region having such a configuration is completely insulated and isolated from other elements by the trench-shaped trench insulating film 5 and the polysilicon film 11.

  A Locos oxide film 12 is formed on the element region by thermal oxidation, and an interlayer insulating film 13 is formed on the Locos oxide layer 12.

  The Locos oxide layer 12 is not formed on the n + -type collector region 8, the n + -type emitter region 9, and the p + -type base region 10, but the n + -type collector region 8 and the n + -type emitter region 9. , And p + -type base region 10 are connected to collector electrode 14, base electrode 15, and emitter electrode 16 that penetrate interlayer insulating film 13.

  In addition, a trench bias electrode 17 that penetrates the Locos oxide layer 12 and the interlayer insulating film 13 is connected to the polysilicon film 11. A power source 18 is connected to the trench bias electrode 17 so that a negative bias Vtrench is applied.

  The electrostatic protection semiconductor element of the present embodiment having the above-described cross-sectional structure has a structure as shown in FIG. 1A in plan view, and the Locos oxide layer 12 surrounded by the trench insulating film 5. The n + -type collector sink region 6 and the p-type base sink region 7 are included therein, the n + -type collector sink region 6 includes an n + -type collector region 8, and the p-type base sink region 7 includes n A + type emitter region 9 and a p + type base region 10 are included. The arrows shown in FIG. 1A will be described later.

"Operation"
When 3000 (V) is applied as an ESD voltage to the collector electrode 14 with the emitter electrode 16 grounded, the emitter electrode 16, the n + -type collector region 8, the n + -type collector sink region 6, the n + -type buried region 3, and the p-type A current flows to the emitter electrode 16 through the base sink region 7 and the n + -type emitter region 9. This current flows through the pn junction between the n + type buried region 3 and the p type base sink region 7. At this time, the negative bias applied to the trench bias electrode 17 is applied toward the p-type base sink region 7 through the trench insulating film 5 as indicated by an arrow in FIG. Due to this negative bias, holes are unevenly distributed in the n + -type buried region 3 and the n-type semiconductor layer 4 close to the trench insulating film 5, whereby the center of the electron flow is not only the center of the pn junction, but also the trench insulating film 5. Shift to the side.

  FIG. 2 is a simulation result showing the relationship between the voltage Vtrench applied to the trench bias electrode 17 and the lattice temperature at the center of the pn junction of the n + -type buried region 3 and the p-type base sink region 7. . This simulation result is obtained by the electrostatic protection semiconductor element shown in FIG.

  As shown in FIG. 2, it can be seen that the lattice temperature decreases from about 1220 (K) to about 1130 (K) as the value of the voltage Vtrench decreases from 0 (V) to −400 (V).

  FIG. 3 is a simulation result showing the maximum lattice temperature distribution when an ESD voltage according to HBM (Human Body Model) is applied to the collector electrode 14, and (a) shows the static electricity of the present embodiment shown in FIG. 1 (b). (B) shows the result when the voltage Vtrench is −400 (V), and (c) shows the result when the voltage Vtrench is 0 (V).

  As shown in FIG. 3C, when the voltage Vtrench is 0 (V), the heat generation center is concentrated at the center of the pn junction between the n + type buried region 3 and the p type base sink region 7. On the other hand, when the voltage Vtrench is −400 (V), the center of heat generation is only the center of the pn junction between the n + type buried region 3 and the p type base sink region 7 as shown in FIG. Instead, it can be seen that the trench insulating film 5 is also dispersed.

  This is because, by applying a negative bias (Vtrench = −400 (V)) to the polysilicon film 11, holes that are minority carriers are attracted to the trench insulating film 5, and electrons flowing in the n + -type buried region 3 are attracted. This is because the electrons concentrated at the center of the pn junction between the n + type buried region 3 and the p type base sink region 7 are reduced as compared with the case of Vtrench = 0 (V) because they are coupled with holes in the vicinity of the trench insulating film 5.

  As described above, when a negative bias is applied to the trench bias electrode 17 as the voltage Vtrench, the heat generation center is not only the center of the pn junction between the n + type buried region 3 and the p type base sink region 7, but also the trench insulating film. 5, the lattice temperature at the center of the pn junction of the n + type buried region 3 and the p type base sink region 7 is lowered as shown in FIG.

  According to the present embodiment, since the electrons concentrated at the center of the pn junction between the n + -type buried region 3 and the p-type base sink region 7 can be reduced as described above, the resistance to element breakdown is improved. A semiconductor element for electrostatic protection can be provided.

  Further, since the lattice temperature at the center of the pn junction of the n + type buried region 3 and the p type base sink region 7 is lowered, the surge resistance can be improved as compared with the conventional case.

  Furthermore, since the surge withstand capability can be improved without increasing the area, an increase in manufacturing cost can be suppressed.

  As described above, the ESD tolerance can be improved by 2 to 3 times compared to the conventional electrostatic protection semiconductor element.

  Note that the case where an npn transistor is used as an electrostatic protection semiconductor element has been described above. However, when a pnp transistor is used, the conductivity type of each region or the like may be reversed. In this case, a positive bias may be applied to the trench bias electrode 17 so as to attract electrons that are decimal carriers.

  The semiconductor substrate 1, the buried insulating film 2, and the n-type semiconductor substrate 4 may be SOI (Silicon On Insulator) wafers.

  Although the electrostatic protection semiconductor device of the exemplary embodiment of the present invention has been described above, the present invention is not limited to the specifically disclosed embodiment, and departs from the scope of the claims. Without limitation, various modifications and changes are possible.

It is a figure which shows the structure of the semiconductor element for electrostatic protection of this Embodiment, (a) is a top view, (b) is AA arrow sectional drawing of (a). It is a simulation result showing the relationship between the voltage Vtrench applied to the trench bias electrode 17 and the lattice temperature (LatticeTemperature) at the center of the pn junction of the n + type buried region 3 and the p type base sink region 7. It is a simulation result which shows the maximum lattice temperature distribution at the time of applying the ESD voltage by HBM (Human Body Model) to the collector electrode 14, (a) is a semiconductor element for electrostatic protection of this Embodiment shown in FIG.1 (b) (B) shows the result when the voltage Vtrench is −400 (V), and (c) shows the result when the voltage Vtrench is 0 (V).

Explanation of symbols

1 semiconductor substrate 2 buried insulating film 3 n + type buried region 4 n type semiconductor substrate 5 trench insulating film 6 n + type collector sink region 7 p type base sink region 8 n + type collector region 9 n + type emitter region 10 p + type Base region 11 Polysilicon film 12 Locos oxide film 13 Interlayer insulating film 14 Collector electrode 15 Base electrode 16 Emitter electrode 17 Trench bias electrode 18 Power supply

Claims (3)

The peripheral and bottom surfaces are partitioned by the side surface insulating film including the trench insulating film and the polysilicon film, and the bottom surface insulating film, and electrically insulated from other elements to prevent electrostatic breakdown of the other elements. In the semiconductor device for electrostatic protection for
A first conductivity type buried region formed on the bottom insulating film;
A semiconductor region of a first conductivity type formed on the buried region and having a lower carrier concentration than the buried region;
A first conductivity type collector region formed on a surface portion of the semiconductor region;
A base region of a second conductivity type formed on a surface portion of the semiconductor region apart from the collector region;
A first conductivity type emitter region formed on a surface portion of the second conductivity type base region, and a potential having a polarity capable of attracting minority carriers in the semiconductor region is applied to the polysilicon film , Semiconductor element for electrostatic protection.   The potential applied to the polysilicon film is such that the heat generation temperature at the boundary between the base region and the buried region is lower than the melting point of silicon because the majority carriers in the semiconductor region are combined with the minority carriers. The semiconductor element for electrostatic protection according to claim 1, which is set as follows.   3. The electrostatic protection semiconductor element according to claim 1, wherein a potential applied to the polysilicon film is a bias lower than a withstand voltage of the trench insulating film.