JP2009141067A - Semiconductor device - Google Patents

Abstract

A semiconductor device capable of suppressing a decrease in heat radiation efficiency due to voids even when solder voids are formed between a substrate and a base plate.
A diode includes a raised portion that surrounds an active region and is raised above the back surface of the active region on the back surface of the substrate and below the guard ring. The substrate 10 and the base plate 12 are fixed by a solder material 30 filled inside the raised portion 18. At the time of soldering, since the raised portion 18 exists around the guard ring 14, no void is formed. The heat transfer path of the heat generated in the guard ring 14, which is a main cause of heat generation, is not obstructed by the void. The diode 100 can suppress a decrease in heat transfer efficiency due to voids.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device in which a peripheral breakdown voltage securing portion surrounding an active region in which a semiconductor element is formed is formed on the surface side of a semiconductor substrate. In particular, the present invention relates to a semiconductor device that can efficiently transfer heat generated by a semiconductor substrate to another member.

In recent years, a semiconductor device can increase a withstand voltage and flow a large current. As a semiconductor device with an increased breakdown voltage, when the semiconductor substrate is viewed in plan, a peripheral conductivity of the second conductivity type surrounding the active region where the semiconductor element is formed is secured on the surface side of the first conductivity type semiconductor substrate. A semiconductor device having a semiconductor substrate in which a portion is formed is known. Specifically, a structure called a guard ring, a field limiting ring, or a surface resurf layer is often used for the peripheral withstand voltage securing portion.
High breakdown voltage and large current semiconductor devices generate a large amount of heat. In order to prevent destruction due to heat generation, it is required to efficiently dissipate heat generated by the semiconductor substrate.
Part of the heat generated by the semiconductor substrate is dissipated through the components attached to the back surface of the semiconductor substrate. In this specification, the component is referred to as a base plate. The base plate functions as a so-called heat sink.
The semiconductor substrate and the base plate are often soldered. When soldering, bubbles may be generated between the semiconductor substrate and the base plate. A void formed by bubbles after soldering is called a solder void (hereinafter simply referred to as “void”). When the void is formed, the heat transfer efficiency from the semiconductor substrate to the base plate is lowered.
Patent Document 1 discloses a semiconductor device in which voids are hardly formed between a heat sink and a semiconductor substrate (more precisely, an insulating substrate attached to the back surface of the semiconductor substrate) during soldering. The technique of Patent Document 1 has a metal pattern in which grooves are formed on the back surface (surface on which a heat sink is attached) of a semiconductor substrate (insulating substrate). During soldering, bubbles that cause voids escape to the outside through the groove. Since the bottom surface of the groove is a metal surface, it is easy to fill the bottom surface of the groove after the bubbles are removed. Therefore, it is difficult to form voids.

JP 2006-247802 A

  According to the technique of Patent Document 1, it is possible to suppress the formation of voids, but it is difficult to completely eliminate voids. Even if a void is formed, a semiconductor device that can suppress a decrease in heat radiation efficiency due to the void is desired.

  In a semiconductor substrate having a peripheral withstand voltage securing portion, current may concentrate on the peripheral withstand voltage securing portion, and this current concentration contributes to heat generation. For example, in the diode, the recovery current is concentrated on the peripheral withstand voltage securing portion. Therefore, if it is possible to prevent the generation of voids in the vicinity of the peripheral withstand voltage securing portion, it is possible to suppress a decrease in heat transfer efficiency even if the void is generated in a region away from the peripheral withstand voltage securing portion.

  A semiconductor device according to the present invention is a back surface of a semiconductor substrate and corresponds to a peripheral withstand voltage securing portion (a region on the back surface of a semiconductor substrate when the semiconductor substrate is viewed in plan). And a ridge that surrounds the active region and rises from the back surface of the active region. In other words, the back surface of the semiconductor substrate is recessed in the active region. The semiconductor substrate and the base plate can be soldered by filling a recess surrounded by the raised portion with a solder material. During the soldering, even if a void is formed in the depression, the void is not formed because the raised portion exists in the vicinity of the peripheral voltage withstanding securing portion. The raised portion interposed between the peripheral pressure resistant portion and the base plate becomes a main diffusion path of the heat generated around the peripheral pressure resistant portion. Even if voids are formed in the depressions, the diffusion path of heat generated around the peripheral withstand voltage securing portion is not obstructed by the voids, so that a decrease in heat transfer efficiency due to the voids can be suppressed.

  Since the semiconductor substrate and the base plate may be soldered in a recess in the center of the back surface of the semiconductor substrate, the top surface of the raised portion and the base plate can be in direct contact with each other without a solder material. That is, no void is generated between the top surface of the raised portion and the base plate. The shortest heat transfer path from the peripheral withstand voltage securing portion to the base plate is not obstructed by the void. Even if voids are generated in other regions, it is possible to suppress a decrease in the heat radiation efficiency of the heat generated by the peripheral withstand voltage securing portion.

  It is preferable that the raised portion formed on the back surface of the semiconductor substrate extends to the inside of the region corresponding to the peripheral withstand voltage securing portion on the back surface of the semiconductor substrate. In particular, the heat generated inside the peripheral withstand voltage securing portion is likely to diffuse to the raised portion.

  It is preferable that the inside of the loop of the raised portion (that is, the depression at the central portion of the back surface of the semiconductor substrate) is filled with a solder material. It is because generation | occurrence | production of the void in a hollow can be suppressed. For this reason, it is preferable that a notch extending from the outside to the inside of the loop is formed in the loop-shaped ridge surrounding the active region. At the time of soldering, excess solder material can escape from the notch, so that the semiconductor substrate and the base plate can be soldered after filling the recess with sufficient solder material.

  ADVANTAGE OF THE INVENTION According to this invention, even if a void is formed between a semiconductor substrate and a baseplate, the semiconductor device which can suppress the fall of heat dissipation efficiency can be provided.

Additional technical features of the semiconductor device of the embodiment will be listed.
(First feature) A semiconductor device is a diode in which one electrode is formed on the surface of a semiconductor substrate and the other electrode is formed on the back surface of the semiconductor substrate and inside a loop-shaped ridge, or IGBT. This is because those semiconductor devices sometimes generate excessive heat in the peripheral withstand voltage securing portion than in other portions. This is because in the diode, the heat generated when the recovery current concentrates on the peripheral withstand voltage securing portion is a large factor of excessive heat generation. This is because in the IGBT, the heat generated when the current is concentrated in the peripheral withstand voltage securing portion at the time of a short circuit is a major cause of excessive heat generation.

First Embodiment A semiconductor device suitable for the present invention will be described with reference to the drawings. The semiconductor device of this example is a diode 100. FIG. 1 is a schematic perspective view of the diode 100. The diode 100 includes an n-type (first conductivity type) semiconductor substrate 10 (hereinafter referred to as the substrate 10) and a base plate 12. The substrate 10 and the base plate 12 are soldered. In FIG. 1, the hatched dots represent the solder material.
FIG. 2 is a schematic perspective view of the substrate 10 as seen from the back surface thereof. FIG. 2 shows only the substrate 10 from which the base plate 12 and the solder material are removed from the diode 100 shown in FIG.
FIG. 3 is a cross-sectional view of the diode 100 taken along line III-III in FIG.
In FIG. 1, the anode electrode 24 shown in FIG. 3 is not shown for easy understanding. In FIG. 2, the cathode electrode 28 shown in FIG. 3 is not shown for easy understanding. Further, FIG. 3 is a cross-sectional view, but the hatching is omitted in some areas for easy understanding.

First, the outline of the diode 100 will be described.
The base plate 12 to which the substrate 10 is soldered functions as a heat sink. That is, most of the heat generated by the substrate 10 is transmitted to the base plate 12 and radiated. Due to the heat radiation of the base plate 12, the temperature rise of the substrate 10 is suppressed.
A p-type (second conductivity type) guard ring 14 (peripheral withstand voltage securing region) surrounding the active region is formed on the surface side of the semiconductor substrate 10. The guard ring 14 surrounds the active region twice.
The back surface of the substrate 10 and the region corresponding to the guard ring 14 (the region that overlaps the guard ring 14 when the substrate 10 is viewed in plan) surrounds the active region and is more than the back surface of the active region. A raised ridge 18 is formed. The raised portion 18 surrounds the active region in a loop. Cutouts 16 are formed at two locations on the raised portion 18. The notch 16 communicates from the outside to the inside of the loop of the raised portion 18. The bottom surface of the notch 16 is formed at the same level as the back surface of the substrate inside the raised portion 18.

The structure of the diode 100, particularly the cross-sectional structure of the substrate 10, will be described with reference to FIG. The substrate 10 is fixed on the base plate 12 by the solder material 30. The solder material 30 is filled inside the raised portion 18. The top surface of the raised portion 18 (the lower surface of the raised portion 18 in FIG. 3) is in direct contact with the base plate 12.
A cathode electrode 28 is formed inside the raised portion 18. An n ⁺ -type cathode layer 22 is formed on the cathode electrode 28. In FIG. 3, a broken line for distinguishing the cathode layer 22 and the raised portion 18 is drawn for convenience, but both the cathode layer 22 and the raised portion 18 are integrally formed of an n ⁺ type semiconductor material. That is, when the substrate 10 is manufactured, the raised portion 18 is formed by removing the central portion of the back surface of the flat substrate 10 by etching.
An n ⁻ type drift layer 20 is formed on the cathode layer 22.
A p ⁺ -type anode region 26 is formed in a partial range of the surface layer of the drift layer 20 (the upper surface side of the drift layer 20 in FIG. 3). A p-type guard ring 14 (inner peripheral guard ring 14 a and outer peripheral guard ring 14 b) that surrounds the anode region 26 in a double manner is formed in the other range of the surface layer of the drift layer 20.
In the substrate 10, an inner region of the inner guard ring 14 a is an active region. A region surrounding the active region may be referred to as a peripheral region. The guard ring 14 is formed in the peripheral region.
An anode electrode 24 is formed on the surface of the anode region 26. The anode electrode 24 covers the surface of the anode region 26 and also covers a part of the surface of the inner peripheral guard ring 14a.

  The material between the anode electrode 24 and the cathode electrode 30 forms a diode. In other words, a diode (semiconductor element) is formed in the active region. When the substrate 10 is viewed in plan, a guard ring 14 surrounding the active region where the semiconductor element is formed is formed on the surface side of the substrate 10.

  The position of the inner peripheral edge B of the raised portion 18 is located inside the position A of the inner peripheral edge of the inner peripheral guard ring 14a. In other words, the raised portion 18 extends from the region corresponding to the guard ring 14 on the back surface of the semiconductor substrate 10 to the inside of the inner peripheral edge A.

The advantages of the diode 100 regarding the heat dissipation action will be described.
The diode 100 generates a large amount of heat around the guard ring 14 where the recovery current is concentrated. The base plate 12 functions as a heat sink. Much of the heat generated around the guard ring 14 is transferred to the base plate 12 through the ridges 18. The heat generated around the guard ring 14 is transferred to the base plate 12, thereby suppressing the temperature rise around the guard ring 14. That is, the temperature rise of the substrate 10 is suppressed. Of course, part of the heat generated around the guard ring 14 diffuses directly from the substrate 10 to the atmosphere, and the other part is transmitted to the base plate 12 through the solder material.
Voids may be formed in the solder material 30 that bonds the substrate 10 and the base plate 12. Voids that are hollow inside have a low heat transfer coefficient. However, since the solder material 30 is filled inside the raised portion 18 and the top surface of the raised portion 18 and the base plate 12 are in direct contact with each other, voids exist on the shortest path connecting the guard ring 14 and the base plate 12. Never do. Therefore, the heat generated around the guard ring 14 is efficiently transmitted to the base plate 12 through the raised portions 18 without being inhibited by the voids. Even if a void is formed, the heat transfer efficiency of the heat generated around the guard ring 14 to the base plate 12 does not decrease.

Further, when a void is generated, the heat capacity is reduced because the solder material is reduced by the capacity of the void space. If voids are formed around the guard ring 14, the heat capacity around the guard ring 14 is reduced. When the heat capacity becomes small, the breakdown tolerance of the diode 100 becomes lower than the design value.
By forming the raised portion 18, it is possible to prevent voids from being generated around the guard link 14, so that the heat capacity around the guard ring 14 is not reduced. In other words, the design heat capacity can be reliably ensured around the guard ring 14 by forming the raised portions 18.

  As shown in FIGS. 1 and 2, a notch 16 is formed in the raised portion 18. When the board 10 and the base plate 12 are soldered after filling a large amount of the solder material 30 inside the raised portion 18, excess solder material is pushed out from the notch 16. Therefore, a semiconductor device is realized in which the inside of the raised portion 18 is filled with the solder material 30 and the top surface of the raised portion 18 is in contact with the base plate 12 reliably. Since the inside of the raised portion 18 can be filled with the solder material, the generation of bubbles during soldering (that is, the formation of voids) can be suppressed. In addition, since the top surface of the raised portion 18 is surely in contact with the base plate 12 (that is, no void is formed between the top surface of the raised portion 18 and the base plate 12), the gap between the raised portion 18 and the base plate 12. High heat transfer efficiency can be ensured.

  Although the void can be formed anywhere in the region occupied by the solder material 30, in the diode 100, it is not formed near the guard ring 14 that generates the most heat. Regardless of where the void is formed in the area occupied by the solder material 30, the change in the efficiency of heat transfer generated around the guard ring 14 that generates the largest amount of heat is small. Therefore, the diode 100 has an advantage that variation in heat resistance performance is small when mass-produced.

  Further, when the diode 100 is soldered, excess solder material is pushed out from the notch 16. As a result, the top surface of the raised portion 18 formed in a loop shape on the back surface of the substrate 10 directly contacts the base plate 12. Accordingly, the substrate 10 is fixed to be inclined with respect to the base plate 12.

Second Embodiment Next, a semiconductor device according to a second embodiment will be described. The semiconductor device of the present embodiment is an IGBT 200. The IGBT 200 is different from the diode 100 of the first embodiment in the structure of the active region. The structure other than the active region is the same as that of the diode 100. That is, an overview of the IGBT 200 can be represented in FIG. An overview of the back surface of the semiconductor substrate of the IGBT 200 can be represented in FIG. The description of the overview shape of the IGBT 200 and the overview shape of the IGBT 200 as viewed from the back surface will be omitted.

FIG. 4 shows a cross-sectional view of the IGBT 200. Although FIG. 4 is a cross-sectional view, the cross-sectional hatching is omitted for easy understanding.
The substrate 210 is fixed on the base plate 212 by the solder material 230. The solder material 30 is filled inside the raised portion 218. The top surface of the raised portion 218 is in direct contact with the base plate 212.
A collector electrode 228 is formed on the back surface of the substrate 210 and on the inner surface of the raised portion 218. A p-type collector layer 222 is formed on the collector electrode 228. In FIG. 4, for convenience, a broken line for distinguishing the collector layer 222 and the raised portion 218 is drawn. However, both the collector layer 222 and the raised portion 218 are integrally formed of a p-type semiconductor material.
An n ⁻ type drift layer 220 is formed on the collector layer 222.
A p ⁻ type body region 226 is formed in a partial range of the surface layer of drift layer 220 (in FIG. 4, the upper surface side of drift layer 220). A p-type guard ring 214 (an inner peripheral guard ring 214a and an outer peripheral guard ring 214b) that doublely surrounds the body region 226 is formed in another range of the surface layer of the drift layer 220.
In the substrate 210, a region inside the inner peripheral guard ring 214a is an active region.
In the active region, a plurality of trenches 230 that penetrate the body region 226 and reach the drift layer 220 are formed. The inside of the trench 230 is filled with a conductive material. The conductive material inside the trench 230 forms the gate electrode. Although not shown, an insulating layer is formed on the upper surface of the trench 230. An emitter electrode 224 is formed on the surface of the body region 226. The conductive material in the emitter electrode 224 and the trench 230 is insulated by an insulating layer.
Although not shown, n-type emitter regions that are in contact with the emitter electrode 224 are formed on both sides of the trench 230. A p-type body contact region (not shown) is formed between the n-type emitter regions. Body region 226 is electrically connected to emitter electrode 224 through the body contact region.
The material between the emitter electrode 224 and the collector electrode 228 forms a transistor. In other words, a semiconductor element is formed in the active region.
Although not shown, a gate wiring connected to the gate electrode filled in the trench 230 is provided on the surface of the substrate.

The IGBT 200 has the same heat dissipation effect as the diode 100. That is, the heat generated around the guard ring 214 is transmitted to the base plate 212 via the raised portion 218 without being blocked by the void. Therefore, in the IGBT 200 as well as the diode 100, even if a void is formed, a decrease in heat dissipation efficiency is suppressed.
Further, the IGBT 200 has an effect of ensuring the heat capacity around the guard ring 214 as in the diode 100.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In the embodiment, the raised portion 18 can be formed by etching the central portion of the back surface of the flat substrate 10. The raised portion 18 may be formed by a method other than etching. For example, a material having a higher heat resistance temperature than the solder material may be deposited in a region around the back surface of the flat substrate 10 (a region overlapping with the guard ring 14 when viewed in plan).

  The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

1 is a schematic perspective view of a semiconductor device according to a first embodiment. It is the typical perspective view which looked at the semiconductor substrate from the back. FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line III-III in FIG. 1. It is typical sectional drawing of the semiconductor device of 2nd Example.

Explanation of symbols

10: Semiconductor substrate 12: Base plate 14: Guard ring 16: Notch 18: Raised portion 20: Drift layer 22: Cathode layer 24: Anode electrode 26: Anode region 28: Cathode electrode 30: Solder material 100: Diode (semiconductor device)
200: IGBT (semiconductor device)

Claims (4)

A semiconductor device in which a second conductivity type peripheral breakdown voltage securing portion surrounding an active region in which a semiconductor element is formed is formed on a surface side of a first conductivity type semiconductor substrate;
A semiconductor device, wherein a raised portion surrounding the active region and rising from the back surface of the active region is formed in a region corresponding to the peripheral breakdown voltage securing portion on the back surface of the semiconductor substrate. It further includes a base plate attached to the back surface of the semiconductor substrate,
2. The semiconductor device according to claim 1, wherein the top surface of the raised portion and the base plate are in contact with each other, and a solder material for fixing the semiconductor substrate and the base plate is filled in a region inside the raised portion.   3. The semiconductor device according to claim 1, wherein the raised portion extends to the inside of a region corresponding to the peripheral breakdown voltage securing portion on the back surface of the semiconductor substrate.   4. The semiconductor device according to claim 1, wherein a notch extending from the outer side to the inner side of the loop is formed in a loop-shaped ridge that surrounds the active region. 5.

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