JP2009038248A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device having a structure capable of suppressing an increase in via resistance is provided.
A semiconductor device includes an insulating film having a via hole on a semiconductor substrate, and a metal nitride film of an IVa group, a Va group, or a VIa group element formed along a bottom and a wall of the via hole. A Ta film 107 formed on the metal nitride film 106 along the bottom and wall of the via hole 105b, and a conductive film formed on the Ta film 107 so as to fill the via hole 105b. And a via 109b. The thickness of the metal nitride film 106 at the bottom of the via hole 105b is 4 nm or more and less than 8 nm.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a via having a barrier film having a laminated structure and a manufacturing method thereof.

  In recent years, there has been a demand for lower resistance along with miniaturization of semiconductor devices, and development of damascene wiring using copper as a material is progressing as one of the objects for realizing low resistance semiconductor devices. The barrier film used for damascene wiring is required to have a function to prevent copper diffusion and high adhesion to copper. A Ta / TaN laminated structure is adopted as the structure of the barrier film that satisfies these requirements. ing.

  A conventional method for manufacturing a semiconductor device will be described below with reference to the drawings.

  8A to 8E are process cross-sectional views illustrating a conventional method for manufacturing a semiconductor device in the order of processes.

  First, as shown in FIG. 8A, a silicon oxide film 12 is formed on a semiconductor substrate 11.

  Next, as shown in FIG. 8B, a lower wiring trench 13 is formed in the silicon oxide film 12 by lithography and dry etching.

  Next, as shown in FIG. 8C, a film thickness of 0.5 nm to 3. nm is formed on the bottom and walls of the lower wiring trench 13 and the silicon oxide film 12 by sputtering using an ion metal plasma chamber. A 0 nm TaN film 14 is formed, and then a 5 to 30 nm thick Ta film 15 is formed on the TaN film 14. Next, a seed layer 16 made of copper is formed on the Ta film 15 by sputtering.

  Next, as shown in FIG. 8D, a copper film 17 is formed so as to fill the lower wiring groove 13 by using an electrolytic plating method.

  Next, as shown in FIG. 8E, a TaN film 14, a Ta film 15 and a copper film 17 existing outside the lower wiring trench 13 are formed by CMP (Chemical Mechanical Polishing). Remove.

In this manner, a lower layer wiring having a barrier film having a Ta / TaN laminated structure is formed (see, for example, Patent Document 1). Thereafter, although not shown, a via having a similar barrier film connected to the lower layer wiring and an upper layer wiring connected to the via are usually formed.
Special table 2004-527132

  However, recent advances in miniaturization of semiconductor devices have led to problems such as reduced via cross-sectional area and increased via resistance, as well as barrier film thickness variations and reduced yield due to particles. Yes. In particular, an increase in via resistance causes heat generation of the metal constituting the via and degrades the reliability of the semiconductor device.

  In view of the above, an object of the present invention is to provide a semiconductor device having a structure capable of suppressing a decrease in yield and suppressing an increase in via resistance, and a manufacturing method thereof.

  In order to achieve the above-mentioned object, the present inventors have made extensive studies on the mechanism of increasing via resistance, and have reached the following findings.

  That is, for example, a case where a TaN film, a Ta film, and a copper film are sequentially formed in the via hole when the opening diameter of the via hole for forming the via is 200 nm is considered. In this case, when a TaN film is formed on the bottom and wall of the via hole so as to have a film thickness of 5 nm, a TaN film having a thickness of 5 nm is uniformly formed on the bottom and wall of the via hole. It was done.

  On the other hand, for example, when the opening diameter of a via hole is 100 nm, similarly, consider a case where a TaN film, a Ta film, and a copper film are sequentially formed inside the via hole. Also in this case, similarly, when a TaN film is formed on the bottom and wall of the via hole so as to have a film thickness of 5 nm, a TaN film having a film thickness of 5 nm is formed on the bottom and wall of the via hole. The TaN film thickness was 3 nm or less at the bottom of the via hole.

  Thus, it can be seen that the thickness of the TaN film is reduced at the bottom of the via hole as the via dimension is reduced.

  Here, when the Ta film is formed on the thinned TaN film at the bottom of the via hole, the Ta film is not composed of an α-Ta film having a specific resistance of 30 μΩcm or less, and the specific resistance is 200 μΩcm or more. The β-Ta film is modified. Thus, it can be seen that the thickness of the TaN film has a great influence on the resistivity of the Ta film formed thereon, and the film quality of the Ta film has a great influence on the resistivity.

  As described above, the increase in via resistance is due to the increase in resistivity of the Ta film constituting the barrier film in addition to the decrease in the cross-sectional area of the via due to the decrease in the opening diameter of the via hole. They found the knowledge that via resistance would increase rapidly.

  The present invention has been made in view of the above knowledge. Specifically, a semiconductor device according to the first embodiment of the present invention includes an insulating film formed on a semiconductor substrate and having a via hole, and a bottom portion of the via hole. And a metal nitride film of group IVa, Va or VIa formed along the wall, a Ta film formed on the metal nitride film along the bottom and wall of the via hole, and Ta A via made of a conductive film formed so as to fill the via hole is provided on the film, and the thickness of the metal nitride film at the bottom of the via hole is 4 nm or more and less than 8 nm.

  The semiconductor device according to the first aspect of the present invention further includes a lower wiring formed of a conductive film formed on the semiconductor substrate and connected to the metal nitride film at the bottom of the via hole.

  A semiconductor device according to a second aspect of the present invention includes a lower layer wiring made of a conductive film formed on a semiconductor substrate, an insulating film having a via hole formed on the lower layer wiring and exposing the surface of the lower layer wiring, A metal nitride film of IVa group, Va group or VIa group element formed along the bottom and wall of the via hole and connected to the surface of the lower layer wiring at the bottom of the via hole, and the bottom of the via hole on the metal nitride film And a Ta film formed along the wall, and a via made of a conductive film formed so as to fill the via hole on the Ta film, and the surface of the lower wiring connected to the metal nitride film is crystalline. It has become.

  In the semiconductor device according to the second embodiment of the present invention, the surface of the lower wiring connected to the metal nitride film is nitrided.

  In the semiconductor device according to the second embodiment of the present invention, the surface of the lower wiring connected to the metal nitride film is silicided.

  In the semiconductor device according to the second embodiment of the present invention, the surface of the metal nitride film is crystallized.

  In the semiconductor device according to the first or second aspect of the present invention, the via is made of a copper film.

  In the semiconductor device according to the first or second aspect of the present invention, the lower layer wiring is made of a copper film.

  The method for manufacturing a semiconductor device according to the first aspect of the present invention includes a step (a) of forming a via hole in an insulating film on a semiconductor substrate, and a group IVa, Va, or a group along the bottom and wall of the via hole. A step (b) of forming a metal nitride film of a VIa group element; a step (c) of forming a Ta film on the metal nitride film along the bottom and wall of the via hole; and And a step (d) of forming a via made of a conductive film so as to fill the via hole, and the thickness of the metal nitride film is 4 nm or more and less than 8 nm.

  The method for manufacturing a semiconductor device according to the first aspect of the present invention further includes a step (e) of forming a lower layer wiring made of a conductive film on a semiconductor substrate before the step (a). ) Is a step of forming a via hole exposing the surface of the lower layer wiring.

  The method for manufacturing a semiconductor device according to the second aspect of the present invention includes a step (a) of forming a lower layer wiring made of a conductive film on a semiconductor substrate, and a step (b) of forming an insulating film on the lower layer wiring. And a step (c) of forming a via hole exposing the surface of the lower layer wiring in the insulating film, and a group IVa, Va connected to the surface of the lower layer wiring at the bottom of the via hole along the bottom and wall of the via hole. A step (d) of forming a metal nitride film of a group or VIa element, a step (e) of forming a Ta film on the metal nitride film along the bottom and wall of the via hole, There is a step (f) of forming a via made of a conductive film so as to fill the via hole, and the surface of the lower wiring connected to the metal nitride film at the bottom of the via hole is crystallized.

  In the method for manufacturing a semiconductor device according to the second aspect of the present invention, a step (g) of nitriding the surface of the lower layer wiring exposed at the bottom of the via hole is further provided between the step (c) and the step (d). Prepare.

  In the method for manufacturing a semiconductor device according to the second aspect of the present invention, a step (h) of siliciding the surface of the lower layer wiring exposed at the bottom of the via hole is further provided between the step (c) and the step (d). Prepare.

  In the method of manufacturing a semiconductor device according to the second aspect of the present invention, the step (i) of annealing the surface of the lower wiring exposed at the bottom of the via hole between the steps (c) and (d) is further performed. Prepare.

  The semiconductor device manufacturing method according to the second aspect of the present invention further includes a step (j) of nitriding the surface of the metal nitride film between the step (d) and the step (e).

  In the method for manufacturing a semiconductor device according to the first or second aspect of the present invention, the via is made of a copper film.

  In the method for manufacturing a semiconductor device according to the first or second aspect of the present invention, the lower layer wiring is made of a copper film.

  According to the semiconductor device and the method for manufacturing the same according to the present invention, it is possible to suppress the increase in resistance of the barrier film that is generated in the miniaturization, to reduce the variation in via resistance, and to improve the yield. As a result, deterioration of the reliability of the semiconductor device can be suppressed.

(First embodiment)
A semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1A to FIG. 1E are cross-sectional views of relevant parts showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.

  First, as shown in FIG. 1A, a lower wiring trench 101a is formed in an insulating film 101 made of, for example, a silicon oxide film on the semiconductor substrate 100 by lithography and dry etching. Subsequently, a metal nitride film 102 made of, for example, a TaN (tantalum nitride) film having a recess 102a is formed on the insulating film 101 including the bottom and wall of the lower wiring trench 101a by sputtering, and then A Ta film 103 having a recess 103a is formed on the metal nitride film 102 including the bottom and wall of the recess 102a. Subsequently, after a seed layer (not shown) made of copper is formed on the Ta film 103 including the bottom and walls of the recess 103a by sputtering, the lower wiring groove 101a is formed by electrolytic plating. Is embedded with a copper film. Subsequently, the metal nitride film 102, the Ta film 103, and the copper film existing outside the lower wiring trench 101a are removed by a CMP method (Chemical Mechanical Polishing), thereby removing the metal nitride film 102. Then, a lower layer wiring 104 made of a copper film having a barrier film having a laminated structure of the Ta film 103 is formed. Subsequently, an insulating film 105 having a thickness of 300 nm is formed on the insulating film 101, the lower layer wiring 104, the Ta (tantalum) film 103, and the metal nitride film 102 by a CVD method at a film forming temperature of 350 ° C. Film. Here, the insulating film 105 is made of a material composed of Si (silicon) and C (carbon), O (oxygen), N (nitrogen), or the like. In this embodiment, the insulating film 105 is described as an example of a single-layer insulating film. However, the insulating film 105 may be formed of an insulating film formed by stacking two or more layers. Furthermore, as a method for forming the insulating film 105, it is also possible to form a film by applying a solvent and then performing an annealing process at 200 ° C. or higher.

  Next, as shown in FIG. 1B, a via hole 105b exposing the upper surface of the lower layer wiring 104 and an upper layer wiring communicating with the via hole 105b are formed on the insulating film 105 by a dry etching method using a photoresist as a mask. The grooves 105a are formed in order.

Next, as shown in FIG. 1C, a recess 106a is formed as a metal nitride film on the insulating film 105 including the bottom and walls of the via hole 105b and the bottom and walls of the upper wiring trench 105a by sputtering. For example, a TaN film 106 having the following structure is formed. Here, the TaN film 106 is formed under the conditions of a target bias of 30 kW, a substrate bias of 400 W, and a nitrogen (N ₂ ) flow rate of 75 × 10 ⁻³ ml / min (sccm) or less. By forming the film under the conditions, a TaN film 106 having a film thickness of 4 nm or more and 8 nm or less is formed as described later. As described above, when the via hole 105b has an opening diameter of 200 nm or less or a height of 500 nm or more as the semiconductor device is miniaturized, as described above, the film is uniformly formed on the bottom and the wall of the via hole 105b, for example, about 5 nm. Even if it tries, the situation where only about 3 nm film-forming is formed in this bottom part can be avoided.

  Subsequently, a Ta film 107 having a recess 107a is formed on the TaN film 106 including the bottom and the wall of the recess 106a by sputtering. Here, the maximum film thickness of the Ta film 107 is appropriate so that no embedding defect occurs when the via hole 105b and the upper wiring groove 105a are filled with a copper film to be described later. It is preferable to form the film so that the total of the film thickness and the film thickness of the Ta film 107 is about 40 nm at the maximum. The Ta film 107 is composed of an α-Ta film as will be described later.

  Subsequently, a 40 nm-thick seed layer 108 made of copper having a recess 108a is formed on the Ta film 107 including the bottom and wall of the recess 107a by sputtering. Here, the deposition conditions of the seed layer 108 are a target bias of 40 kW and a substrate bias of 600 W. Here, the seed layer 108 is formed using a PVD (Physical Vapor Deposition) method, but may be formed using a CVD (Chemical Vapor Deposition) method.

  Next, as shown in FIG. 1 (d), the seed layer including the inside of the recess 108a is obtained by immersing the semiconductor device in a copper sulfate solution by electroplating and passing a current through the seed film 108 described above. A copper film having a thickness of 500 nm is formed on 108. In this way, the copper film 109 including the seed layer 108 is formed. The copper sulfate plating solution used here has a chlorine concentration of 10 ppm to 100 ppm, a sulfuric acid concentration of 10 to 250 g / L, and a copper concentration of 5 to 100 g / L.

  Next, as shown in FIG. 1E, the copper film 109, the Ta film 107, and the TaN film 106 existing outside the via hole 105b and the upper wiring groove 105a are removed by a CMP method. A via 109b and an upper wiring 109a having a barrier film having a laminated structure of the film 107 and the TaN film 106 are formed.

  Here, the reason why the thickness of the TaN film 106 is 4 nm or more and less than 8 nm at the bottom of the via hole 105b will be described.

  FIG. 2A shows the relationship between the film thickness of the TaN film 106 and the specific resistance of the Ta / TaN laminated film in the first embodiment of the present invention. The horizontal axis represents the film thickness of the TaN film 106, and the vertical axis represents the specific resistance of the barrier film (Ta / TaN laminated film).

  As shown in FIG. 2A, it can be seen that when the TaN film 106 is less than 4 nm, the specific resistance of the barrier film (Ta / TaN laminated film) rapidly increases. From this, it can be seen that the thickness of the TaN film 106 is preferably 4 nm or more.

  FIG. 2B shows that the orientation of the Ta film 107 measured using XRD (X-ray diffraction) depends on the thickness of the TaN film 106. The horizontal axis represents the angle of X-rays applied to the sample, and the vertical axis represents the peak size.

  As shown in FIG. 2B, it can be seen that when the thickness of the TaN film 106 is reduced, the Ta film 107 on the TaN film 106 is changed from α-Ta to β-Ta. Here, the peak of β-Ta (330) is 37.392 (deg), the peak of α-Ta (110) is 38.5 (deg), and the peak of β-Ta (331) is 41. 2 (deg). β-Ta is easily formed on an amorphous surface such as a silicon oxide film, and α-Ta is easily formed on a crystallized (not amorphous structure) surface of the TaN film. As described above, when the TaN film 106 is thinned, the mechanism that β-Ta is easily formed is as follows. That is, since the outermost surface of the copper film constituting the lower layer wiring 104 that becomes the base film of the TaN film 106 is amorphized by dry etching, damage during cleaning, or oxidation, an attempt is made to form the TaN film 106 thereon. Then, at the initial stage of film formation, the interface portion of the TaN film 106 with the copper film also has an amorphous structure. Then, when the TaN film 106 is formed to have a thickness of 3 nm or more, it is considered that the crystallization gradually proceeds and the portion having no amorphous structure increases. On the crystallized surface of the TaN film 106, the Ta film 107 formed thereon becomes easy to fix Ta atoms to fixed lattice sites by migration after sputtering, and a cubic Ta film 107 is formed. It becomes easy. From the above, the film thickness of the TaN film 106 is necessary for the outermost surface to be crystallized, and is 4 nm or more as shown in FIG.

  FIG. 3 shows the relationship between via resistance and cumulative frequency in the first embodiment of the present invention. The horizontal axis represents the via resistance, and the vertical axis represents the cumulative frequency. In the same figure, the case where the thickness of the TaN film 106 is 4.0 nm (3a) and the case where it is 3.2 nm (3b) are shown.

  As shown in FIG. 3, when the thickness of the TaN film 106 is 3.2 nm at the bottom of the via hole 105b (3b), it can be seen that the distribution of via resistance varies on the high resistance side. In addition, when the thickness of the TaN film 106 is 4.0 nm at the bottom of the via hole 105b (3a), it can be seen that variations in via resistance are suppressed. Thus, it can be seen that the thickness of the TaN film 106 is preferably 4 nm or more at the bottom of the via hole 105b also from the viewpoint of suppressing variation in via resistance.

  On the other hand, when the thickness of the TaN film 106 is 8 nm or more at the bottom of the via hole 105b, the specific resistance increases by the specific resistance of the TaN film 106 itself having a high specific resistance, so that the via resistance can be reduced. become unable. In addition, when the TaN film 106 having a thickness of 8 nm or more is formed, the embedding characteristic of the copper film 109 in the via hole 105b and the upper wiring groove 105a is greatly affected.

  As described above, the thickness of the TaN film 106 needs to be 4 nm or more and less than 8 nm at the bottom of the via hole 105b.

Next, the reason why the nitrogen (N ₂ ) flow rate when forming the TaN film 106 is 75 × 10 ⁻³ ml / min (sccm) or less will be described.

FIG. 4A shows the relationship between the specific resistance of the TaN film 106 and the flow rate of nitrogen (N ₂ ). The horizontal axis represents the N ₂ flow rate, and the vertical axis represents the specific resistance of the TaN film 106.

As shown in FIG. 4A, it can be seen that when the N ₂ flow rate exceeds 75 (sccm), the specific resistance of the TaN film 106 increases.

FIG. 4B shows the relationship between the film thickness uniformity (Rs) of the TaN film 106 and the nitrogen (N ₂ ) flow rate. The horizontal axis represents the N ₂ flow rate, and the vertical axis represents the film thickness uniformity of the TaN film 106.

As shown in FIG. 4B, it can be seen that when the N ₂ flow rate exceeds 75 (sccm), the film thickness uniformity of the TaN film 106 deteriorates. When the N ₂ flow rate is high, crystallization of the TaN film 106 is promoted, but nitriding of the target and shield in the chamber proceeds and causes generation of particles. Therefore, when the N ₂ flow rate is high, the ratio of the TaN film 106 is increased. There arises a problem that resistance increases and film thickness uniformity deteriorates.

  From the above, the nitrogen flow rate when forming the TaN film 106 is desirably 75 (sccm) or less.

  As described above, according to the manufacturing method of the semiconductor device according to the first embodiment of the present invention, the Ta film made of the α-Ta film having a low specific resistance is formed in the via hole 105b having an opening diameter of 200 nm or less or a height of 500 nm or more. Since a barrier film having a laminated structure of 107 and TaN film 106 can be formed, a semiconductor device having a via structure in which an increase in via resistance is suppressed is realized. As a result, a highly reliable semiconductor device can be obtained.

  In this embodiment, the case where the TaN film 106 is formed as the metal nitride film has been described. However, instead of the TaN film, for example, Ti (titanium), W (tungsten), Zr (zirconium), etc., group IV Even when a metal nitride film of a group Va, group VIa element is formed, the present invention can be implemented in the same manner.

(Second Embodiment)
A semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 5A to FIG. 5E are cross-sectional views of relevant parts showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.

  In the method of manufacturing the semiconductor device according to the second embodiment of the present invention shown in FIGS. 5A to 5E, the surface of the lower layer wiring exposed at the bottom of the via hole in the step shown in FIG. Since the other steps are the same as those of the semiconductor device manufacturing method according to the first embodiment described above, the following description will focus on the characteristic portions. 5A to FIG. 5E, FIG. 1A to FIG. 1E used for explaining the method of manufacturing the semiconductor device according to the first embodiment described above. Since the parts corresponding to the constituent parts shown in FIG. 2 are the same but different in the reference numerals, the description thereof will not be repeated.

In the method for manufacturing a semiconductor device according to the second embodiment of the present invention, as shown in FIG.
The exposed copper film is formed by performing a nitrogen annealing process at 100 ° C. to 400 ° C. in a state where the surface of the copper film constituting the lower layer wiring 204 exposed to the via hole 205b is exposed to the outside air. The surface 210 is nitrided to form a crystallized region 210. Here, instead of the nitrogen annealing treatment, a region 210 is formed by nitriding and crystallizing the surface of the exposed copper film by the ammonia plasma method under the conditions of room temperature to 400 ° C. in the same state. Also good. Further, the gas used in the nitrogen annealing treatment or the ammonia plasma method may be any gas that contains nitrogen and does not contain oxygen. Further, although nitriding is performed by plasma treatment, nitriding may be performed using laser irradiation with a short wavelength capable of decomposing gas.

  Thus, by crystallization or nitriding the surface of the copper film constituting the lower layer wiring 204 exposed at the bottom of the via hole 205b, it is possible to prevent the surface from being damaged by dry etching or cleaning. This prevents the surface of the copper film exposed at the bottom of the via hole 205b from becoming difficult to crystallize or causing lattice defects. As a result, it is possible to assist the formation of the nitride film when forming the TaN film 206 in the next step shown in FIG.

  5C, when the TaN film 206 is formed on the insulating film 205 including the inside of the via hole 205b and the upper layer wiring groove 205a, the lower layer wiring 204 exposed at the bottom of the via hole 205b in the previous step. Since the surface of the copper film constituting the film is crystallized and no longer has an amorphous structure, the TaN film 206 is crystallized from the initial stage of film formation. Therefore, the Ta film 207 formed on the upper layer of the TaN film 206 that has been crystallized from the beginning of the film formation is easily formed as an α-Ta film. In addition, since the surface of the copper film constituting the lower layer wiring 204 exposed at the bottom of the via hole 205b is crystallized and thus has no amorphous structure, the TaN film 206 is not used as in the first embodiment described above. Even if the film thickness is not less than 4 nm and less than 8 nm, the Ta film 207 is formed as an α-Ta film. However, if the thickness of the TaN film 206 is 4 nm or more and less than 8 nm, the Ta film 207 is more likely to be formed as an α-Ta film. Therefore, under the same film formation conditions as in the first embodiment. The film thickness of the TaN film 206 is more preferably 4 nm or more and less than 8 nm.

  As described above, according to the method of manufacturing a semiconductor device according to the second embodiment of the present invention, the Ta film made of the α-Ta film having a low specific resistance is formed in the via hole 105b having an opening diameter of 200 nm or less or a height of 500 nm or more. Since a barrier film having a laminated structure of 207 and TaN film 206 can be formed, a semiconductor device having a via structure in which an increase in via resistance is suppressed is realized. As a result, a highly reliable semiconductor device can be obtained.

  In the present embodiment, similarly to the first embodiment, instead of the TaN film 206 as the metal nitride film, for example, Ti (titanium), W (tungsten), Zr (zirconium), etc., group IV, A metal nitride film of a Va group or VIa group element can be used in the same manner.

(Third embodiment)
A semiconductor device and a manufacturing method thereof according to a third embodiment of the present invention will be described with reference to the drawings.

  FIG. 6A to FIG. 6E are cross-sectional views of relevant parts showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention in the order of steps.

  In the method of manufacturing the semiconductor device according to the third embodiment of the present invention shown in FIGS. 6A to 6E, the surface of the TaN film formed in the step shown in FIG. 6C is nitrided. Since the other steps are the same as those of the semiconductor device manufacturing method according to the first embodiment described above, the following description will focus on the features. 6A to 6E used in the description of the semiconductor device manufacturing method according to the first embodiment described above. Since the parts corresponding to the constituent parts shown in FIG. 2 are the same but different in the reference numerals, the description thereof will not be repeated.

  As shown in FIG. 6C, for example, a recess 306a is formed as a metal nitride film on the insulating film 305 including the bottom and walls of the via hole 305b and the bottom and walls of the upper wiring trench 305a by sputtering. A TaN (tantalum nitride) film 306 is formed. Subsequently, nitriding of the surface of the TaN film 306 is promoted by ammonia plasma treatment. This is because the surface of the TaN film 306 after sputtering is likely to be amorphous, so that the top surface of the TaN film 306 is crystallized by nitriding and crystallizing the top surface of the TaN film 306. This is because the Ta film 307 is easily formed as an α-Ta film. Then, when the Ta film 307 is formed on the TaN film 306 including the bottom and the wall of the recess 306a, the amount of nitrogen in the underlying TaN film 306 increases, and crystallization of the outermost surface of the TaN film 306 is promoted. Therefore, the Ta film 307 is easily formed as an α-Ta film. Here, the ammonia plasma method is used as a method for nitriding the TaN film 306, but the gas used may be any gas that contains nitrogen and does not contain oxygen. Further, although nitriding is performed by plasma treatment, nitriding can also be performed using laser irradiation with a short wavelength capable of decomposing gas.

  As described above, since the surface of the TaN film 306 is crystallized and no longer has an amorphous structure, the film thickness of the TaN film 306 is 4 nm or more and less than 8 nm as in the second embodiment. The Ta film 307 is formed as an α-Ta film even if the film is not formed by the above method. However, if the film thickness of the TaN film 306 is 4 nm or more and less than 8 nm, the Ta film 307 is more easily formed as an α-Ta film, and therefore the same film formation conditions as in the first embodiment. Therefore, it is more preferable that the thickness of the TaN film 306 is 4 nm or more and less than 8 nm.

  Similarly to the second embodiment, in the step shown in FIG. 6B, the surface of the copper film constituting the lower layer wiring 304 exposed in the via hole 305b is subjected to nitriding treatment, whereby the surface of the copper film is formed. You may crystallize instead of an amorphous structure. This is because the Ta film 307 is more easily formed as an α-Ta film.

  As described above, according to the manufacturing method of the semiconductor device according to the third embodiment of the present invention, the Ta film made of the α-Ta film having a low specific resistance is formed in the via hole 305b having an opening diameter of 200 nm or less or a height of 500 nm or more. Since a barrier film having a stacked structure of 307 and the TaN film 306 can be formed, a semiconductor device having a via structure in which an increase in via resistance is suppressed is realized. As a result, a highly reliable semiconductor device can be obtained.

  In the present embodiment, similarly to the first embodiment, instead of the TaN film 306 as the metal nitride film, for example, Ti (titanium), W (tungsten), Zr (zirconium), etc., group IV, A metal nitride film of a Va group or VIa group element can be used in the same manner.

(Fourth embodiment)
A semiconductor device and a manufacturing method thereof according to a fourth embodiment of the present invention will be described with reference to the drawings.

  FIG. 7A to FIG. 7E are cross-sectional views of relevant parts showing a method of manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps.

  In the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention shown in FIGS. 7A to 7E, the surface of the lower layer wiring exposed at the bottom of the via hole in the step shown in FIG. 7B. Since the other steps are the same as those of the semiconductor device manufacturing method according to the first embodiment described above, the following description will focus on the characteristic portions. 7A to 7E used in the method for manufacturing the semiconductor device according to the first embodiment described above in the components shown in FIGS. Since the parts corresponding to the constituent parts shown in FIG. 2 are the same but different in the reference numerals, the description thereof will not be repeated.

In the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, as shown in FIG. 7B, the surface of the copper film constituting the lower layer wiring 404 exposed in the via hole 405b is exposed to the outside air. Thus, a region 410 in which the surface of the exposed copper film is silicided is formed by flowing SiH ₄ gas under conditions of 100 ° C. to 450 ° C. Here, since the wiring resistance increases when the thickness of the silicided region 410 on the surface of the copper film increases, the thickness of the region 410 is preferably 5 nm or less. Further, instead of SiH ₄ gas, a gas made of polysilane (Si _n H _{2n + 2} ) (n ≦ 2) or organic silane (for example, tetramethylsilane) may be used.

  Thus, siliciding the surface of the copper film exposed to the via hole 405b promotes the reaction between silicon and nitrogen, so that the ratio of nitrogen at the bottom of the via hole 405b increases. Accordingly, when the TaN film 406 is formed by sputtering on the silicided region 410 of the lower layer wiring 404 exposed at the bottom of the via hole 405b, the crystallized TaN film 406 is formed at the bottom of the via hole 405a. It becomes easy to be done. As a result, in the next step shown in FIG. 7C, the Ta film 407 formed on the TaN film 406 is easily formed as an α-Ta film.

  That is, in the step shown in FIG. 7C, when the TaN film 406 is formed on the insulating film 405 including the inside of the via hole 405b and the upper layer wiring trench 405a, the lower layer wiring 404 exposed at the bottom of the via hole 405b in the previous step. Since the surface of the copper film constituting the film is silicided, the reaction between silicon and nitrogen is promoted and crystallization is facilitated. Therefore, the interface between the surface of the copper film and the TaN film 406 does not have an amorphous structure, so that the TaN film 406 is crystallized from the initial stage of film formation. Therefore, the Ta film 407 formed on the upper layer of the TaN film 406 that has been crystallized from the beginning of the film formation is easily formed as an α-Ta film. In addition, since the surface of the copper film constituting the lower layer wiring 404 exposed at the bottom of the via hole 405b is crystallized and is not in an amorphous structure, the first structure described above is obtained as in the second embodiment. As in the embodiment, even if the TaN film 406 has a film thickness of 4 nm or more and less than 8 nm, the Ta film 407 is formed as an α-Ta film. However, if the thickness of the TaN film 406 is set to 4 nm or more and less than 8 nm, the Ta film 407 is more easily formed as an α-Ta film. Therefore, the film forming conditions are the same as those in the first embodiment. Thus, it is more preferable that the thickness of the TaN film 406 be 4 nm or more and less than 8 nm.

  As described above, according to the semiconductor device manufacturing method of the fourth embodiment of the present invention, the Ta film made of the α-Ta film having a low specific resistance is formed in the via hole 305b having an opening diameter of 200 nm or less or a height of 500 nm or more. Since a barrier film having a stacked structure of 407 and TaN film 406 can be formed, a semiconductor device having a via structure in which an increase in via resistance is suppressed is realized. As a result, a highly reliable semiconductor device can be obtained.

  In this embodiment, as in the first embodiment, instead of the TaN film 406 as a metal nitride film, for example, Ti (titanium), W (tungsten), Zr (zirconium), etc., group IV, A metal nitride film of a Va group or VIa group element can be used in the same manner.

  In each of the above embodiments, the lower layer wiring, the via, and the upper layer wiring have been described with respect to the case of using a copper film as a material from the viewpoint of reducing the resistance. However, the present invention is not limited to the copper film. A conductive film may be used.

  As described above, the present invention is useful for a method of manufacturing a semiconductor device for forming a low resistance barrier film to suppress an increase in via resistance.

(A)-(e) is principal part sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (A) is a relational diagram between the film thickness of the TaN film and the specific resistance of the Ta / TaN laminated film in the first embodiment of the present invention, and (b) is measured using XRD (X-ray diffraction). It is a figure which shows the TaN film thickness dependence of the orientation of the done Ta film. It is a relationship figure of via resistance and accumulation frequency in a 1st embodiment of the present invention. (A) is a relationship diagram between the specific resistance of the TaN film and the flow rate of nitrogen (N ₂ ), and (b) is a relationship diagram of the film thickness uniformity (Rs) of the TaN film and the flow rate of nitrogen (N ₂ ). It is. (A)-(e) is principal part sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. (A)-(e) is principal part sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention in process order. (A)-(e) is principal part sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention in process order. It is principal part sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process.

Explanation of symbols

100, 200, 300, 400 Semiconductor substrate 101, 201, 301, 401 Insulating film 101a, 201a, 301a, 401a Lower wiring trench 102, 202, 302, 402 Metal nitride film 102a, 202a, 302a, 402a Recess 103, 203, 303, 403 Ta film 103a, 203a, 303a, 403a Recess 104, 204, 304, 404 Lower layer wiring 105, 205, 305, 405 Insulating film 105a, 205a, 305a, 405a Upper layer wiring trench 105b, 205b, 305b, 405b Via hole 106 , 206, 306, 406 TaN films 106a, 206a, 306a, 406a Recesses 107, 207, 307, 407 Ta films 107a, 207a, 307a, 407a Recesses 108, 208, 308, 408 Seed layer 108 a, 208a, 308a, 408a Recess 109, 209, 309, 409 Copper film 109a, 209a, 309a, 409a Upper layer wiring 109b, 209b, 309b, 409b Via 210 Crystallized area 410 Silicided area

Claims (17)

An insulating film formed on a semiconductor substrate and having a via hole;
A metal nitride film of an IVa group, a Va group or a VIa group element formed along the bottom and wall of the via hole;
A Ta film formed on the metal nitride film along the bottom and wall of the via hole,
A via made of a conductive film formed to fill the via hole on the Ta film;
The thickness of the metal nitride film at the bottom of the via hole is 4 nm or more and less than 8 nm. The semiconductor device according to claim 1,
A semiconductor device further comprising a lower layer wiring formed on the semiconductor substrate and made of a conductive film connected to the metal nitride film at the bottom of the via hole. A lower layer wiring made of a conductive film formed on a semiconductor substrate;
An insulating film formed on the lower wiring and having a via hole exposing the surface of the lower wiring;
A metal nitride film of an IVa group, Va group or VIa group element formed along the bottom and wall of the via hole and connected to the surface of the lower layer wiring at the bottom of the via hole;
A Ta film formed on the metal nitride film along the bottom and wall of the via hole,
A via made of a conductive film formed to fill the via hole on the Ta film;
A semiconductor device, wherein a surface of the lower wiring connected to the metal nitride film is crystallized. The semiconductor device according to claim 3.
A semiconductor device, wherein a surface of the lower wiring connected to the metal nitride film is nitrided. The semiconductor device according to claim 3.
A semiconductor device, wherein a surface of the lower wiring connected to the metal nitride film is silicided. The semiconductor device according to any one of claims 3 to 5,
A semiconductor device, wherein a surface of the metal nitride film is crystallized. The semiconductor device according to any one of claims 1 to 6,
The via is a semiconductor device made of a copper film. In the semiconductor device of any one of Claims 2-7,
The lower layer wiring is a semiconductor device made of a copper film. Forming a via hole in the insulating film on the semiconductor substrate (a);
A step (b) of forming a metal nitride film of an IVa group, Va group or VIa group element along the bottom and wall of the via hole;
(C) forming a Ta film on the metal nitride film along the bottom and wall of the via hole;
(D) forming a via made of a conductive film on the Ta film so as to fill the via hole;
The method of manufacturing a semiconductor device, wherein the metal nitride film has a thickness of 4 nm or more and less than 8 nm. In the manufacturing method of the semiconductor device according to claim 9,
Prior to step (a),
A step (e) of forming a lower wiring made of a conductive film on the semiconductor substrate;
The method (a) is a method of manufacturing a semiconductor device, which is a step of forming the via hole exposing the surface of the lower layer wiring. Forming a lower wiring made of a conductive film on a semiconductor substrate (a);
Forming an insulating film on the lower layer wiring (b);
Forming a via hole exposing the surface of the lower layer wiring in the insulating film (c);
Forming a metal nitride film of an IVa group, a Va group or a VIa group element connected to the surface of the lower layer wiring at the bottom of the via hole along the bottom and wall of the via hole;
A step (e) of forming a Ta film on the metal nitride film along the bottom and wall of the via hole;
A step (f) of forming a via made of a conductive film so as to fill the via hole on the Ta film;
The method of manufacturing a semiconductor device, wherein a surface of the lower layer wiring connected to the metal nitride film at the bottom of the via hole is crystallized. In the manufacturing method of the semiconductor device according to claim 11,
Between the step (c) and the step (d),
A method of manufacturing a semiconductor device, further comprising a step (g) of nitriding the surface of the lower layer wiring exposed at the bottom of the via hole. In the manufacturing method of the semiconductor device according to claim 11,
Between the step (c) and the step (d),
A method of manufacturing a semiconductor device, further comprising a step (h) of siliciding the surface of the lower layer wiring exposed at the bottom of the via hole. In the manufacturing method of the semiconductor device according to claim 11,
Between the step (c) and the step (d),
A method of manufacturing a semiconductor device, further comprising a step (i) of performing nitrogen annealing on the surface of the lower layer wiring exposed at the bottom of the via hole. In the manufacturing method of the semiconductor device of any one of Claims 11-14,
Between the step (d) and the step (e),
A method for manufacturing a semiconductor device, further comprising a step (j) of nitriding the surface of the metal nitride film. In the manufacturing method of the semiconductor device of any one of Claims 9-15,
The method for manufacturing a semiconductor device, wherein the via is made of a copper film. In the manufacturing method of the semiconductor device according to any one of claims 10 to 16,
The method of manufacturing a semiconductor device, wherein the lower layer wiring is made of a copper film.

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