JP2009032961A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance a manufacture yield of a semiconductor device equipped with a semiconductor element which has a butting diffusion structure. <P>SOLUTION: An active region 3a used for a pMIS and surrounded by an element isolation region 2, an active region 3b for a Vdd potential power supply unit, and an active region 3c for pMIS coupling are defined on a main face of a semiconductor substrate 1. A boundary portion 8 between a p<SP>+</SP>-type semiconductor region 7b, which is designed for source and used in common by two pMIS's (Qp) in a two-input NAND gate CMOS logic circuit, and an n<SP>+</SP>-type semiconductor region 6b for the Vdd potential power supply unit are not prepared in the active region 3c for pMIS coupling and prepared in the active region 3a for the pMIS. As a result, disconnection of a silicide layer formed on the surface of the p<SP>+</SP>-type semiconductor region 7b for the source of pMIS (Qp) formed all along the boundary portion 8, and the n<SP>+</SP>-type semiconductor region 6b for the Vdd potential power supply unit can be prevented. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and in particular, a butting diffusion structure in which an n-type diffusion region (impurity region, semiconductor region) and a p-type diffusion region (impurity region, semiconductor region) are in contact with each other. The present invention relates to a semiconductor device including a semiconductor element having the above and a technique effective when applied to the manufacture thereof.

  For example, Japanese Patent Laying-Open No. 2006-287257 (see Patent Document 1) discloses a contact for supplying a predetermined potential to a substrate region in a standard cell having a substrate region formed beyond a boundary line with an adjacent cell. A structure is disclosed in which the diffusion layer forming the substrate region of the portion where the contact is disposed is extended from the center of the width of the substrate region to the inside of the cell. Yes.

Further, for example, Japanese Patent Laid-Open No. 2005-347360 (see Patent Document 2) includes a MOS transistor in which an n-type impurity region is formed in a p-well provided in a silicon substrate, and a GND potential is applied to the p-well. In a semiconductor device having a GND contact for supply, a part of an n-type impurity region is removed by etching, and a p-type power supply diffusion layer is formed on the silicon substrate in the etched-off region. A configuration in which power is supplied to the p-well by a GND contact connected to a diffusion layer for use is disclosed.
JP 2006-287257 A (paragraph [0007], paragraph [0017], FIG. 1) JP 2005-347360 A (paragraphs [0019] to [0027], FIGS. 2 and 3)

  The present inventors have made various CMOS (Complementary Metal Oxide) composed of an n channel field effect transistor (Metal Insulator Semiconductor Field Effect Transistor: n channel MISFET) and a p channel field effect transistor (p channel MISFET). Semiconductor) is developing semiconductor devices using logic circuits.

  In recent years, with the reduction of the chip area of semiconductor products, the reduction of the size of the CMOS logic circuit is also being studied, and the present inventors are considering the use of a batting diffusion structure as one of the countermeasures. For example, when a batting diffusion structure is adopted in a NAND type CMOS logic circuit, in a p-channel type MISFET, an n-type semiconductor region for a Vdd potential power supply unit that supplies a Vdd potential and a p-type semiconductor region for a source are directly connected. In the n-channel type MISFET, the p-type semiconductor region for the Vss potential power supply unit that supplies the Vss potential and the n-type semiconductor region for the source are directly connected.

  However, the batting diffusion structure has various technical problems described below.

  FIG. 21 is a main part plan view showing an example of a two-input NAND type CMOS logic circuit adopting the batting diffusion structure studied by the present inventors, and FIG. 22 (a) is examined by the present inventors. FIG. 22B is a main part sectional view showing a defective example of the batting diffusion structure, and FIG. 22B is a main part sectional view taken along the line DD ′ of FIG. 21 and 22A show a gate electrode and source / drain p-type semiconductor region constituting a p-channel MISFET, and a gate electrode and source / drain n-type semiconductor region constituting an n-channel MISFET. , A Vdd potential feeding portion, a Vss potential feeding portion, and a contact hole are shown, and a silicide layer and wiring are omitted.

  As shown in FIG. 21, an active region (hereinafter referred to as an active region for pMIS) 52a in which two p-channel MISFETs (Qp) sharing a source are formed on the main surface of a semiconductor substrate 51, and Vdd An active region (hereinafter referred to as an active region for the Vdd potential power supply portion) 52b in which the potential power supply portion is formed is defined (enclosed) by the element isolation region 53, respectively. Further, an active region 52c (hereinafter referred to as an active region for pMIS coupling) 52c is formed between the active region 52a for pMIS and the active region 52b for the Vdd potential feeding portion, and this pMIS is formed. The active region 52c for coupling includes a p-type semiconductor region for source of the p-channel type MISFET (Qp) (region shown by diagonally rising to the left) 54 and an n-type semiconductor region for the Vdd potential feeding portion (upward to the right). A boundary portion 56 with respect to a region 55 shown by oblique hatching 55 is provided. Since the width (WBDp in FIG. 21) of the active region 52c for pMIS coupling needs to be narrower than the interval between two adjacent gate electrodes 57 (WG in FIG. 21), for example, two adjacent gates When the distance (WG) between the electrodes 57 is 0.3 μm, the width (WBDp) of the active region 52c for pMIS coupling is 0.2 μm.

  Further, on the main surface of the semiconductor substrate 51, an active region 58a in which two n-channel MISFETs (Qn) are formed (hereinafter referred to as an nMIS active region) 58a, and an active region in which a Vss potential power supply portion is formed. 58b (hereinafter referred to as an active region for the Vss potential feeding portion) are defined (enclosed) by the element isolation region 53. Further, an active region 58c (hereinafter referred to as an active region for nMIS coupling) 58c is formed between the active region 58a for nMIS and the active region 58b for the Vss potential power supply unit. The active region 58c for coupling includes an n-type semiconductor region for source of the n-channel MISFET (Qn) (region shown by diagonally rising to the right) 59 and a p-type semiconductor region for the Vss potential feeding portion (upward to the left). A boundary portion 61 with an area 60 indicated by oblique hatching is provided. In FIG. 21, reference numeral 62 indicates a contact hole.

  By the way, the p-type semiconductor region 54 for the source of the p-channel type MISFET (Qp) and the n-type semiconductor region 55 for the Vdd potential feeding portion are electrically connected by a silicide layer formed on these surfaces. . Accordingly, the silicide layer formed on the surface of the pMIS coupling active region 52c electrically connects the p-type semiconductor region 54 for the source of the p-channel type MISFET (Qp) and the n-type semiconductor region 55 for the Vdd potential power supply unit. Will be connected. However, as described above, the width (WBDp) of the active region 52c for pMIS coupling is as narrow as 0.2 μm, for example, and stress from the gate electrode 57 tends to concentrate on the silicide layer. As shown in (a) and (b), the silicide layer 63 formed on the surface of the active region 52c for pMIS coupling may break (region indicated by Bp in FIG. 22). When the silicide layer 63 formed on the surface of the active region 52c for pMIS coupling is disconnected, the p-type semiconductor region 54 for the source of the p-channel type MISFET (Qp) and the n-type semiconductor region 55 for the Vdd potential feeding portion are formed. Since it cannot be electrically connected, a defect occurs and causes a reduction in product yield.

  The same applies to the n-channel MISFET (Qn), and detailed description and illustration thereof are omitted. However, if the silicide layer formed on the surface of the active region 58c for nMIS coupling is disconnected, the n-channel MISFET (Qn) Since the n-type semiconductor region 59 for the source and the p-type semiconductor region 60 for the Vss potential feeding portion cannot be electrically connected, a defect occurs and the product yield is lowered.

  An object of the present invention is to provide a technique capable of improving the manufacturing yield of a semiconductor device including a semiconductor element having a batting diffusion structure.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor device according to the present invention includes a semiconductor substrate, a first active region for a field effect transistor surrounded by an element isolation region, and a second active for a potential power supply unit extending in a second direction surrounded by the element isolation region. And a third active region for coupling surrounded by an element isolation region that connects the first active region and the second active region arranged in a first direction orthogonal to the second direction, and A first semiconductor region of a first conductivity type for a source or drain of a field effect transistor and a second semiconductor region of a second conductivity type opposite to the first conductivity type for a potential feeder are formed, and the first semiconductor region Device in which the first semiconductor region and the second semiconductor region are in direct contact, and the first semiconductor region and the second semiconductor region are electrically connected by the silicide layer formed on the surface of the first semiconductor region and the surface of the second semiconductor region And the first semiconductor region and the first semiconductor region In which the boundary portion where the semiconductor region is in contact is provided in the first active region or the second active region.

  A method of manufacturing a semiconductor device according to the present invention includes a first active region for a field effect transistor surrounded by an element isolation region on a main surface of a semiconductor substrate, and a second active region for a potential power feeding portion extending in a second direction. Forming a first active region located in a first direction orthogonal to the second direction and a third active region for coupling that connects the second active region, and a second conductivity type on the semiconductor substrate Impurities are introduced to form a second conductivity type well in the first active region, the second active region, and the third active region, and a gate insulating film and a gate electrode of the field effect transistor are formed in the first active region And a step of forming, by ion implantation, a first semiconductor region for a source or drain of a field effect transistor made of an impurity of the first conductivity type opposite to the second conductivity type in a part of the first active region. By ion implantation In addition, the second semiconductor region for the potential feeding unit, which is formed of the second conductive type impurity in the other part of the first active region where the first semiconductor region is not formed, the second active region, and the third active region. Forming a boundary portion where the first semiconductor region and the second semiconductor region are in contact with each other in the first active region, and forming a silicide layer on the surfaces of the first active region, the second active region, and the third active region. Forming the process.

  A method of manufacturing a semiconductor device according to the present invention includes a first active region for a field effect transistor surrounded by an element isolation region on a main surface of a semiconductor substrate, and a second active region for a potential power feeding portion extending in a second direction. Forming a first active region located in a first direction orthogonal to the second direction and a third active region for coupling that connects the second active region, and a second conductivity type on the semiconductor substrate Impurities are introduced to form a second conductivity type well in the first active region, the second active region, and the third active region, and a gate insulating film and a gate electrode of the field effect transistor are formed in the first active region And a source of a field effect transistor comprising an impurity of a first conductivity type opposite to the second conductivity type in the first active region, a part of the second active region, and the third active region by an ion implantation method. Or first semiconductor region for drain Forming a second semiconductor region for a potential power feeding portion made of an impurity of the second conductivity type in another part of the second active region where the first semiconductor region is not formed by a forming step and an ion implantation method; Forming a boundary portion between the first semiconductor region and the second semiconductor region in the second active region; forming a silicide layer on the surfaces of the first active region, the second active region, and the third active region; It is what has.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since electrical disconnection at the boundary between the n-type semiconductor region and the p-type semiconductor region can be prevented, the manufacturing yield of a semiconductor device including a semiconductor element having a batting diffusion structure can be improved.

  In this embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Some or all of the modifications, details, supplementary explanations, and the like are related.

  Further, in this embodiment, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless otherwise specified, or in principle limited to a specific number in principle. The number is not limited to the specific number, and may be a specific number or more. Further, in the present embodiment, the constituent elements (including element steps and the like) are not necessarily essential unless particularly specified and apparently essential in principle. Yes. Similarly, in this embodiment, when referring to the shape, positional relationship, etc. of the component, etc., the shape, etc. substantially, unless otherwise specified, or otherwise considered in principle. It shall include those that are approximate or similar to. The same applies to the above numerical values and ranges.

  In the drawings used in the present embodiment, hatching may be added even in a plan view for easy understanding of the drawings. In the present embodiment, a MISFET that represents a field effect transistor may be abbreviated as MIS, a p-channel MISFET may be abbreviated as pMIS, and an n-channel MISFET may be abbreviated as nMIS. In this embodiment, the term “wafer” mainly refers to a Si (Silicon) single crystal wafer, but not only to this, but also to form an SOI (Silicon On Insulator) wafer and an integrated circuit thereon. It refers to an insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like.

  In all the drawings for explaining the embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
A NAND type CMOS logic circuit employing the batting diffusion structure according to the first embodiment will be described with reference to FIGS. 1 is a circuit diagram of a 2-input NAND gate CMOS logic circuit, FIG. 2 is a plan view of an essential part showing an example of a 2-input NAND gate CMOS logic circuit, and FIGS. 3A and 3B are 2-input NAND gate CMOS logic circuits. FIG. 4A is a main part sectional view taken along line AA ′ of FIG. 2, and FIG. 4B is a main part sectional view taken along line BB ′ of FIG. FIG. 4C is a cross-sectional view of the main part taken along the line CC ′ of FIG.

  As shown in FIG. 1, the 2-input NAND gate CMOS logic circuit uses nMIS (Qn) as a driver MISFET, pMIS (Qp) as a load MISFET, and both gate electrodes and drains of nMIS (Qn) and pMIS (Qp). Are the input terminals A and B and the output terminal Y, respectively. Since the basic circuit of this CMOS logic circuit is a CMOS inverter that discharges with nMIS (Qn) and charges with pMIS (Qp), in a steady state, only one of them conducts according to the input, and a direct current Since there is no path, there is no power consumption and power is consumed only when switching is excessive. Further, since the source of nMIS (Qn) is fixed at the Vss potential and the source of pMIS (Qp) is fixed at the Vdd potential, there is an advantage that there is no substrate bias effect.

As shown in FIG. 2, two pMISs constituting a CMOS logic circuit and sharing a source (that is, a gate insulating film, a gate electrode, a p ⁻ type semiconductor region for source / drain, and a p ⁺ type semiconductor constituting pMIS) The region Qp is formed in the active region 3 a for pMIS defined (enclosed) by the element isolation region 2 on the main surface of the semiconductor substrate 1. Two adjacent gate electrodes 4 of pMIS (Qp) are formed in parallel to the first direction. The Vdd potential power supply section that supplies the Vdd potential is formed in the active region 3b for the Vdd potential power supply section defined (enclosed) by the element isolation region 2 on the main surface of the semiconductor substrate 1. The active region 3b for the Vdd potential feeding portion is formed to extend in a second direction orthogonal to the first direction.

Further, between the active region 3a for pMIS in which pMIS (Qp) is formed and the active region 3b for Vdd potential power supply section in which the Vdd potential power supply portion is formed, an active region for pMIS coupling (both) A region 3c surrounded by a fine dotted line is formed. An active region 3c for pMIS coupling is an active region 3a for pMIS located between two gate electrodes 4 (an active region in which a p ⁺ type semiconductor region for a source shared by two pMIS (Qp) is formed). Are connected to the active region 3b for the Vdd potential feeding portion. In order to prevent the width (WBDp) along the first direction of the active region 3c for pMIS coupling from contacting the adjacent two gate electrodes 4 of pMIS (Qp) formed in the active region 3a for pMIS, It is formed narrower than the distance (WG) between the two gate electrodes 4.

Similarly, the two nMISs constituting the CMOS logic circuit (that is, the gate insulating film, the gate electrode, the source / drain n ⁻ type semiconductor region and the n ⁺ type semiconductor region constituting the nMIS) Qn are formed on the semiconductor substrate 1. The main surface is formed in the active region 5a for nMIS defined (enclosed) by the element isolation region 2. Two adjacent gate electrodes 4 of nMIS (Qn) are formed parallel to the first direction. One gate electrode 4 of pMIS (Qp) and one gate electrode 4 of nMIS (Qn) are connected in the first direction, and the other gate electrode 4 of pMIS (Qp) and nMIS (Qn) The other gate electrode 4 is connected in the first direction. The Vss potential power supply section that supplies the Vss potential is formed in the active region 5 b for the Vss potential power supply section defined (enclosed) by the element isolation region 2 on the main surface of the semiconductor substrate 1. The active region 5b for the Vss potential power supply portion is formed extending in the second direction.

Further, between the active region 5a for nMIS in which nMIS (Qn) is formed and the active region 5b for Vss potential supply unit in which the Vss potential supply unit is formed, an active region for nMIS coupling (the active region 5b for connecting them) A region 5c surrounded by a fine dotted line is formed. The nMIS coupling active region 5c connects the nMIS active region 5a on the source side of one nMIS (Qn) and the active region 5b for the Vss potential power supply section. The width (WBDn) along the first direction of the active region 5c for nMIS coupling is the width along the second direction of the active region where the n ⁺ -type semiconductor region for the source of nMIS (Qn) is formed ( LSn) is formed narrower.

Although not shown in FIG. 2, the surface of the p ⁺ type semiconductor region for source / drain of pMIS (Qp), the surface of the gate electrode 4 of pMIS (Qp), the surface of the active region 3c for pMIS coupling, A silicide layer is formed on the surface of the n ⁺ type semiconductor region for the Vdd potential power supply unit. Similarly, the surface of the n ⁺ -type semiconductor region for source / drain of the n-channel type MISFET (Qn), the surface of the gate electrode 4 of nMIS (Qn), the surface of the active region 5c for nMIS coupling, and the Vss potential power supply unit A silicide layer is formed on the surface of the p ⁺ type semiconductor region.

In the first embodiment, as described above, the active region 3a for pMIS surrounded by the element isolation region 2, the active region 3b for the Vdd potential power supply unit, and the active region 3c for pMIS coupling are included. The active regions are defined, and these three active regions (active region 3a for pMIS, active region 3b for Vdd potential feeding portion, and active region 3c for pMIS coupling) are the source and source of pMIS described later. This is different from the p ⁺ type semiconductor region for the drain or the n ⁺ type semiconductor region for the Vdd potential feeding portion. Similarly, the active region 5a for nMIS surrounded by the element isolation region 2, the active region 5b for the Vss potential power supply unit, and the active region 5c for nMIS coupling are defined, and these are defined. The three active regions (the active region 5a for nMIS, the active region 5b for the Vss potential feeding portion, and the active region 5c for nMIS coupling) are n ⁺ type semiconductor regions for nMIS source / drain, which will be described later, or This is different from the p ⁺ type semiconductor region for the Vss potential power supply unit. The same applies to the following second to fifth embodiments.

p ⁺ type semiconductor region for source of pMIS (Qp) 7b (region shown by oblique hatching rising to the left in FIG. 2) and n ⁺ type semiconductor region for the Vdd potential power supply portion (diagonal hatching rising to the right in FIG. 2) A region 8 (shown by a one-dot broken line) 8 with the region 6b is not provided in the active region 3c for pMIS coupling, but is provided in the active region 3a for pMIS. That is, the boundary portion 8 is provided between the two gate electrodes 4 of pMIS (Qp) and is not in contact with the two gate electrodes 4 and is provided in the active region 3a for pMIS. Further, the length of the boundary portion 8 is formed longer than the width (WBDp) along the second direction of the active region 3c for pMIS coupling. Since the boundary portion 8 is provided in the active region 3a for pMIS, and the length of the boundary portion 8 is longer than the width (WBDp) along the second direction of the active region 3c for pMIS coupling, The silicide layers formed on the surfaces of the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential power supply portion do not break along the entire boundary portion 8. It is conceivable (even if the silicide layer is disconnected at a part of the boundary portion 8 as long as the silicide layer is connected at the other part), the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and Vdd It is possible to prevent the occurrence of electrical disconnection with the n ⁺ type semiconductor region 6b for the potential power supply unit. The width (WBDp) along the second direction of the active region 3c for pMIS coupling may be, for example, 0.18 μm, and the interval (WG) between two adjacent gate electrodes 4 may be, for example, 0.28 μm.

In FIG. 2, the boundary 8 between the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential feeding portion is in the first direction of the active region 3a for pMIS. The pMIS coupling active region 3c is formed to extend straight while maintaining the width (WBDp) along the second direction, and for the pMIS opposite to the active region 3b for the Vdd potential feeding portion. Reaches the end of the active region 3a. Therefore, the length of the boundary portion 8 between the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential power supply portion is the first direction of the active region 3a for pMIS. It is twice the width (Wp1) along.

A plurality of contact holes 9 reaching the ^{n +} -type semiconductor regions (silicide layer) 6b for Vdd potential feed section, formed in the active region 3b for Vdd potential power supply unit, the active region 3a and pMIS binding for pMIS It is not formed in the active region 3c.

Similarly, an n ⁺ -type semiconductor region for source of nMIS (Qn) (region shown by oblique hatching rising to the right in FIG. 2) 6b and a p ⁺ -type semiconductor region for Vss potential feeding portion (upward to the left in FIG. 2). The region (shown by a one-dot broken line) 8 with respect to the region 7b shown by diagonal hatching is not provided in the active region 5c for nMIS coupling, but is provided in the active region 5a for nMIS. That is, the boundary 8 is provided in the nMIS active region 5a on the source side of one nMIS (Qn) without contacting the gate electrode 4. The length of the boundary portion 8 is longer than the width (WBDn) along the second direction of the active region 5c for nMIS coupling. By forming the length of the boundary portion 8 to be longer than the width (WBDn) along the second direction of the active region 5c for nMIS coupling, a part for the source of nMIS (Qn) is formed at a part of the boundary portion 8. Even if the silicide layers formed on the surfaces of the n ⁺ -type semiconductor region 6b and the p ⁺ -type semiconductor region 7b for the Vss potential feeding portion are disconnected, there is a high possibility that the silicide layer is connected to other portions of the boundary portion 8. Therefore, it is possible to prevent the occurrence of electrical disconnection between the n ⁺ type semiconductor region 6b for the source of nMIS (Qn) and the p ⁺ type semiconductor region 7b for the Vss potential feeding portion. The width (WBDn) along the second direction of the active region 5c for nMIS coupling can be set to 0.18 μm, for example.

In Figure 2, the boundary portion 8 of the ^{n +} -type semiconductor region 6b and Vss ^{p +} -type semiconductor regions 7b for potential power supply unit for the source of the nMIS (Qn) is in a first direction of the active region 5a for nMIS The nMIS coupling active region 5c is formed to extend straight while maintaining the width (WBDn) along the second direction, and the nMIS coupling active region 5c is opposite to the active region 5b for the Vss potential power supply unit. Reaches the end of the active region 5a. Accordingly, the length of the boundary portion 8 between the n ⁺ type semiconductor region 6b for the source of nMIS (Qn) and the p ⁺ type semiconductor region 7b for the Vss potential feeding portion is the first direction of the active region 5a for nMIS. (Wn1) along the line.

A plurality of contact holes 9 reaching the Vss ^{p +} -type semiconductor regions (silicide layer) for potential feeding portion 7b is formed in the active region 5b for the potential Vss power supply unit, the active region 5a and nMIS binding for nMIS It is not formed in the active region 5c.

^{p +} -type semiconductor regions 7b for Vss potential power supply section formed in the active region 5a of the active region ^{n +} -type semiconductor region 6b for potential Vdd power supply unit formed in 3a and nMIS for pMIS is Figure It is not limited to the shape shown in 2.

3 (a) and 3 (b) show modifications thereof. For example, as shown in FIG. 3A, the width along the second direction of the n ⁺ -type semiconductor region 6b for the Vdd potential feeding portion formed in the active region 3a for pMIS is set to the active region for pMIS coupling. It can be formed narrower than the width (WBDp) along the second direction of 3c. Similarly, the width along the second direction of the p ⁺ type semiconductor region 7b for the Vss potential feeding portion formed in the active region 5a for nMIS is set along the second direction of the active region 5c for nMIS coupling. It can be formed narrower than the width (WBDn).

Further, as shown in FIG. 3B, the boundary portion 8 between the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential supply portion is a Vdd potential supply portion. It is not necessary to reach the end of the pMIS active region 3a opposite to the active region 3b. Similarly, the boundary 8 between the n ⁺ type semiconductor region 6b for the source of nMIS (Qn) and the p ⁺ type semiconductor region 7b for the Vss potential power supply portion is opposite to the active region 5b for the Vss potential power supply portion. It does not have to reach the end of the active region 5a for nMIS.

  4 (a), 4 (b) and 4 (c) are cross-sectional views of the main parts of the pMIS and Vdd potential power supply portions constituting the 2-input NAND gate CMOS logic circuit (respectively along the lines AA ′ and B− in FIG. Sectional views along line B 'and line CC') are shown. FIG. 4 shows only pMIS (Qp), and nMIS (Qp) is substantially the same as pMIS (Qp), and thus description thereof is omitted here.

The pMIS (Qp) is formed in the active region 3a for pMIS surrounded by the element isolation region 2 formed in the semiconductor substrate 1, and the active region 3a for pMIS is formed in the n well 10n. A gate insulating film 11 made of, for example, silicon oxide is formed on the surface of the semiconductor substrate 1 (n well 10n), and a gate electrode 4p made of, for example, polycrystalline silicon is further formed thereon. On both sides of the semiconductor substrate 1 of the gate electrode 4p (n-well 10n) is, p of a pair of low impurity concentration ^- -type semiconductor regions 7a are formed in self-alignment with the gate electrode 4p. A sidewall 12 is formed on the side wall of the gate electrode 4p, and a pair of high impurity concentration p ⁺ type semiconductor regions 7b are formed on the sidewall 12 on the semiconductor substrate 1 (n well 10n) on both sides of the sidewall 12. Is formed in a self-aligned manner. Therefore, the source / drain of pMIS (Qp) has an LDD (Lightly doped Drain) structure. A low-resistance metal silicide layer 13, for example, a cobalt silicide layer, a nickel silicide layer, or a titanium silicide layer, is formed on the surfaces of the gate electrode 4p and the source / drain p ⁺ type semiconductor region 7b.

The n ⁺ -type semiconductor region 6b for the Vdd potential feeding portion includes an active region 3b for the Vdd potential feeding portion surrounded by an element isolation region 2 formed in the semiconductor substrate 1, an active region 3c for pMIS coupling, and 2 The pMIS active region 3a is sandwiched between p ⁺ type semiconductor regions 7b for the source of two pMIS (Qp). In addition, the n ⁺ type semiconductor region 6b for the Vdd potential power supply portion is formed in the n well 10n, and a low resistance metal silicide layer 13 is formed on the surface thereof.

Further, on the semiconductor substrate 1 including the ^{n +} -type semiconductor regions 6b above for pMIS (Qp) and Vdd potential power supply unit is formed an interlayer insulating film 14. The interlayer insulating film 14 includes a contact hole 9 reaching the p ⁺ type semiconductor region 7b (metal silicide layer 13) for the source / drain of pMIS (Qp), and a gate electrode 4p (metal silicide layer 13) of pMIS (Qp). And a plurality of contact holes 9 reaching the n ⁺ -type semiconductor region 6b (metal silicide layer 13) for the Vdd potential feeding portion formed in the active region 3b for the Vdd potential feeding portion. It is open. A plug 15 made of, for example, metal is embedded in the contact hole 9, and the wiring 16 is connected to the p ⁺ type semiconductor region 7 b for pMIS (Qp) source / drain via the plug 15, pMIS ( Qp) is electrically connected to a gate electrode 4p of Vp or a Vdd potential power supply portion and an n ⁺ type semiconductor region 6b for a Vdd potential power supply portion. An insulating film 17 is formed on the semiconductor substrate 1 including the wiring 16.

  Next, a method of manufacturing a 2-input NAND gate CMOS logic circuit employing the batting diffusion structure according to the first embodiment will be described in the order of steps with reference to FIGS. 5 to 12 are cross-sectional views of the main parts of pMIS and nMIS constituting a 2-input NAND gate CMOS logic circuit. 5 to 12 are main part cross-sectional views along the second direction of the active region 3a for pMIS and the active region 5a for nMIS, and the active region 3b for the Vdd potential power supply unit and the Vss potential power supply. The principal part sectional drawing along the 1st direction of the active region 5b for parts is shown.

  First, as shown in FIG. 5, a semiconductor substrate 1 (prepared as a semiconductor wafer having a substantially circular shape called a semiconductor wafer at this stage) 1 made of p-type single crystal Si having a specific resistance of about 1 to 10 Ωcm is prepared. To do. Then, after forming a groove (element isolation groove) 2a having a depth of, for example, about 300 nm on the semiconductor substrate 1 in the element isolation formation scheduled region, on the semiconductor substrate 1 including the inside (side wall and bottom) of the groove 2a, An insulating film 2b is deposited by CVD or the like so as to fill the trench 2a.

  Next, the insulating film 2b is polished by a CMP (Chemical Mechanical Polishing) method, the insulating film 2b outside the groove 2a is removed, and the insulating film 2b is left inside the groove 2a, thereby forming the element isolation region 2. To do. Then, the semiconductor substrate 1 is heat-treated at, for example, about 1000 ° C., thereby baking the insulating film 2b embedded in the trench 2a. In this manner, the element isolation region 2 composed of the insulating film 2b embedded in the trench 2a is formed by the STI (Shallow Trench Isolation) method. That is, the above-described active region 3a for pMIS, active region 3b for the Vdd potential feeding portion, and active region 3c for pMIS coupling are formed in the active region defined (enclosed) by the element isolation region 2. In addition, the above-described active region 5a for nMIS, active region 5b for Vss potential feeding portion, and active region 5c for nMIS coupling are also formed in the active region defined (enclosed) by the element isolation region 2.

Next, as shown in FIG. 6, a p-well 10p and an n-well 10n are formed from the surface of the semiconductor substrate 1 to a predetermined depth. The p well 10p is planned to be formed by using a photoresist film that covers the pMIS formation planned regions (active region 3a for pMIS, active region 3b for Vdd potential feeding portion and active region 3c for pMIS coupling) as an ion implantation blocking mask. For example, B (boron) or BF ₂ (boron fluoride) is ion-implanted into the semiconductor substrate 1 in the regions (the active region 5a for nMIS, the active region 5b for the Vss potential feeding portion, and the active region 5c for nMIS coupling). It can be formed by doing. The n well 10n is formed by using another photoresist film covering the nMIS formation planned region (the active region 5a for nMIS, the active region 5b for the Vss potential feeding portion, and the active region 5c for nMIS coupling) as an ion implantation blocking mask. , For example, P (phosphorus) or As (arsenic) is ionized on the semiconductor substrate 1 in the pMIS formation scheduled region (active region 3a for pMIS, active region 3b for Vdd potential feeding portion and active region 3c for pMIS coupling). It can be formed by injection or the like.

  Next, after the surface of the semiconductor substrate 1 is cleaned (washed) by, for example, wet etching using an HF (hydrofluoric acid) aqueous solution, the surface of the semiconductor substrate 1 (that is, the surface of the p well 10p and the n well 10n) is formed. A gate insulating film 11 is formed. The gate insulating film 11 is made of, for example, a thin silicon oxide film, and can be formed by, for example, a thermal oxidation method.

Next, a silicon film 4a such as a polycrystalline silicon film is formed on the semiconductor substrate 1 (that is, on the gate insulating film 11 of the p well 10p and the n well 10n) as a conductive film for forming a gate electrode. An nMIS formation planned region (region to be a gate electrode 4n described later) in the silicon film 4a has a low resistance by ion implantation of phosphorus (P) or arsenic (As) using a photoresist film as a mask. N-type semiconductor film (doped polysilicon film). In addition, a pMIS formation scheduled region (region to be a gate electrode 4p described later) in the silicon film 4a is ion-implanted with boron (B) or BF ₂ using another photoresist film as a mask. It is a low-resistance p-type semiconductor film (doped polysilicon film). The silicon film 4a can be changed from an amorphous silicon film at the time of film formation to a polycrystalline silicon film by heat treatment after film formation (after ion implantation).

  Next, as shown in FIG. 7, gate electrodes 4n and 4p are formed by patterning the silicon film 4a using a photolithography method and a dry etching method. The gate lengths of the gate electrodes 4n and 4p can be changed as necessary, but can be about 50 nm, for example.

Next, a pair of n ⁻ -type semiconductor regions 6a are formed by ion-implanting P or As or the like into regions on both sides of the gate electrode 4n of the active region 5a for nMIS, and the gate electrode of the active region 3a for pMIS is formed. A pair of p ⁻ -type semiconductor regions 7a is formed by ion-implanting B or BF ₂ or the like into regions on both sides of 4p. The depth (junction depth) of the n ⁻ type semiconductor region 6a and the p ⁻ type semiconductor region 7a can be set to, for example, about 30 nm.

  Next, as shown in FIG. 8, on the sidewalls of the gate electrodes 4n and 4p, sidewall spacers or sidewalls (sidewalls) made of, for example, a silicon oxide film, a silicon nitride film, or a laminated film of these insulating films as an insulating film. Insulating film) 12 is formed. For example, the sidewall 12 is formed by depositing a silicon oxide film, a silicon nitride film, or a laminated film thereof on the semiconductor substrate 1 and depositing the silicon oxide film, the silicon nitride film, or the laminated film by an RIE (Reactive Ion Etching) method or the like. It can be formed by anisotropic etching.

After the formation of the sidewalls 12, a pair of n ⁺ -type semiconductor regions 6b are formed by ion-implanting P or As into the gate electrode 4n of the active region 5a for nMIS and the regions on both sides of the sidewalls 12. A pair of p ⁺ type semiconductor regions 7b is formed by ion-implanting B, BF ₂ or the like into the gate electrode 4p of the active region 3a for pMIS and the regions on both sides of the sidewall 12. The n ⁺ type semiconductor region 6b may be formed first, or the p ⁺ type semiconductor region 7b may be formed first. After the ion implantation, heat treatment for activating the introduced impurities can be performed. The depth (junction depth) of the n ⁺ type semiconductor region 6b and the p ⁺ type semiconductor region 7b can be set to, for example, about 80 nm.

The n ⁺ type semiconductor region 6b has a higher impurity concentration than the n ⁻ type semiconductor region 6a, and the p ⁺ type semiconductor region 7b has a higher impurity concentration than the p ⁻ type semiconductor region 7a. Thus, an n-type semiconductor region (impurity diffusion layer) functioning as an nMIS source or drain is formed by the n ⁺ -type semiconductor region (impurity diffusion layer) 6b and the n ⁻ -type semiconductor region 6a, and the pMIS source or drain is formed. A p-type semiconductor region (impurity diffusion layer) that functions as a p ⁺ type semiconductor region (impurity diffusion layer) 7b and a p ⁻ type semiconductor region 7a. Therefore, the source / drain of nMIS and pMIS have an LDD structure. n ⁺ -type semiconductor region 6b can be regarded as the semiconductor region for the source or drain of the nMIS (Qn), ^{p +} -type semiconductor regions 7b are be regarded as the semiconductor region for the source or drain of the pMIS (Qp) it can.

Further, the n ⁺ type semiconductor region 6b for the source or drain of nMIS (Qn) is formed, and at the same time, P or As or the like is ion-implanted into the active region 3b for the Vdd potential power supply portion, thereby providing the Vdd potential power supply portion. N ⁺ type semiconductor region 6b is formed. Further, the p ⁺ type semiconductor region 7b for the source or drain of pMIS (Qp) is formed, and at the same time, B or BF ₂ or the like is ion-implanted into the active region 5b for the Vss potential power supply unit. A ^p.sup . ⁺ Type semiconductor region 7b is formed.

Next, as shown in FIG. 9, the surface of the gate electrode 4n and the source / drain (here n ⁺ -type semiconductor region 6b) of the nMIS (Qn), the gate electrode 4p of the pMIS (Qp) and the source / drain (here Then, a metal silicide layer, for example, CoSi, is formed on the surface of the p ⁺ type semiconductor region 7b), the surface of the n ⁺ type semiconductor region 6b for the Vss potential feeding portion, and the surface of the p ⁺ type semiconductor region 7b for the Vdd potential feeding portion. _{2 The} (cobalt silicide) layer 18 is formed by a self-alignment method, for example, a salicide (Salicide: Self Align silicide) process. First, after exposing the surfaces of the gate electrodes 4n and 4p, the n ⁺ type semiconductor region 6b and the p ⁺ type semiconductor region 7b, the gate electrodes 4n and 4p, the n ⁺ type semiconductor region 6b and the p ⁺ type semiconductor region 7b are exposed. A cobalt (Co) film is deposited on the included semiconductor substrate 1 by sputtering, for example. Then, by subjecting the semiconductor substrate 1 to a heat treatment using an RTA (Rapid Thermal Anneal) method, the Co film reacts with Si of the polycrystalline silicon film constituting the gate electrode to cause the reaction on the surfaces of the gate electrodes 4n and 4p ( A CoSi ₂ layer 18 is formed on the upper layer portions of the gate electrodes 4n and 4p. Further, by the heat treatment, CoSi ₂ layer 18 is formed on reacting the Si of the Co film and ^{the n +} -type semiconductor regions 6b on the surface of the ^{n +} -type semiconductor regions 6b (the upper layer portion of the ^{n +} -type semiconductor regions 6b) The Further, by the heat treatment, CoSi ₂ layer 18 is formed on reacting the Si of the Co film and the ^{p +} -type semiconductor regions 7b on the surface of the ^{p +} -type semiconductor regions 7b (upper layer portion of the ^{p +} -type semiconductor regions 7b) The Thereafter, the unreacted cobalt film is removed. By forming the CoSi ₂ layer 18, a CoSi ₂ layer 18, it is possible to reduce the contact resistance between the plug and the like formed thereon, and the gate electrode 4n, 4p, ^{n +} -type semiconductor regions 6b and p The resistance of the ⁺ type semiconductor region 7b itself can be reduced.

Further, as another material of the CoSi ₂ (cobalt silicide) layer 18, Ni (nickel) or Ti (titanium) is used as a metal film to form a NiSi ₂ (nickel silicide) layer or a TiSi ₂ (titanium silicide) layer. Also good.

Next, as shown in FIG. 10, an insulating film 14 a is formed on the main surface of the semiconductor substrate 1. That is, the insulating film 14a is formed on the semiconductor substrate 1 including the CoSi ₂ layer 18 so as to cover the gate electrodes 4n and 4p. The insulating film 14a is made of, for example, a silicon nitride film, and can be formed by a CVD method or the like. Then, an insulating film 14b thicker than the insulating film 14a is formed on the insulating film 14a. The insulating film 14b is made of, for example, a silicon oxide film such as an O ₃ -TEOS oxide film. Note that the O ₃ -TEOS oxide film is a silicon oxide formed by a thermal CVD method using O ₃ (ozone) and TEOS (Tetraethoxysilane: Tetra Ethyl Ortho Silicate) as a source gas (source gas). It is a membrane. Thereby, an interlayer insulating film 14 composed of the insulating films 14a and 14b is formed. Thereafter, the upper surface of the insulating film 14b is planarized by polishing the surface of the insulating film 14b by a CMP method or the like. Even if the surface of the insulating film 14a is uneven due to the base step, the surface of the insulating film 14b is polished by CMP to obtain the interlayer insulating film 14 with a flattened surface. it can.

Next, as shown in FIG. 11, by using the photoresist film formed on the interlayer insulating film 14 as a mask, the interlayer insulating film 14 is dry-etched, whereby contact holes (through holes, holes) are formed in the interlayer insulating film 14. ) 9 is formed. At this time, first, the insulating film 14b is dry-etched under a condition that the insulating film 14b is more easily etched than the insulating film 14a, and the insulating film 14a functions as an etching stopper film, so that the contact hole 9 is formed in the insulating film 14b. After the formation, the insulating film 14a at the bottom of the contact hole 9 is removed by dry etching under the condition that the insulating film 14a is more easily etched than the insulating film 14b. At the bottom of the contact hole 9, a part of the main surface of the semiconductor substrate 1, for example, a part of the CoSi ₂ layer 18 on the surface of the n ⁺ -type semiconductor region 6b for the source or drain of nMIS (Qn), pMIS (Qp) some of the CoSi ₂ layer 18 on the surface of the ^{p +} -type semiconductor regions 7b for the drain of a portion of the CoSi ₂ layer 18 on the surface of the ^{p +} -type semiconductor regions 7b for Vss potential power supply unit and the Vdd potential power supply unit Part of the CoSi ₂ layer 18 on the surface of the n ⁺ type semiconductor region 6b for use is exposed.

Next, a plug (connecting conductor portion) 15 made of W (tungsten) or the like is formed in the contact hole 9. In order to form the plug 15, for example, a barrier conductor film 15 a (for example, a TiN (titanium nitride) film or a Ti (titanium) film and a TiN film is formed on the interlayer insulating film 14 including the inside (on the bottom and side walls) of the contact hole 9. A laminated film) is formed. Then, a main conductor film 15b made of a W film or the like is formed by CVD or the like so as to fill the contact hole 9 on the barrier conductor film 15a, and unnecessary main conductor film 15b and barrier conductor film 15a on the interlayer insulating film 14 are formed. The plug 15 can be formed by removing by a CMP method or an etch back method. The plug 15 formed on the gate electrodes 4n, 4p, the n ⁺ type semiconductor region 6b or the p ⁺ type semiconductor region 7b has a gate electrode 4n, 4p, an n ⁺ type semiconductor region 6b or a p ⁺ type semiconductor region 7b at the bottom. And in contact with the CoSi ₂ layer 18 on the surface of the substrate.

Next, as shown in FIG. 12, a wiring 16 made of, for example, W is formed as a first layer wiring on the interlayer insulating film 14 in which the plug 15 is embedded. The wiring 16 can be formed by forming a conductor film such as a W film on the interlayer insulating film 14 and patterning the conductor film by a photolithography method and a dry etching method. Wiring 16, the source or ^{n +} -type semiconductor region 6b for the drain, ^{p +} -type semiconductor regions 7b for the drain of the pMIS (Qp), ^{p +} -type for the Vss potential power supply portion of the nMIS (Qn) via the plug 15 n ⁺ -type semiconductor region 6b and is electrically connected to the semiconductor region 7b and the Vdd potential power source. The wiring 16 is not limited to a W film and can be variously modified. For example, a single film such as an Al (aluminum) film or an Al alloy film, or a Ti film or a TiN film on at least one of upper and lower layers of these single films is used. You may form with the laminated metal film in which the various metal film was formed. Further, the wiring 16 can be an embedded wiring (for example, embedded copper wiring) formed by a damascene method.

  Next, an insulating film 17 is formed on the interlayer insulating film 14 so as to cover the wiring 16. Thereafter, vias or through holes that expose part of the wiring 16 are formed in the insulating film 17 in the same manner as the contact holes 9, and the plugs or plugs that fill the through holes are formed in the same manner as the plugs 15 and wirings 16. Thus, a second layer wiring electrically connected to the wiring 16 is formed, but illustration and description thereof are omitted here. After the second layer wiring, embedded wiring (for example, embedded copper wiring) formed by the damascene method may be used.

As described above, according to the first embodiment, in the case of pMIS (Qp) constituting a 2-input NAND gate CMOS logic circuit, the pMIS active region 3a surrounded by the element isolation region 2 is formed on the semiconductor substrate 1. The active region 3b for the Vdd potential power supply section and the active region 3c for pMIS coupling are defined, and the p ⁺ type semiconductor region 7b for the source shared by the two pMIS (Qp) is defined. And the n ⁺ -type semiconductor region 6b for the Vdd potential feeding portion are not provided in the active region 3c for pMIS coupling, but are provided in the active region 3a for pMIS. This prevents disconnection of the silicide layers formed on the surfaces of the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential feeding portion along the entire boundary portion 8. Even if the silicide layer is disconnected at a part of the boundary portion 8, the silicide layer is connected at the other part. Therefore, the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) The occurrence of electrical disconnection with the n ⁺ -type semiconductor region 6b for the Vdd potential power supply unit can be prevented.

The same applies to the case of nMIS (Qn). In the semiconductor substrate 1, an nMIS active region 5a surrounded by an element isolation region 2, an active region 5b for a Vss potential feeding portion, and an active region 5c for nMIS coupling are provided. Are defined, and the boundary 8 between the n ⁺ -type semiconductor region 6b for the source of one nMIS (Qn) and the p ⁺ -type semiconductor region 7b for the Vss potential feeding portion is connected by nMIS coupling. The active region 5c is not provided in the active region 5c but is provided in the active region 5a for nMIS. This prevents disconnection of the silicide layers formed on the surfaces of the n ⁺ type semiconductor region 6b for the source of nMIS (Qn) and the p ⁺ type semiconductor region 7b for the Vss potential feeding portion along all of the boundary portion 8. Even if the silicide layer is disconnected at a part of the boundary 8, the silicide layer is connected at the other part, so that the n ⁺ -type semiconductor region 6 b for the source of nMIS (Qn) It is possible to prevent the occurrence of electrical disconnection with the p ⁺ type semiconductor region 7b for the Vss potential power supply unit.

(Embodiment 2)
The structure of a 2-input NAND gate CMOS logic circuit employing the batting diffusion structure according to the second embodiment will be described with reference to FIGS. 13 is a plan view of a principal part showing a pMIS formation region and a Vdd potential power supply part constituting a 2-input NAND gate CMOS logic circuit. FIG. 14A is a sectional view of a principal part taken along line AA ′ of FIG. FIG. 14B is a sectional view taken along the line BB ′ of FIG. 13, and FIG. 14C is a sectional view taken along the line CC ′ of FIG. Here, the present invention will be described using pMIS, but the same applies to nMIS.

The difference from the first embodiment is that the p ⁺ type semiconductor region 7b for the source shared by the two pMISs (Qp) in the two-input NAND gate CMOS logic circuit and the n ⁺ type semiconductor for the Vdd potential power supply unit. The boundary portion 8 with the region 6b is not provided in the active region 3a for pMIS and the active region 3c for pMIS coupling, and extends in the second direction into the active region 3b for the Vdd potential feeding portion. It is formed. That is, the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) formed in the active region 3a for pMIS and the active region 3c for pMIS coupling and extending further extends to the active region 3b for the Vdd potential power supply unit. The active region 3c for pMIS coupling is formed with a predetermined length longer than the width (WBDp) along the second direction along the second direction.

In FIG. 13, a predetermined length (length along the second direction) and a predetermined width (length along the first direction) projecting toward the active region 3a side for pMIS in the active region 3b for the Vdd potential power supply unit And a p ⁺ type semiconductor for the source of pMIS (Qp), which is formed in the active region 3a for pMIS and the active region 3c for pMIS coupling, and extends further. Region 7b is formed. It is not always necessary to form this convex part. For example, the width of the active region 3b for the Vdd potential power supply unit is constant, the width is shorter than the width along the first direction of the active region 3b for the Vdd potential power supply unit, and the active region 3c for pMIS coupling is A p ⁺ type semiconductor for the source of pMIS (Qp) having a predetermined length longer than the width (WBDp) along the second direction and extending in the second direction into the active region 3b for the Vdd potential power supply unit Region 7b can be formed.

As described above, according to the second embodiment, the boundary portion 8 between the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential feeding portion is activated for pMIS. It is provided in the region 3a, and the length of the boundary portion 8 is longer than the width (WBDp) along the second direction of the active region 3c for pMIS coupling. Therefore, as in the first embodiment, the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential power supply unit along the entire boundary 8 are formed on the surface. The disconnection of the formed silicide layer can be prevented, and even if the silicide layer is disconnected at a part of the boundary portion 8, the silicide layer is connected at the other part, so that the source of pMIS (Qp) It is possible to prevent the occurrence of electrical disconnection between the p ⁺ type semiconductor region 7b for use and the n ⁺ type semiconductor region 6b for the Vdd potential feeding portion.

(Embodiment 3)
The structure of a 2-input NAND gate CMOS logic circuit employing the batting diffusion structure according to the third embodiment will be described with reference to FIGS. 15 is a plan view of a principal part showing a pMIS formation region and a Vdd potential power supply part constituting a 2-input NAND gate CMOS logic circuit, FIG. 16A is a sectional view of a principal part taken along line AA ′ of FIG. FIG. 16B is a cross-sectional view of main parts taken along the line BB ′ of FIG. 15, and FIG. 16C is a cross-sectional view of main parts taken along the line CC ′ of FIG. Here, the present invention will be described using pMIS, but the same applies to nMIS.

The difference from the first and second embodiments described above is that the p ⁺ type semiconductor region 7b for the source shared by the two pMIS (Qp) in the two-input NAND gate CMOS logic circuit and the n ⁺ for the Vdd potential power supply unit. The boundary 8 with the type semiconductor region 6b is not provided in the active region 3a for pMIS and the active region 3c for pMIS coupling, but is provided in the active region 3b for the Vdd potential power supply unit, The boundary portion 8 is formed in the active region 3b for the Vdd potential power supply portion in the same direction as the width of the active region 3b for the Vdd potential power supply portion in the first direction. That is, the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) formed in the active region 3a for pMIS and the active region 3c for pMIS coupling and extending further extends to the active region 3b for the Vdd potential power supply unit. And a predetermined length longer than the width (WBDp) along the second direction of the active region 3c for pMIS coupling.

As described above, according to the third embodiment, the boundary 8 between the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential feeding portion is defined as pMIS (Qp ) Is formed in the active region 3b for the Vdd potential power feeding portion apart from the gate electrode 4p, so that the influence of stress due to the gate electrode 4p of pMIS (Qp) can be reduced. Therefore, disconnection along the boundary portion 8 of the silicide layer formed on the surfaces of the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential feeding portion can be suppressed. since, it is possible to prevent the occurrence of electrical disconnection between the ^{p +} -type semiconductor regions 7b and Vdd ^{n +} -type semiconductor region 6b for potential power supply unit for the source of pMIS (Qp).

(Embodiment 4)
A structure of a 2-input NAND gate CMOS logic circuit employing the batting diffusion structure according to the fourth embodiment will be described with reference to FIGS. 17 is a principal plan view showing a pMIS formation region and a Vdd potential power supply portion constituting a two-input NAND gate CMOS logic circuit. FIG. 18A is a principal sectional view taken along line AA ′ of FIG. FIG. 18B is a sectional view taken along the line BB ′ in FIG. 17, and FIG. 18C is a sectional view taken along the line CC ′ in FIG. Here, the present invention will be described using pMIS, but the same applies to nMIS.

In the 2-input NAND gate CMOS logic circuit according to the fourth embodiment, the boundary between the p ⁺ type semiconductor region 7b for the source shared by the two pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential feeding portion 8 is the same as that of the third embodiment described above, and is provided in the active region 3b for the Vdd potential power supply unit, and the boundary 8 is in the first region in the active region 3b for the Vdd potential power supply unit. Along the direction, it is formed with the same width as the width of the active region 3b for the Vdd potential feeding portion. That is, the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) formed in the active region 3a for pMIS and the active region 3c for pMIS coupling and extending further extends to the active region 3b for the Vdd potential power supply unit. And a predetermined length longer than the width (WBDp) along the second direction of the active region 3c for pMIS coupling.

The difference from the third embodiment described above is that the contact hole 9a is on the boundary portion 8 between the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential feeding portion. In addition, it is formed across both.

As described above, according to the fourth embodiment, the silicide layer formed on the surface of the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential feeding portion is a boundary. Even if the disconnection occurs in the portion 8, the silicide layer formed on the surface of the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the silicide formed on the surface of the n ⁺ type semiconductor region 6b for the Vdd potential feeding portion Since electrical connection with the layer can be ensured, the occurrence of electrical disconnection between the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential feeding portion is prevented. be able to.

(Embodiment 5)
The structure of a 2-input NAND gate CMOS logic circuit employing the batting diffusion structure according to the fifth embodiment will be described with reference to FIGS. 19 is a plan view of a principal part showing a pMIS formation region and a Vdd potential power supply part constituting a two-input NAND gate CMOS logic circuit, FIG. 20A is a sectional view of a principal part taken along the line AA ′ of FIG. FIG. 20B is a main part sectional view taken along line BB ′ of FIG. 19, and FIG. 20C is a main part sectional view taken along line CC ′ of FIG. Here, the present invention will be described using pMIS, but the same applies to nMIS.

In the two-input NAND gate CMOS logic circuit according to the fifth embodiment, the boundary between the p ⁺ type semiconductor region 7b for the source shared by the two pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential feeding portion 8 is the same as that of the third embodiment described above, and is provided in the active region 3b for the Vdd potential power supply unit, and the boundary 8 is in the first region in the active region 3b for the Vdd potential power supply unit. Along the direction, it is formed with the same width as the width of the active region 3b for the Vdd potential feeding portion. That is, the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) formed in the active region 3a for pMIS and the active region 3c for pMIS coupling and extending further extends to the active region 3b for the Vdd potential power supply unit. And a predetermined length longer than the width (WBDp) along the second direction of the active region 3c for pMIS coupling.

The difference from the third embodiment described above is that the contact hole 9b has a p ⁺ type semiconductor region 7b for the source of pMIS (Qp) formed in the active region 3b for the Vdd potential power supply portion, and a Vdd potential power supply portion. And n ⁺ -type semiconductor region 6b. The contact hole 9b has a boundary 8 between the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential feeding portion, as described in the fourth embodiment. Above, it is not formed across both.

As described above, according to the fifth embodiment, the silicide layer formed on the surfaces of the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential feeding portion is a boundary. Even if the disconnection occurs in the portion 8, the silicide layer formed on the surface of the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the silicide formed on the surface of the n ⁺ type semiconductor region 6b for the Vdd potential feeding portion Since electrical connection with the layer can be ensured, the occurrence of electrical disconnection between the p ⁺ type semiconductor region 7b for the source of pMIS (Qp) and the n ⁺ type semiconductor region 6b for the Vdd potential feeding portion is prevented. be able to.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the present embodiment, the batting diffusion structure employed in the 2-input NAND gate CMOS logic circuit has been described. However, the present invention is not limited to the 2-input NAND gate CMOS logic circuit, and other CMOS logic circuits (for example, inverters) Circuit, NOR circuit, AND circuit, NOR circuit, etc.) or CMOS logic circuit, and can be applied to any semiconductor element having a batting diffusion structure in which an n-type semiconductor region and a p-type semiconductor region are directly connected. it can.

  The present invention is implemented in a semiconductor device including a semiconductor element having a batting diffusion structure in which an n-type diffusion region (impurity region, semiconductor region) and a p-type diffusion region (impurity region, semiconductor region) are in contact with each other. it can.

1 is a circuit diagram of a 2-input NAND gate CMOS logic circuit according to a first embodiment of the present invention. FIG. 1 is a plan view of a principal part showing one example of a 2-input NAND gate CMOS logic circuit according to a first embodiment of the present invention; FIG. (A) And (b) is a principal part top view which shows the other example of the 2-input NAND gate CMOS logic circuit by Embodiment 1 of this invention, respectively. 2A is a sectional view taken along the line AA ′ in FIG. 2, FIG. 2B is a sectional view taken along the line BB ′ in FIG. 2, and FIG. 2C is a sectional view taken along the line CC ′ in FIG. FIG. It is principal part sectional drawing which shows the manufacturing process of the 2 input NAND gate CMOS logic circuit which employ | adopted the batting diffusion structure by Embodiment 1 of this invention. FIG. 6 is a fragmentary cross-sectional view of the same place as that in FIG. 5 during the manufacturing process of the 2-input NAND gate CMOS logic circuit following FIG. 5; FIG. 7 is a fragmentary cross-sectional view of the same place as that in FIG. 5 during a manufacturing process of the 2-input NAND gate CMOS logic circuit following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the same place as that in FIG. 5 during the manufacturing process of the 2-input NAND gate CMOS logic circuit following FIG. 7; FIG. 9 is a fragmentary cross-sectional view of the same place as that in FIG. 5 during the manufacturing process of the 2-input NAND gate CMOS logic circuit following FIG. 8; FIG. 10 is a fragmentary cross-sectional view of the same place as that in FIG. 5 during the manufacturing process of the 2-input NAND gate CMOS logic circuit following FIG. 9; FIG. 11 is a fragmentary cross-sectional view of the same place as that in FIG. 5 during the manufacturing process of the 2-input NAND gate CMOS logic circuit following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the same place as that in FIG. 5 during the manufacturing process of the 2-input NAND gate CMOS logic circuit following FIG. 11; It is a principal part top view which shows an example of the 2 input NAND gate CMOS logic circuit by Embodiment 2 of this invention. 13A is a sectional view taken along the line AA ′ in FIG. 13, FIG. 13B is a sectional view taken along the line BB ′ in FIG. 13, and FIG. 13C is a sectional view taken along the line CC ′ in FIG. FIG. It is a principal part top view which shows an example of the 2 input NAND gate CMOS logic circuit by Embodiment 3 of this invention. 15A is a sectional view taken along the line AA ′ in FIG. 15, FIG. 15B is a sectional view taken along the line BB ′ in FIG. 15, and FIG. 15C is a sectional view taken along the line CC ′ in FIG. FIG. It is a principal part top view which shows an example of the 2 input NAND gate CMOS logic circuit by Embodiment 4 of this invention. 17A is a sectional view taken along the line AA ′ of FIG. 17, FIG. 17B is a sectional view taken along the line BB ′ of FIG. 17, and FIG. 17C is a sectional view taken along the line CC ′ of FIG. FIG. It is a principal part top view which shows an example of the 2 input NAND gate CMOS logic circuit by Embodiment 5 of this invention. 19A is a sectional view taken along line AA ′ in FIG. 19, FIG. 19B is a sectional view taken along line BB ′ in FIG. 19, and FIG. 19C is a sectional view taken along line CC ′ in FIG. FIG. It is a principal part top view which shows an example of the 2 input NAND type CMOS logic circuit which employ | adopted the batting diffusion structure examined by the present inventors. (A) is a principal part top view which shows the example of a defect of the batting diffusion structure examined by the present inventors, (b) is principal part sectional drawing in the DD 'line | wire of the figure (a).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 2a Groove 2b Insulating film 3a Active region for pMIS 3b Active region for Vdd potential feeding part 3c Active region for pMIS coupling 4, 4n, 4p Gate electrode 4a Silicon film 5a Active region for nMIS 5b Active region for Vss potential feeding portion 5c Active region for nMIS coupling 6a n ⁻ type semiconductor region 6b n ⁺ type semiconductor region 7a p ⁻ type semiconductor region 7b p ⁺ type semiconductor region 8 Boundary portion 9 Contact hole 10n n well 10p p well 11 gate insulating film 12 sidewall 13 metal silicide layers 14a and 14b insulating film 14 interlayer insulating film 15 plug 15a barrier conductor film 15b main conductor film 16 wiring 17 insulating film 18 cobalt silicide layer 51 semiconductor substrate 52a active region for pMIS 52b Active region 5 for Vdd potential feeder 3c pMIS coupling active region 54 p-type semiconductor region 55 n-type semiconductor region 56 boundary 57 gate electrode 58a nMIS active region 58b Vss potential supply region active region 58c nMIS coupling active region 59 n-type semiconductor region 60 p-type semiconductor region 61 boundary 62 contact hole A, B input terminal Qn n-channel MISFET
Qp p-channel MISFET
Y output terminal

Claims (21)

A first active region surrounded by an element isolation region in which a field effect transistor is formed in a semiconductor substrate; a second active region surrounded by an element isolation region in which a potential feeding portion extending in a second direction is formed; A third active region for coupling surrounded by an element isolation region connecting the first active region and the second active region arranged in a first direction orthogonal to the second direction;
A first conductivity type first semiconductor region for a source or drain of the field effect transistor, and a second conductivity type second semiconductor region opposite to the first conductivity type for the potential power supply unit,
The first semiconductor region and the second semiconductor region are in direct contact with each other, and the first semiconductor region and the second semiconductor region are formed by a silicide layer formed on a surface of the first semiconductor region and a surface of the second semiconductor region. Are electrically connected semiconductor devices,
A boundary portion between the first semiconductor region and the second semiconductor region is formed in the first active region, and the second semiconductor region is not only the second active region and the third active region, The semiconductor device is also formed in a part of the first active region.   2. The semiconductor device according to claim 1, wherein a length of the boundary portion formed in the first active region is longer than a width of the third active region along the second direction. A semiconductor device.   2. The semiconductor device according to claim 1, wherein the boundary portion formed in the first active region extends in the first direction and is an end of the first active region located on a side opposite to the third active region. A semiconductor device characterized by reaching a part. A first active region surrounded by an element isolation region in which a field effect transistor is formed in a semiconductor substrate; a second active region surrounded by an element isolation region in which a potential feeding portion extending in a second direction is formed; A third active region for coupling surrounded by an element isolation region connecting the first active region and the second active region arranged in a first direction orthogonal to the second direction;
A first conductivity type first semiconductor region for a source or drain of the field effect transistor, and a second conductivity type second semiconductor region opposite to the first conductivity type for the potential power supply unit,
The first semiconductor region and the second semiconductor region are in direct contact with each other, and the first semiconductor region and the second semiconductor region are formed by a silicide layer formed on a surface of the first semiconductor region and a surface of the second semiconductor region. Are electrically connected semiconductor devices,
A boundary portion where the first semiconductor region and the second semiconductor region are in contact is formed in the second active region, and the first semiconductor region is not only the first active region and the third active region, The semiconductor device is also formed in a part of the second active region.   5. The semiconductor device according to claim 4, wherein the first semiconductor region formed in the second active region has a width shorter than a width along the first direction of the second active region, and 3. A semiconductor device, wherein the active region is formed to extend in the second direction with a predetermined length longer than a width along the second direction of the active region.   5. The semiconductor device according to claim 4, wherein the first semiconductor region formed in the second active region has the same width as the width along the first direction of the second active region, and the third semiconductor region. A semiconductor device, wherein the semiconductor device is formed to extend in the second direction with a predetermined length longer than a width along the second direction of the active region.   7. The semiconductor device according to claim 6, wherein a contact hole is formed on a boundary portion between the first semiconductor region and the second semiconductor region formed in the second active region. A semiconductor device characterized by being formed across a semiconductor region.   7. The semiconductor device according to claim 6, wherein contact holes are respectively formed on the first semiconductor region and the second semiconductor region formed in the second active region, and the first semiconductor region. And a semiconductor device, wherein the semiconductor device is not formed across the second semiconductor region.   5. The semiconductor device according to claim 1, wherein the first active region, the second active region, and the third active region are formed in the second conductivity type well formed in the semiconductor substrate. The semiconductor device is characterized in that the second semiconductor region and the well are connected.   5. The semiconductor device according to claim 1, wherein the silicide layer is a cobalt silicide layer, a nickel silicide layer, or a titanium silicide layer.   5. The semiconductor device according to claim 1, wherein a gate electrode of the field effect transistor extends in the first direction and is formed in the first active region. (A) a first active region for a field effect transistor surrounded by an element isolation region, a second active region for a potential feeder extending in a second direction, and the second direction on the main surface of the semiconductor substrate; Forming a third active region for bonding that connects the first active region and the second active region located in a first direction orthogonal to
(B) introducing a second conductivity type impurity into the semiconductor substrate to form the second conductivity type well in the first active region, the second active region, and the third active region;
(C) forming a gate insulating film of the field effect transistor on the surface of the semiconductor substrate in the first active region;
(D) forming a gate electrode of the field effect transistor on the gate insulating film of the first active region;
(E) forming a first semiconductor region for the source or drain of the field effect transistor made of an impurity of the first conductivity type opposite to the second conductivity type by ion implantation in a part of the first active region; And a process of
(F) Impurities of the second conductivity type are formed by ion implantation into another part of the first active region where the first semiconductor region is not formed, the second active region, and the third active region. Forming a second semiconductor region for the potential power supply portion, and forming a boundary portion where the first semiconductor region and the second semiconductor region are in contact with each other in the first active region;
(G) forming a silicide layer on the surfaces of the first active region, the second active region, and the third active region.   13. The method of manufacturing a semiconductor device according to claim 12, wherein a length of the boundary portion formed in the first active region is longer than a width of the third active region along the second direction. A method for manufacturing a semiconductor device.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the boundary portion formed in the first active region extends in the first direction and is located on the opposite side to the third active region. A method of manufacturing a semiconductor device, characterized by reaching an end of a region. (A) a first active region for a field effect transistor surrounded by an element isolation region, a second active region for a potential feeder extending in a second direction, and the second direction on the main surface of the semiconductor substrate; Forming a third active region for bonding that connects the first active region and the second active region located in a first direction orthogonal to
(B) introducing a second conductivity type impurity into the semiconductor substrate to form the second conductivity type well in the first active region, the second active region, and the third active region;
(C) forming a gate insulating film of the field effect transistor on the surface of the semiconductor substrate in the first active region;
(D) forming a gate electrode of the field effect transistor on the gate insulating film of the first active region;
(E) By the ion implantation method, the field effect of the first active region, the part of the second active region, and the third active region having the first conductivity type opposite to the second conductivity type. Forming a first semiconductor region for a source or drain of a transistor;
(F) forming a second semiconductor region for the potential feeding portion made of the impurity of the second conductivity type by ion implantation in another part of the second active region where the first semiconductor region is not formed; Forming a boundary in the second active region where the first semiconductor region and the second semiconductor region are in contact with each other;
(G) forming a silicide layer on the surfaces of the first active region, the second active region, and the third active region.   16. The method of manufacturing a semiconductor device according to claim 15, wherein the first semiconductor region formed in the second active region has a width shorter than a width along the first direction of the second active region, and A method of manufacturing a semiconductor device, wherein the semiconductor device is formed with a predetermined length longer than a width of the third active region along the second direction.   16. The method of manufacturing a semiconductor device according to claim 15, wherein the first semiconductor region formed in the second active region has the same width as the width along the first direction of the second active region, and A method of manufacturing a semiconductor device, wherein the third active region is formed to extend in the second direction with a predetermined length longer than a width along the second direction of the third active region. 18. The method of manufacturing a semiconductor device according to claim 17, further comprising the step (g):
(H) forming an interlayer insulating film on the semiconductor substrate including the surface of the silicide layer;
(I) forming a plurality of contact holes reaching the silicide layer in the interlayer insulating film,
Forming the contact hole straddling the first semiconductor region and the second semiconductor region on a boundary portion between the first semiconductor region and the second semiconductor region formed in the second active region; A method of manufacturing a semiconductor device. 18. The method of manufacturing a semiconductor device according to claim 17, further comprising the step (g):
(H) forming an interlayer insulating film on the semiconductor substrate including the surface of the silicide layer;
(I) forming a plurality of contact holes reaching the silicide layer in the interlayer insulating film,
The contact holes are formed on the first semiconductor region and the second semiconductor region formed in the second active region, respectively, and straddle the first semiconductor region and the second semiconductor region. A method for manufacturing a semiconductor device, wherein no contact hole is formed.   16. The method of manufacturing a semiconductor device according to claim 12, wherein the silicide layer is a cobalt silicide layer, a nickel silicide layer, or a titanium silicide layer.   16. The method of manufacturing a semiconductor device according to claim 12, wherein a gate electrode of the field effect transistor extending in the first direction is formed in the first active region.

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