JP2009021514A - Multilayer thin film capacitor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer thin film capacitor wherein the reliability of connection is not lowered even when the number of layers is increased, and to provide its manufacturing method. <P>SOLUTION: In the multilayer thin film capacitor 10, a plurality of electrodes 12A belonging to one group, dielectric layers 13 and electrodes 12B belonging to the other group are alternately laminated on a substrate 11. On one end side of an opposite region, a first connection part for which the plurality of electrodes belonging to one group are piled up with each other is provided. Also, on the other end side of the opposite region, a second connection part for which the plurality of electrodes belonging to the other group are piled up with each other is provided. Only on the first connection part and the second connection part, a thickness adjusting conductor layer for alleviating a level difference from the opposite region is each piled up. Thus, the level difference between the connection parts and the opposite region is alleviated, and the number of lamination is increased without lowering the reliability of the connection. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multilayer thin film capacitor capable of stable production even when the number of stacked layers is increased, and a method for manufacturing the same.

Conventionally, a multilayer thin film capacitor using a dielectric thin film as a dielectric layer has been proposed. For example, Patent Document 1 discloses a method for manufacturing a multilayer dielectric thin film capacitor in which an electrode and a dielectric thin film are formed on a substrate by a film forming method using a mask. Specifically, a mask that covers the opposite side edges of the substrate and has an opening is disposed at a predetermined interval facing the substrate, and the dielectric is disposed so as to face the substrate across the mask. A material deposition source is disposed, a pair of conductor material deposition sources are disposed in the opposite side edge direction of the substrate with the dielectric material deposition source interposed therebetween, and the materials of the conductor material deposition source are alternately deposited. At the same time, the conductor material deposition source and the dielectric material deposition source are alternately evaporated, and the electrodes 212A and 212B and the dielectric layer 213 are alternately stacked on the substrate 211 as shown in FIG. A method of manufacturing a multilayer dielectric thin film capacitor in which every other electrode 212A, 212B is connected to each other has been proposed.
Further, in Patent Document 2, the pattern size on the evaporation source side is made smaller than the side of the mask that contacts the substrate, and the gap between the substrate and the mask edge is further increased compared to the former background art, As shown in FIG. 15, a method of manufacturing a thin film multilayer capacitor is proposed in which the edge portion of the attached film is smoothed and at the same time the cut is eliminated.
Japanese Examined Patent Publication No. 38-21426 Japanese Patent Laid-Open No. 5-251259

However, in the multilayer dielectric thin film capacitor of the former background art, as the number of stacked layers inside the multilayer dielectric thin film capacitor increases, a facing region where the electrodes face each other with the dielectric thin film interposed therebetween, and a periphery of the facing region The difference in thickness between the electrode and the electrode region formed by vapor deposition on the inclined surface is increased. There was a problem that the connection reliability was lowered due to a decrease in thickness.
For the purpose of improving the moisture resistance of the element, etc., when the multilayer dielectric thin film capacitor is covered with an SiO ₂ insulating layer or the like and an extraction electrode penetrating the insulating layer is provided, the thick opposing region Since the opening reaching the connection portion is provided in the insulating layer portion very close to the substrate, the reliability of the element may be lowered.
Further, in the method of manufacturing the multilayer dielectric thin film capacitor, when the number of stacked layers is increased as described above, the line connecting the electrode material deposition source and the connecting portion that connects the electrodes alternately to each other. Further, the opposing region with the increased number of stacked layers protrudes to cause a shadow during film formation. For this reason, the thickness dimension of the electrode varies, and there is a problem that stable production is difficult.
Further, in the latter method for manufacturing a thin film multilayer capacitor of the background art, when the number of stacked layers is increased, the positional accuracy of the edge portion of each layer is lowered, so that there is a problem that further multilayering is difficult.

The present invention focuses on the above points, and an object of the present invention is to provide a multilayer thin film capacitor in which connection reliability does not decrease even when the number of stacked layers increases. It is another object of the present invention to provide a method for manufacturing a multilayer thin film capacitor capable of stable production without variation in electrode thickness dimension even when the number of stacked layers is increased.

In order to achieve the above object, the present invention provides: (1) an electrode belonging to one group and a dielectric so that the electrode belonging to one group and the electrode belonging to the other group face each other with a dielectric layer interposed therebetween; A multilayer thin film capacitor in which a plurality of layers and electrodes belonging to the other group are alternately stacked on one main surface side of the substrate, and the electrodes belonging to one group and the other group sandwiching the dielectric layer One end side of the opposing region facing the belonging electrode has a first connecting portion in which a plurality of electrodes belonging to the one group are overlapped with each other, and the other end side of the opposing region has the other side A thickness-adjusting conductor that has a second connecting portion in which a plurality of electrodes belonging to a group are overlapped with each other, and the first connecting portion and the second connecting portion further relieve a step from the facing region Each layer is Crafted wherein the are. (... hereinafter referred to as first problem solving means)

In addition to the first problem-solving means, one of the main embodiments of the present invention further includes: (2) an insulating layer covering the first connection portion to the second connection portion. And an extraction electrode penetrating the insulating layer is provided on each of the first connection portion and the second connection portion. (... hereinafter referred to as second problem solving means)

The present invention also includes (3) a step of forming an electrode belonging to one group on the substrate, and a step of forming a dielectric layer so as to cover the electrode belonging to the one group except for one end side. A step of forming an electrode belonging to the other group from above the dielectric layer to the substrate on the other end side of the dielectric layer, and an electrode belonging to the other group excluding the other end side. Forming a dielectric layer so as to cover the electrode, and an opposing region in which the electrode belonging to the one group and the electrode belonging to the second group face each other across the dielectric layer from above the dielectric layer Forming an electrode belonging to the one group over the electrode belonging to the one group on one end side to form a first connection portion; and belonging to the one group with the dielectric layer interposed therebetween Electric Forming a dielectric layer so as to cover the opposing region where the electrodes belonging to the second group face each other except for one end of the opposing region; Forming a second connecting portion by re-forming the electrode belonging to the other group over the electrode belonging to the other group on the end side, and a method of manufacturing a multilayer thin film capacitor, comprising:
Forming a thickness adjusting conductor layer on the first connecting portion to further reduce the step with the facing region; and adjusting the thickness on the second connecting portion to further reduce the step with the facing region. And a step of forming a conductive layer for each. (... hereinafter referred to as third problem solving means)

The operation of the first problem solving means is as follows. That is, the first electrode in which the electrodes belonging to one group and the electrodes belonging to the other group are opposed to each other across the dielectric layer is overlapped with each other. It has a connection part. Moreover, the other end side of the opposing region has a second connection portion in which a plurality of electrodes belonging to the other group are overlapped with each other. Further, a conductor layer for adjusting the thickness that relaxes the step with the opposing region is overlaid on each of the first connection portion and the second connection portion. For this reason, the level | step difference of the said connection part and the said opposing area | region is eased, and the number of lamination | stacking can be increased, without reducing the reliability of a connection.

The operation of the second problem solving means is as follows. That is, it has an insulating layer covering the first connecting portion and the second connecting portion, and penetrates the insulating layer on each of the first connecting portion and the second connecting portion. An extraction electrode is provided. For this reason, since the connection portion on one end side and the other end side of the facing region is brought close to the thickness of the facing region, even if an opening is provided in the insulating layer close to the facing region, it is reliable. The possibility that the performance is lowered is reduced.

The operation of the third problem solving means is as follows. That is, a step of forming a conductive layer for thickness adjustment that further relaxes the step with the facing region on the first connecting portion, and a step with the facing region that is further relaxed on the second connecting portion. Forming a conductor layer for adjusting the thickness. For this reason, it is possible to avoid the opposing region from protruding on a straight line connecting the connection portion and the electrode material deposition source, and an electrode having a uniform thickness can be stably formed.
The above and other objects, features, and advantages of the present invention will be apparent from the following detailed description and the accompanying drawings.

  According to the first problem solving means of the present invention, the number of stacked layers can be increased, and a large-capacity stacked thin film capacitor can be provided. Further, according to the second problem solving means of the present invention, it is possible to realize a multilayer thin film capacitor that does not have a risk of lowering reliability due to the opening for providing the extraction electrode. According to the third problem solving means of the present invention, the multilayer thin film capacitor can be produced stably.

  Next, a first embodiment of the multilayer thin film capacitor of the present invention will be described with reference to FIG. FIG. 1 is a schematic cross-sectional view for explaining the internal structure of the multilayer thin film capacitor 10 of the first embodiment.

As shown in FIG. 1, the multilayer thin film capacitor 10 of the first embodiment includes a substrate 11, an element body 14 of the multilayer thin film capacitor formed on the substrate 11, and an insulation that covers the element body 14. It has the layer 16 and the extraction electrode 17 which penetrates this insulating layer 16 in the thickness direction.
Specifically, in the multilayer thin film capacitor 10 of this embodiment, the electrodes 12A1, 12A2 belonging to one group and the electrodes 12B1, 12B2 belonging to the other group are opposed to each other with the dielectric layers 13a, 13b, 13c interposed therebetween. As described above, the electrodes 12A1, 12A2 belonging to the one group, the dielectric layers 13a, 13b, 13c and the electrodes 12B1, 12B2 belonging to the other group are alternately stacked on one main surface side of the substrate 11. . Then, the electrode 12A1, 12A2 belonging to one group and the electrodes 12B1, 12B2 belonging to the other group are opposed to one end side of the opposing region OA across the dielectric layers 13a, 13b, 13c. A plurality of electrodes 12A1, 12A2 belonging to the first connection portion 12AC overlaid on each other. In addition, a second connection portion 12BC in which a plurality of electrodes 12B1.12B2 belonging to the other group are overlapped with each other is provided on the other end side of the counter area OA. Further, only the first connection portion 12AC and the second connection portion 12BC are further overlapped with thickness adjusting conductor layers 15a and 15b for relaxing a step with the facing area OA.

More specifically, the substrate 11 includes a silicon substrate 11a and a SiO ₂ insulating layer 11b formed on the silicon substrate 11a. The thickness of the silicon substrate 11a can be arbitrarily selected, and the thickness of the SiO ₂ insulating layer 11b is 3 μm, for example.

The element body 14 includes a plurality of electrodes 12A1 and 12A2 belonging to one group and a plurality of electrodes 12B1 and 12B2 belonging to the other group. Also, a dielectric layer 13a is provided between the electrode 12A1 belonging to the one group and the electrode 12B1 belonging to the other group. Also, a dielectric layer 13b is provided between the other electrode 12B1 and the one electrode 12A2. Further, a dielectric layer 13c is provided between the electrode 12A2 belonging to the one group and the electrode 12B2 belonging to the other group. For example, the thicknesses of the electrodes 12A belonging to the first group are 150 nm, the electrodes 12B belonging to the second group are 150 nm, and the dielectric layer 13 is 250 nm.

Also, the thickness adjusting conductor layer 15a overlaid on the first connecting portion 12AC is made of the same material as the electrodes 12A1 and 12A2 belonging to the one group, and the height of the upper surface thereof is adjusted. The height of the upper surface of the opposing region OA of the electrode 12A2 belonging to the one group, which is the base layer on which the conductor layer 15a is formed, is substantially equal. Similarly, the thickness adjusting conductor layer 15b overlaid on the second connecting portion 12BC is made of the same material as the electrodes 12B1 and 12B2 belonging to the other group, and the height of the upper surface thereof is adjusted. The height of the upper surface of the opposing region OA of the electrode 12B2 belonging to the other group serving as the base layer on which the conductive layer 15b is formed is substantially equal.

Further, in the multilayer thin film capacitor 10 of the present embodiment, an insulating layer that covers the element body 14 from the first connection portion 12AC to the second connection portion 12BC through the opposing region OA. 16 The insulating layer 16 includes a first insulating layer 16a made of Al ₂ O ₃ covering the element body 14 on the substrate 11 and a _second insulating layer 16 made of SiO ₂ covering the first insulating layer 16a. The insulating layer 16b includes a third insulating layer 16c made of SiN and covering the second insulating layer 16b. The thickness of the first insulating layer is 150 nm, the thickness of the second insulating layer is 3 μm, and the thickness of the third insulating layer is 200 nm.
Lead electrodes 17 and 17 penetrating the insulating layer 16 in the thickness direction are provided on the first connection portion 12AC and the second connection portion 12BC, respectively, and are connected to the connection portions 12AC and 12BC, respectively. Has been.

Next, an example of an embodiment of a method for manufacturing the multilayer thin film capacitor 10 of the present invention will be described with reference to FIGS. FIG. 2 is a schematic diagram for explaining the internal arrangement of the chamber of the film forming apparatus used in the method for manufacturing the multilayer thin film capacitor 10 of the present embodiment. FIG. 3 is a plan view showing an example of a mask used for forming the element body 14 in the method for manufacturing the multilayer thin film capacitor 10 of the present embodiment. 4 to 11 are schematic diagrams for explaining an example of the manufacturing process of the manufacturing method of the multilayer thin film capacitor 10 of this embodiment step by step.

The chamber 20 of the film forming apparatus used in the method for manufacturing the multilayer thin film capacitor of the present embodiment will be described by taking as an example the case of using it for film formation of electrodes. The chamber 20 is a box-shaped film forming chamber, and the substrate 11 is placed on the bottom of the chamber 20. An electrode film-forming mask 32 is held above the substrate 11 with a predetermined interval, for example, via a spacer (not shown). Next, the film formation mask 32 of the electrode 12A belonging to one group and the electrode 12B belonging to the other group of the multilayer thin film capacitor 10 of the present embodiment has a substantially rectangular plate shape as shown in FIG. In order to form a plurality of capacitor units on the substrate at the same time, a plurality of rectangular openings 32b having the same shape are arranged so that diagonal lines of the respective openings 32b are parallel to each other. In addition, the film formation mask 33 of the dielectric layer 13 made of, for example, BST of the multilayer thin film capacitor 10 of the present embodiment is substantially similar to the electrode film formation mask 32 as shown in FIG. A plurality of rectangular openings 33b having the same shape are arranged in a rectangular plate-shaped frame portion 33a so that diagonal lines of the openings 33b are parallel to each other. The opening 33 b of the film formation mask 33 of the dielectric layer 13 is configured to have substantially the same size and shape as the opening 32 b of the electrode film formation mask 32. Further, as shown in FIG. 3C, the film forming mask 35 for the conductor layer 15 for adjusting the thickness is formed on the substantially rectangular plate-shaped frame portion 35a and the electrode film forming mask 32 and the dielectric layer are formed. A plurality of key-shaped openings 35b are provided along two adjacent sides of the plurality of rectangular openings 32b and 33b provided in the mask 33 for use. A target 22A made of, for example, Pt for forming the electrode 12A belonging to one group is disposed diagonally to the right above the substrate 11 in the chamber 20. Similarly, a target 22B made of, for example, Pt for forming the electrode 12B belonging to the other group is disposed obliquely above and to the left of the inside 20 of the chamber. The target 22 </ b> A and the target 22 </ b> B are respectively disposed so as to sandwich the substrate 11 on a straight line passing through the substrate 11 and parallel to the diagonal line of each opening of the deposition masks 32 and 33. A target 23 made of, for example, BST for forming the dielectric layer 13 and a target 25 made of, for example, Pt for forming the thickness adjusting conductor layer 15 are opposed to the substrate 11 above the chamber 20. It is arranged at the position to do. 2, for the sake of convenience, the targets 22A, 22B, 23, and 25 are disposed in the same chamber 20, but the present invention is not limited to this. For example, the targets 22A, 22B, An individual chamber may be provided for each of 23 and 25, and each of the targets 22A, 22B, 23, and 25 may be disposed at the same position in each chamber. In this case, it is preferable to provide a transport means for transporting the substrate 11 between the plurality of chambers.

Next, an example of the manufacturing process of the manufacturing method of the multilayer thin film capacitor 10 of this embodiment will be described step by step. (Step 1) First, as shown in FIG. 4A, for example, SiO ₂ or the like in advance for the purpose of improving the adhesion with the electrode 12A to be formed next on one main surface of the silicon substrate 11a. The substrate 11 on which the insulating film 11b is formed is prepared. (Step 2) Next, as shown in FIG. 4B, the electrode film forming mask 32 is arranged on the substrate 11 to form the electrode 12A1 belonging to one group. 4B, the film forming material source side of the frame portion 32a of the electrode film forming mask 32 is formed wider than the side in contact with the substrate 11. In FIG. As described above, a spacer for separating the substrate 11 and the electrode film forming mask 32 from the electrode film forming mask 32 is integrated with the electrode film forming mask so as to have both functions. The present invention is not limited to this. For example, a mask having a frame portion having the same width on the side in contact with the substrate and the film forming material source side is spaced apart from the substrate by a predetermined spacer. Of course, they may be placed apart. As described above, the mask 32 is substantially held at a position separated from the substrate 11, so that the electrode 12 </ b> A <b> 1 belonging to one group formed on the substrate 11 is the electrode deposition mask 32. It is formed at a position displaced slightly to the left along the diagonal line of the opening 32b of the mask 32 compared to the position of the opening 32b. (Step 3) Next, the substrate 11 on which the electrode 12A1 is formed is placed in the chamber 20 in the same manner as described above, and the dielectric layer deposition mask 33 is substantially separated from the substrate 11. A target made of BST, for example, for forming a dielectric layer (not shown) is disposed vertically above the substrate 11 and held in position. Then, as shown in FIG. 4C, the dielectric layer 13a is formed so as to cover the electrode 12A1 belonging to the one group except for one end side. At this time, since the dielectric layer deposition target (not shown) is arranged vertically above the substrate 11 with the mask 33 in between, the dielectric layer 13 a is along the diagonal line of the mask 32. It is formed without being displaced left and right. (Step 4) Next, the substrate 11 on which the dielectric layer 13a is formed is placed in the chamber 20 in the same manner as described above, and the electrode film forming mask 32 is substantially separated from the substrate 11. The Pt target (not shown) is disposed at an upper left position of the substrate 11. Then, as shown in FIG. 5D, an electrode 12B1 belonging to the other group is formed from the dielectric layer 13a to the substrate 11 on the other end side of the dielectric layer 13a. At this time, since the mask 32 is substantially held at a position separated from the substrate 11, the electrode 12B1 belonging to the other group has an opening 32b of the mask 32 compared to the position of the opening 32b of the mask 32. It is formed at a position displaced slightly to the right along the diagonal line. As described above, the electrode 12A1 belonging to the one group and the electrode 12B1 belonging to the other group are on the left side along the diagonal line of the opening 32b of the electrode film formation mask 32 with the dielectric layer 13a formation position therebetween. And right and left sides, respectively. Therefore, even if the size and shape of each opening 32b of the electrode film forming mask 32 and the size and shape of each opening 33b of the dielectric layer film forming mask 33 are substantially equal, they belong to the one group. The electrode 12A1 and the electrode 12B1 belonging to the other group are prevented from contacting each other. (Step 5) Next, in the same manner as in Step 3, as shown in FIG. 5E, the dielectric layer 13b is coated so as to cover the electrode 12B1 belonging to the other group except for the other end side. Form. (Step 6) Next, as in step 2 above, as shown in FIG. 5 (f), the electrode 12A belonging to the one group with the dielectric layer 13b sandwiched from the dielectric layer 13b and the The electrode 12A2 belonging to the one group is formed again over the electrode 12A1 belonging to the one group on one end side of the counter area OA facing the electrode 12B belonging to the second group, and the first connection portion 12AC is formed. Form. (Step 7) Next, the substrate 11 on which the electrode 12A2 is formed is placed in the chamber 20 in the same manner as described above, and the conductor layer film-forming mask 35 for adjusting the thickness with respect to the substrate 11 substantially. Is held at a spaced position, and a target made of, for example, Pt for forming a conductor layer for adjusting the thickness (not shown) is disposed vertically above the substrate 11. Then, as shown in FIG. 6G, a thickness adjusting conductor layer 15a is further formed only on the first connection portion 12AC to relieve a step difference from the counter area OA. The thickness of the thickness adjusting conductor layer 15a is, for example, 400 nm. (Step 8) Next, as in step 3 above, as shown in FIG. 6 (h), an electrode belonging to the one group and an electrode belonging to the second group are sandwiched between the dielectric layers. The dielectric layer 13c is formed so as to cover the electrode 12A2 belonging to the one group of the opposing region OA facing each other except one end side having the first connection portion 12AC on which the conductive layer 15a for adjusting the thickness is formed. Form. (Step 9) Next, as in step 4 above, as shown in FIG. 6 (i), on the electrode 12B1 belonging to the other group on the other end side of the counter area OA from the dielectric layer 13c. Then, the electrode 12B2 belonging to the other group is formed to form the second connection portion 12BC. (Step 10) Next, the substrate 11 on which the electrode 12B2 belonging to the other group is formed is placed in the chamber 20 in the same manner as in Step 7, and the conductor layer for thickness adjustment used in Step 7 is formed. After the mask 35 is rotated 180 degrees on the same plane and the position of the key-shaped opening 35b is moved, the conductor layer for adjusting the thickness is substantially formed on the substrate 11 in the same manner as in step 7 above. The target mask 35 is held at a separated position, and a target made of, for example, Pt for forming a thickness adjusting conductor layer (not shown) is disposed vertically above the substrate 11. Then, as shown in FIG. 7 (j), a thickness adjusting conductor layer 15b is formed on the second connection portion 12BC only to further reduce the step with the counter area OA. The thickness of the thickness adjusting conductor layer 15b is, for example, 400 nm. As a result, the element body 14 of the multilayer thin film capacitor 10 is formed on the substrate 11.

In the present embodiment, the insulating layer 16 that covers the element body 14 of the multilayer thin film capacitor 10 and the extraction electrode 17 that penetrates the insulating layer 16 in the thickness direction are formed as necessary. It has the following steps. (Step 11) As shown in FIG. 7 (k), a first insulating layer 16a made of Al ₂ O _{3 is} formed by, for example, sputtering so as to cover the element body 14 of the multilayer thin film capacitor on the substrate 11. To do. The thickness of the first insulating layer 16a is, for example, 150 nm. (Step 12) Next, as shown in FIG. 7L, a _second insulating layer 16b made of SiO ₂ is formed on the first insulating layer 16a by, eg, CVD. The thickness of the second insulating layer 16b is 3 μm, for example. (Step 13) Next, as shown in FIG. 8 (m), a resist layer 18a having a predetermined opening pattern is formed on the second insulating layer 16b. The thickness of the resist layer 18a is, for example, 1.5 μm. (Step 14) Next, as shown in FIG. 8 (n), by using the resist layer 18a as a mask, the _second layer made of SiO _{2 is formed} by RIE using C ₄ F ₈ / O ₂ / Ar gas. The insulating layer 16b is etched. Further, the first insulating layer 16a made of Al ₂ O ₃ is etched by reactive ion etching (hereinafter referred to as RIE) using BCl ₃ gas, so that the second insulating layer 16b and the first insulating layer are etched. An opening OP1 penetrating the layer 16a in the thickness direction is formed. (Step 15) Next, as shown in FIG. 8 (o), the resist layer 18a is peeled and removed by, for example, an ashing process mainly including oxygen gas and a wet cleaning process. (Step 16) Next, as shown in FIG. 9 (p), a Ta barrier film / Cu seed layer 17a is formed on the upper surface of the second insulating layer 16b and the inner peripheral surface of the opening OP1, for example, by sputtering. To do. The thickness of the Ta barrier film is, for example, 50 nm, and the thickness of the Cu seed layer is, for example, 100 nm. (Step 17) Next, as shown in FIG. 9 (q), the surface of the Ta barrier film / Cu seed layer 17a on the second insulating layer 16b and the Ta barrier film / Cu seed in the opening OP1. A Cu plating film 17b is formed on the surface of the layer 17a by electrolytic plating. The thickness of the Cu plating film 17b is preferably a thickness that sufficiently fills the opening OP1 in which the Ta barrier film / Cu seed layer 17a is formed. (Step 18) Next, as shown in FIG. 9 (r), the Cu plating layer 17b and the Ta barrier film / Cu seed layer 17a on the second insulating layer 16b are removed by CMP to remove the first The upper surface of the second insulating layer 16b is exposed. (Step 19) Next, as shown in FIG. 10 (s), a third insulating layer 16c made of, eg, SiN is formed by, eg, CVD so as to cover the exposed upper surface of the second insulating layer 16b. To do. The thickness of the third insulating layer 16c is, for example, 200 nm. (Step 20) Next, as shown in FIG. 10 (t), a resist layer 18b having a predetermined opening pattern is formed on the third insulating layer 16c. The thickness of the resist layer 18b is 1.5 μm, for example. (Step 21) Next, as shown in FIG. 10 (u), the third insulating layer 16c is etched by RIE using C ₄ F ₈ / O ₂ / Ar gas using the resist layer 18b as a mask. Thus, the opening OP2 is formed. (Step 22) Next, as shown in FIG. 11 (v), the resist layer 18b is removed by, for example, a wet cleaning process. (Step 23) Next, as shown in FIG. 11 (w), plating is performed in the order of Ni / Au and connected to the conductors 17a and 17b for the extraction electrode filled in the opening OP1 in advance. An extraction electrode 17 is formed as a power feeding portion inside the opening OP2 and over the third insulating layer 16c, thereby completing the multilayer thin film capacitor 10 of the present embodiment.

Next, a preferred embodiment of the substrate 11 is as follows. That is, the substrate 11 is preferably selected from silicon, quartz, alumina, sapphire, glass and the like, obtained by cutting out from a base material, and having a flat surface. The thickness of the substrate 11 is preferably 20 μm to 500 μm. Note that an insulating layer made of, for example, SiO ₂ is preferably provided on one main surface of the substrate 11 for the purpose of improving the adhesion with one electrode 12 to be formed next. Is not limited to this.

Next, preferred embodiments of the electrodes 12A1 and 12A2 belonging to the one group and the electrodes 12B1 and 12B2 belonging to the other group are as follows. That is, the electrodes 12A1, 12A2 belonging to the one group and the electrodes 12B1, 12B2 belonging to the other group are preferably noble metals such as Pt, Ir, Ru, but are not limited thereto. When the noble metal is used, it is preferably formed on the substrate 11 by a film forming method using a mask such as vacuum deposition or sputtering. The electrode 12A1 belonging to the one group is directly formed on the SiO ₂ insulating film 11b of the substrate 11. However, the present invention is not limited to this. For example, the electrode 12A1 belongs to the SiO ₂ insulating film 11b and the one group. A TiO _x layer may be inserted between the electrode 12A1 for the purpose of improving adhesion.

Next, preferred embodiments of the dielectric layers 13a, 13b, and 13c are as follows. That is, the dielectric layers 13a, 13b, and 13c are preferably selected from various dielectric materials having a high dielectric constant such as BST (BaSrTiO ₃ ) and STO (SrTiO ₃ ).

Next, a preferred embodiment of the first insulating layer 16a formed on the element body 14 is as follows. That is, the insulating layer 16a preferably has a high hydrogen barrier property such as Al ₂ O ₃ . Further, not limited to this, for _{example, TiN, TaN, Ti x O} y, may be used a material such as _Ta x _{O y.}

Next, although the Ta barrier film is used as the base of the extraction electrode 17, the present invention is not limited to this. For example, TaN, TaSiN, TiSiN, or the like may be used.

Next, a preferred embodiment of the multilayer thin film capacitor 10 is as follows. That is, in the multilayer thin film capacitor 10, the electrode and the dielectric layer are substantially square, but the present invention is not limited to this, and may be changed to various rectangles. Moreover, it is not limited to a rectangle, For example, various changes, such as a circle and a polygon, are possible.

Next, a preferred embodiment of the element body 14 of the multilayer thin film capacitor 10 is as follows. That is, the element body 14 has a laminated structure including three dielectric layers, but is not limited to this and may have any number of laminated layers. Further, in the case of increasing the number of layers, it is preferable to insert Step 7 and Step 10 as appropriate every time Step 2 to Step 6, Step 8 and Step 9 are repeated. However, the present invention is not limited to this. For example, step 7 and step 10 may be inserted once each time step 2 to step 6, step 8 and step 9 are repeated a plurality of times.

Next, a preferred embodiment of the thickness adjusting conductor layers 15a and 15b is as follows. That is, the thickness adjusting conductor layers 15a and 15b are preferably noble metals such as Pt, Ir and Ru, and are the same as the electrodes 12a1 and 12A2 belonging to the one group and the electrodes 12B1 and 12B2 belonging to the other group. However, it is not limited to this. In addition, a preferred embodiment of a method of forming the thickness adjusting conductor layers 15a and 15b and the dielectric layers 13a, 13b, and 13c is as follows. That is, in the above-described embodiment, the targets 23 and 25 serving as film forming material sources are respectively arranged vertically above the substrate 11. However, the present invention is not limited to this. It can be changed to any position between 22A and 22B.

In addition, in the said embodiment, although the material and thickness dimension of each part were illustrated, it is not limited to this, It can change suitably. Moreover, in the said embodiment, although the film-forming method and processing method of each part were illustrated, it is not limited to this, It can change suitably.

Further, the multilayer thin film capacitor and the manufacturing method thereof of the present invention are not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention.

EXAMPLES Examples of the multilayer thin film capacitor of this embodiment will be described below with reference to FIGS. 1 and 4 to 13. FIG. 1 is a schematic diagram showing the internal structure of an example of the multilayer thin film capacitor of the present embodiment, and FIGS. 4 to 11 explain the manufacturing process of the multilayer thin film capacitor of the above example step by step. FIG. FIG. 12 is a diagram showing an internal structure of a multilayer thin film capacitor having a conventional structure as a comparative example. Further, FIG. 13 is a diagram showing the yield of non-defective products based on the capacitance measurement results for the multilayer thin film capacitor 10 of this embodiment and the multilayer thin film capacitor 110 of the comparative example having the conventional structure.

First, as shown in FIG. 4A, a substrate 11 was prepared by forming a 3 μm thick SiO ₂ insulating film 11b on one main surface of a silicon substrate 11a by a CVD method. Next, as shown in FIG. 4B, the electrode film-forming mask 32 was disposed on the substrate 11 to form a 150 nm-thick electrode 12A1 made of Pt belonging to one group. Next, as shown in FIG. 4C, a dielectric layer 13a made of BST having a thickness of 250 nm was formed so as to cover the electrode 12A1 belonging to the one group except for one end side. Next, as shown in FIG. 5 (d), an electrode made of Pt having a thickness of 150 nm belonging to the other group from above the dielectric layer 13a to the substrate 11 on the other end side of the dielectric layer 13a. 12B1 was formed. Next, in the same manner as in Step 3, as shown in FIG. 5E, a dielectric made of BST having a thickness of 250 nm so as to cover the electrode 12B1 belonging to the other group except for the other end side. Layer 13b was formed. Next, as in step 2 above, as shown in FIG. 5 (f), the one over the dielectric layer 13b and the electrode 12A1 belonging to the one group on one end side of the counter area OA. The electrode 12A2 belonging to this group was formed again to form the first connection portion 12AC. Next, as shown in FIG. 6G, a conductor layer 15a having a thickness of 400 nm for adjusting the thickness of the opposing region OA was further formed only on the first connection portion 12AC. Next, in the same manner as in Step 3, as shown in FIG. 6H, the first connecting portion 12AC in which the thickness adjusting conductor layer 15a is formed on the electrode 12A2 belonging to the one group is formed. The dielectric layer 13c was formed so as to cover except for the one end side. Next, in the same manner as in Step 4, as shown in FIG. 6 (i), the electrode 12B1 belonging to the other group on the other end side of the counter area OA is spread over the dielectric layer 13c. The electrode 12B2 belonging to the other group was formed again to form the second connection portion 12BC. Next, as shown in FIG. 7 (j), a conductor layer 15b having a thickness of 400 nm is formed on the second connection portion 12BC only for the purpose of adjusting the thickness with respect to the facing region OA. Thus, the element body 14 of the multilayer thin film capacitor 10 was formed on the substrate 11. Further, as shown in FIG. 7 (k), a first insulating layer 16a made of Al ₂ O ₃ and having a thickness of 150 nm is formed by sputtering so as to cover the element body 14 of the multilayer thin film capacitor on the substrate 11. Formed. Next, as shown in FIG. 7L, a second insulating layer 16b made of SiO ₂ and having a thickness of 3 μm was formed on the first insulating layer 16a by the CVD method. Next, as shown in FIG. 8M, a 1.5 μm thick resist layer 18a having a predetermined opening pattern was formed on the second insulating layer 16b. Next, as shown in FIG. 8 (n), using the resist layer 18a as a _mask, the second insulating layer 16b made of the SiO ₂ by RIE using _{C 4 F 8 / O 2 /} Ar gas The first insulating layer 16a made of Al ₂ O ₃ is etched by RIE using BCl ₃ gas, and the second insulating layer 16b and the first insulating layer 16a are etched in the thickness direction. An opening OP1 penetrating therethrough was formed. Next, as shown in FIG. 8 (o), the resist layer 18a was peeled and removed by an ashing process mainly including oxygen gas and a wet cleaning process. Next, as shown in FIG. 9 (p), a 50 nm thick Ta barrier film / 100 nm thick Cu seed layer 17a is formed by sputtering on the upper surface of the second insulating layer 16b and the inner peripheral surface of the opening OP1. Formed. Next, as shown in FIG. 9 (q), the surface of the Ta barrier film / Cu seed layer 17a on the second insulating layer 16b and the surface of the Ta barrier film / Cu seed layer 17a in the opening OP1. A Cu plating film 17b was formed by electrolytic plating. At this time, the thickness of the Cu plating film 17b was set so as to sufficiently fill the inside of the opening OP1 in which the Ta barrier film / Cu seed layer 17a was formed. Next, as shown in FIG. 9 (r), the Cu plating layer 17b and the Ta barrier film / Cu seed layer 17a on the second insulating layer 16b are removed by CMP to remove the second insulating layer. The upper surface of 16b was exposed. Next, as shown in FIG. 10 (s), a third insulating layer 16c made of SiN and having a thickness of 200 nm was formed by CVD so as to cover the exposed upper surface of the second insulating layer 16b. Next, as shown in FIG. 10 (t), a 1.5 μm thick resist layer 18b having a predetermined opening pattern was formed on the third insulating layer 16c. Next, as shown in FIG. 10 (u), the third insulating layer 16c is etched by RIE using C ₄ F ₈ / O ₂ / Ar gas using the resist layer 18b as a mask. OP2 was formed. Next, as shown in FIG. 11 (v), the resist layer 18b was removed by a wet cleaning process. Next, FIG.
As shown in FIG. 1 (w), plating is performed in the order of Ni / Au and connected to lead electrode conductors 17a and 17b filled in the opening OP1 in advance, and inside the opening OP2 and the third The lead electrode 17 as a power feeding portion over the insulating layer 16c was formed, and the multilayer thin film capacitor 10 of this embodiment was completed. (Comparative Example) A multilayer thin film capacitor 110 of a comparative example shown in FIG. 12 was completed in the same manner as in the above example except that the thickness adjusting conductor layers 15a and 15b described in Steps 7 and 10 were not formed. . For the multilayer thin film capacitor 10 of the example obtained above and the multilayer thin film capacitor 110 of the comparative example, each n = 1000 pieces was measured for capacitance and tan δ by using an LCR meter manufactured by Agilent Technologies, and short-circuited. FIG. 13 shows the result of calculating the yield of non-defective products by determining that the defect is caused by the connection portion. From this result, it was found that the yield of non-defective products was improved by about 20% in the multilayer thin film capacitor 10 of the example of the present invention compared to the multilayer thin film capacitor 110 of the conventional structure of the comparative example.

  The present invention is suitable for peripheral circuits of high-frequency modules such as Bluetooth (registered trademark) and W (wideband) -LAN, and capacitors such as RF-MEMS (Micro Electro Mechanical Systems).

It is a schematic diagram of the cross section which shows the internal structure of 1st Embodiment of the multilayer thin film capacitor of this invention. It is a schematic diagram which shows the internal structure of the film-forming apparatus used for the manufacturing method of the multilayer thin film capacitor of this invention. It is a top view which shows an example of the mask used for the manufacturing method of the multilayer thin film capacitor of this embodiment. It is a schematic diagram of the cross section for demonstrating a part of process of the manufacturing method of the multilayer thin film capacitor of this embodiment. It is a schematic diagram of the cross section for demonstrating a part of process of the manufacturing method of the multilayer thin film capacitor of this embodiment. It is a schematic diagram of the cross section for demonstrating a part of process of the manufacturing method of the multilayer thin film capacitor of this embodiment. It is a schematic diagram of the cross section for demonstrating a part of process of the manufacturing method of the multilayer thin film capacitor of this embodiment. It is a schematic diagram of the cross section for demonstrating a part of process of the manufacturing method of the multilayer thin film capacitor of this embodiment. It is a schematic diagram of the cross section for demonstrating a part of process of the manufacturing method of the multilayer thin film capacitor of this embodiment. It is a schematic diagram of the cross section for demonstrating a part of process of the manufacturing method of the multilayer thin film capacitor of this embodiment. It is a schematic diagram of the cross section for demonstrating a part of process of the manufacturing method of the multilayer thin film capacitor of this embodiment. It is a schematic diagram of the cross section which shows the multilayer thin film capacitor of a comparative example. It is a figure which shows the quality yield of the connection part of the Example of the multilayer thin film capacitor of this embodiment. It is a cross-sectional schematic diagram which shows an example of the multilayer thin film capacitor of background art. It is a schematic diagram of the cross section which shows the other example of the multilayer thin film capacitor of background art.

Explanation of symbols

10: Multilayer multilayer thin film capacitor 11: Substrate 11a: Silicon substrate 11b: SiO ₂ insulating film 12: Electrodes 12A1, 12A2: Electrode 12AC belonging to one group: First connecting portions 12B1, 12B2: belonging to the other group Electrode 12BC: 2nd connection part 13a, 13b, 13c: Dielectric layer 14: Element body 15a, 15b: Conductive layer 16 for adjusting thickness: Insulator layer 16a: Al ₂ O ₃ film 16b: SiO ₂ film 16c: SiN film 17: extraction electrode 17a: Ta barrier film / Cu seed layer 17b: Cu plating film 18a, 18b: resist layer 20: film formation apparatus (chamber) 22A: electrode film formation target (Pt, oblique) belonging to one group (For incident) 22B: electrode deposition target (Pt, for oblique incidence) 23: dielectric layer deposition target belonging to the other group Get (BST, for normal incidence) 25: Thickness adjusting conductor layer film formation target (Pt, for normal incidence) 32: Electrode film formation mask 32a: Frame portion 32b: Opening 33: Dielectric layer film formation mask 33a : Frame portion 33b: Opening 35: Mask layer 35a for adjusting the thickness 35a: Frame portion 35b: Opening OA: Opposing areas OP1, OP2: Opening

Claims (3)

The electrode belonging to one group, the dielectric layer, and the electrode belonging to the other group are arranged on one side of the substrate so that the electrode belonging to one group and the electrode belonging to the other group face each other with the dielectric layer interposed therebetween. In the multilayer thin film capacitor, which is alternately stacked on the main surface side, the one of the opposing regions where the electrode belonging to one group and the electrode belonging to the other group face each other across the dielectric layer A plurality of electrodes belonging to the first group overlapped with each other, and a second connection portion where the plurality of electrodes belonging to the other group overlapped with each other on the other end side of the opposing region. A laminated thin film characterized in that a conductive layer for adjusting the thickness for relaxing a step with the opposing region is further stacked on each of the first connecting portion and the second connecting portion. Yapashita. An extraction electrode having an insulating layer covering from the first connection portion to the second connection portion, and penetrating the insulation layer on the first connection portion and the second connection portion, respectively. The multilayer thin film capacitor according to claim 1, wherein the multilayer thin film capacitor is provided. Forming an electrode belonging to one group on the substrate; forming a dielectric layer so as to cover the electrode belonging to the one group except for one end; and A step of forming an electrode belonging to the other group over the substrate on the other end side of the dielectric layer, and a dielectric layer so as to cover the electrode belonging to the other group except the other end side And the electrode belonging to the one group and the electrode belonging to the second group belong to the one group on one end side of the opposing region facing each other across the dielectric layer from above the dielectric layer Forming a first connection portion again by forming an electrode belonging to the one group over the electrode, and an electrode belonging to the one group and the second group with the dielectric layer interposed therebetween Forming a dielectric layer so as to cover an opposing region facing the electrode to which the electrode belongs, excluding one end side of the opposing region, and the other group on the other end side of the opposing region from the dielectric layer Forming a second connecting portion by re-forming the electrode belonging to the other group over the electrode belonging to the above, and in a method of manufacturing a multilayer thin film capacitor, further comprising: Forming a thickness-adjusting conductor layer that relaxes the step with the facing region; and forming a thickness-adjusting conductor layer that further relaxes the step with the facing region on the second connection portion; A method for manufacturing a multilayer thin film capacitor, comprising:

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