JP2009015281A - Method for detecting pixel status of flat panel display and display driver thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To disclose methods and display drivers for pixel status detection of flat panel displays. <P>SOLUTION: The method includes the following steps of: providing scan data to the register; using the scan data to drive the pixel; detecting the pixel status to obtain status data; refreshing the register with the status data; and, comparing the scan data with the status data to determine whether the pixel is in abnormal status or not. Based on the method, the pixel status can be real-time monitored. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to flat panel display technology. More specifically, the present invention relates to a method for detecting the pixel state of a flat panel display and its display driver.

  With the development of technology, video products, especially digital video / video processing products, are becoming essential in our daily lives. A display device around a digital video / video processing apparatus is one of the important devices for displaying related information. The user may read information from the display and further operate the device accordingly. Flat panel displays, or light emitting diode (LED) displays, made with optoelectronics and semiconductor technology are in the spotlight in the display field. The LED display has a large size, high display quality, high brightness, and a wide viewing angle, and the LED display has become a popular display of a large size display.

  The LED display has the following features. If a pixel of an LED display is damaged, it can be repaired by directly replacing the damaged LED with a new LED. For this reason, techniques for detecting the state of LEDs have begun to appear in LED displays. Abnormal conditions of LEDs in LED displays include open circuits, short circuits, and overheating. Generally, the method for detecting the state of the LED can be divided into the following three techniques in the prior art.

  FIG. 1 illustrates a prior art LED driver for explaining a first technique for detecting an LED state in the prior art. In the first technique, as shown in FIG. 1, each of the drive circuits 103-1 to 103-m includes a warning terminal connected to a plurality of pixels and connected to the control unit 101. When the pixels in the plurality of pixels are in an abnormal state and the abnormal state is detected by the drive circuits 103-1 to 103-m, a warning signal is connected to the abnormal pixel in the plurality of pixels. It transmits to the control part 101 from the warning terminal of a certain drive circuit. Normally, the warning terminals from the drive circuits 103-1 to 103-m are connected together to the control unit 101 in order to reduce the number of pins of the control unit 101. However, by doing so, it is difficult for the control unit 101 to determine which pixel is abnormal.

  In the second prior art, a detection circuit for detecting a pixel state and reporting the state to the control unit is added to each drive circuit. The detection circuit of each drive circuit includes a dedicated line for connecting to the control unit. Therefore, the second technology increases the cost of the device and the complexity of the design.

In the third technique of the prior art, the drive circuit uses a mode switching circuit that switches the drive circuit between the display mode and the non-display mode and two control signals. This technique is disclosed in Patent Document 1. When the driving circuit is in the non-display mode, the serial data line may carry pixel state information. However, using two control signals increases the complexity of the firmware design and switching to the non-display mode may interrupt the display of the video. This technology also fails to meet real-time monitoring requirements.
US Pat. No. 6,930,679

  Accordingly, a method and display driver for pixel state detection of a flat panel display device is disclosed in the present invention. The present invention eliminates the need for a mode switching circuit for pixel state detection. Also, so-called real-time monitoring is achieved because the pixel state data is collected without interruption while the pixels display the video. Further, by comparing the scan data and the status data, the position of the abnormal pixel can be pinpointed.

  One object of the present invention is to configure a method for pixel state detection of a flat panel display.

  A method of detecting a pixel state of a flat panel display comprising a display driver having a register for driving a pixel, providing scan data to the register; and using the scan data to drive a pixel; Detecting a pixel state to obtain state data; refreshing the register with the state data; and scanning data and the state data to determine whether the pixel is in an abnormal state. Comparing.

  Another method for detecting a pixel state of a flat panel display comprising a display driver having n shift registers driving n pixels comprises: enabling the n pixels by the driver; and n state data Detecting n pixel states to obtain n, refreshing n shift registers with n state data, and determining which pixels in the n pixels by the n state data Determining whether is in an abnormal state. Here, n is a natural number.

  Another object of the present invention is to construct a display driver for pixel state detection of a flat panel display. The display driver is connected to a plurality of pixels of the display and includes m drive circuits and a control unit.

Each drive circuit of the display driver is
A data input terminal;
A data output terminal;
N drive terminals each connected to n pixels in the pixel;
n shift registers;
a detection device having n detection terminals and n output terminals,
m, n and i are natural numbers, and 0 <i <= n,
The data output terminal of the i-th drive circuit is connected to the data input terminal of the (i + 1) -th drive circuit;
Each shift register has an input terminal and an output terminal,
The output terminal of the i-th shift register is connected to the input terminal and the i-th drive terminal of the (i + 1) -th shift register;
In order to detect the state of n pixels and output the state data to the shift register, the detection terminals of the detection device are respectively connected to the drive terminals, and the output terminal of the detection device is Are respectively connected to the shift register.

  The control unit of the display driver includes a receiving terminal and a scanning data terminal. The receiving terminal connects the scanning data terminal to the data input terminal of the first driving circuit and receives the status data sequentially. Is connected to the data output terminal of the mth drive circuit. Here, the data input terminal of the first driving circuit sequentially receives scan data from the scan data terminal of the control unit according to a clock signal.

  The following benefits are achieved by the present invention. It is possible to pinpoint the position of a pixel in an abnormal state. A mode switching circuit for detecting the pixel state is not necessary, and the number of terminals used for detecting the pixel state can be reduced. In addition, real-time monitoring and invisible detection can be achieved without interrupting video display.

  In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

  It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the invention as set forth in the claims. It is.

  The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

  The LED display has the advantages of large size, high display quality, high brightness, and wide viewing angle, and the LED display has become a popular display of large size display. In the following, an LED display is used as an example illustrating an embodiment of the present invention. However, in the following embodiments, the pixels in the display are implemented with LEDs, while in other embodiments the pixels are implemented with thin film transistors and liquid crystals, organic light emitting diodes (OLEDs), or other light emitting devices. Also note that it is good.

  FIG. 2 is a schematic block diagram of a display driver for LED state detection according to the first embodiment of the present invention. Please refer to FIG. The display driver includes a control unit 201 and m drive circuits 203-1 to 203-m. The m drive circuits 203-1 to 203-m are cascade-connected. If each of the driving circuits 203-1 to 203-m can drive n LEDs, the display driver in FIG. 2 can drive m × n LEDs. Each drive circuit includes a data input (DAI) terminal and a data output (DAO) terminal. The shift registers from the drive circuits 203-1 to 203-m can shift input data bit by bit from the data input (DAI) terminal to the data output (DAO) terminal. The data input terminal of the driving circuit 203-1 is connected to the scanning data terminal of the control unit 201. In addition, scan data that carries video data to be displayed is transmitted from the control unit 201 to the drive circuits 203-1 to 203-m via the scan data terminal. The data output terminal of the first drive circuit 203-1 is connected to the data input terminal of the second drive circuit 203-2. The data output terminal of the second drive circuit 203-2 is connected to the data input terminal of a third drive circuit (not shown in FIG. 2). And so on. The data output terminal of the last drive circuit 203-m is connected to the reception terminal of the control unit 201. The control unit 201 serially transmits the scan data to the drive circuits 203-1 to 203-m. One bit of operation data is transmitted for each clock (CLK).

  While the LEDs are displaying an image such as image #K, for example, the detection devices of the drive circuits 203-1 to 203-m in FIG. 2 can detect the states of these LEDs. When the scan data of the new image, image # K + 1, is transmitted from the control unit 201 to the shift registers of the drive circuits 203-1 to 203-m, the control unit latches the scan data to latch the scan data. (LAT) signal is transmitted to the latch registers of the drive circuits 203-1 to 203-m, and the drive buffer devices of the drive circuits 203-1 to 203-m are latched in the latch registers. The LED is driven by the data. At the same time that the drive circuits 203-1 to 203-m receive the latch signal, the detection devices of the respective drive circuits 203-1 to 203-m drive the state data carrying the LED state data. Load the shift registers from circuits 203-1 to 203-m. When the next new scan data carrying image # K + 2 data is transmitted from the drive circuits 203-1 to 203-m, the LED state data is synchronized with the clock (CLK) signal, and the drive circuit The data is serially shifted out to the control unit 201 via the data output (DAO) terminals 203-1 to 203-m.

  Only when the LED is turned on by the driver, the LED state detection result can be useful. Therefore, the control unit 201 can only determine whether the LED that is turned on is in an abnormal state. The controller 201 may store the LED status data and the corresponding scan data in the memory device, and in order to pinpoint the exact position of the abnormal LED, the status data and the scan data May be compared.

  If it is necessary to detect the state of all the LEDs, the control unit 201 transmits scanning data carrying white image data to the drive circuits 203-1 to 203-m in order to turn on all the LEDs. Also good. The LED state data is serially shifted to the control unit 201 in synchronization with the clock signal (CLK), so that the control unit 201 pinpoints the exact position of these abnormal LEDs. (CLK) signal may be counted.

  FIG. 3 is a schematic block diagram of the internal connections of the drive circuit according to the first embodiment of the present invention, for example 203-1 of FIG. Please refer to FIG. For example, the drive circuit 203-1 for driving n LEDs includes n shift registers 301-1 to 301-n, n latch registers 303-1 to 303-n, a drive buffer device 305, , A detection device 307, a data input (DAI) terminal, a data output (DAO) terminal, a clock (CLK) input terminal, and a latch (LAT) input terminal.

  In the n shift registers 301-1 to 301-n, the data output terminal of the i-th shift register is connected to the data input terminal of the (i + 1) -th shift register. Here, i is an integer and 0 <i <= n.

  In the n latch registers 303-1 to 303-n, the output terminal of the jth latch register is connected to the drive buffer device 305 that drives the jth LED, and the jth latch register. The input terminal of the register is connected to the output terminal of the jth shift register. Here, j is an integer and 0 <j <= n.

  The drive buffer device 305 has its input terminal connected to the output terminals of n latch registers 301-1 to 303-n, and its output terminal connected to n LEDs.

  The detection device 307 has its input terminal connected to the LED and its output terminal connected to n shift registers 301-1 to 301-n.

  The data input (DAI) terminal of the drive circuit 203-1 is connected to the input terminal of the first shift register 301-1. The data output (DAO) terminal of the drive circuit 203-1 is connected to the output terminal of the nth shift register 301-n. The clock (CLK) input terminal provides a clock signal to the driving circuit 203-1. A latch (LAT) input terminal is connected to n latch registers 303-1 to 303-n and to the detection device 307.

  The CLK and LAT signals are transmitted from the control unit to the drive circuit 203-1.

  The detection device 307 of FIG. 3 can detect the states of n LEDs 309-1 to 309-n, while these LEDs display an image, for example, image #K. When the scan data of the new image, image # K + 1, is transmitted to the shift registers 301-1 to 301-n, a latch (LAT) signal is sent to the latch registers 303-1 to 303 to latch the scan data. The driving buffer device 305 drives the LEDs 309-1 to 309-n with the data latched to the latch registers 303-1 to 303-n. Simultaneously with receiving the latch signal, the detection device 307 loads the status data from the LEDs 309-1 to 309-n into the shift registers 301-1 to 301-n. When the scan data of the new image, image # K + 2, is shifted in via the data input (DAI) terminal, these LED state data are synchronized with the clock (CLK) signal and the data output (DAO) terminal is set. Shift out serially.

  FIG. 4 is a flowchart illustrating an LED state detection method according to the first embodiment of the present invention. Please refer to FIG. First, the control unit provides scan data to the shift register (S401). Next, the driving buffer device drives the LED according to the scan data (S403). The detection device can detect the state of the LED to obtain the state data (S405). Next, the detection device refreshes the shift register with the state data (S407). Finally, the state data is shifted to the control unit, and the scan data and the state data can be compared to determine which LED is in an abnormal state (S409).

  Subsequent examples are used to illustrate the implementation of the first embodiment of the present invention. Assume that the control unit 201 transmits n-bit scanning data, for example, 01... 1 to the driving circuit 203-1 in FIG. That is, logical bit 0 is shifted to the first shift register 301-1, logical bit 1 is shifted to the second shift register 301-2, and ... and logical bit 1 is shifted to the nth shift register 301-n. To do. When the latch (LAT) signal is transmitted to the drive circuit 203-1, the latch registers 303-1 to 303-n latch the scan data of the image #K. Next, the drive buffer device drives the LEDs 309-1 to 309-n according to the data latched in the latch registers 303-1 to 303-n. In this embodiment, since the scan data has n bits 01. ... and turn on the nth LED 309-n.

  The detection device 307 can detect the states of the LEDs 309-1 to 309-n that are displaying the image #K. Note that the status detection results are valid only for LEDs that are emitting light. Assume that the second LED 309-2 is abnormal. The detection device 307 discovers that the second LED 309-2 is abnormal and stores an abnormal state bit, for example a logical bit 0, in the second bit of the state data. For the sake of clarity, the state data corresponding to the state of the LED when the image #K is displayed is referred to herein as state data #K.

  When n-bit scan data of the next image, image # K + 1, is transmitted from the shift registers 301-1 to 301-n, a latch (LAT) signal is transmitted again to the driving device 203-1. When the driving device 203-1 receives the latch (LAT) signal, the detection device 307 loads the state data #K into the shift registers 301-1 to 301-n. In this embodiment, the second bit that is logic 0 of the state data #K is loaded into the second shift register 301-2. When n-bit scan data for the next image # K + 2 is transmitted from the shift registers 301-1 to 301-n, the status data #K from the shift registers 301-1 to 301-n is transmitted to the control unit 201. shift.

  The control unit 201 may compare the scan data of the image #K with the state data #K in order to determine which LED is abnormal. The logical bit 1 in the scan data indicates that the corresponding LED is turned on and the LED state detection result is valid. In this embodiment, the second bit of the scan data for image #K is a logic one, while the second bit of status data #K is a logic zero. Therefore, the control unit 201 knows that the second LED 309-2 is abnormal.

  From the above, a mode switching circuit and an extra control terminal are not required for LED state detection. While LED status data is collected, so-called real-time monitoring is achieved because the image is displayed without the LED being interrupted. Furthermore, the position of the abnormal LED can be pinpointed by comparing the scan data with the state data.

  It should be noted that the above-described embodiments are configurations that the present invention can take for LED state detection, but various modifications and variations will be apparent to those skilled in the art without departing from the scope or spirit of the present invention. Modifications can be made to the configuration of the present invention. That is, any invention comprising a method for comparing scan data with said status data to refresh a register with status data and determine whether a pixel of a flat panel display is in an abnormal state. Within the scope and spirit.

  In the following, more embodiments will be described so that those skilled in the art can easily carry out the present invention.

  FIG. 5 is a schematic block diagram of a display driver for LED state detection by a smart detection function according to a second embodiment of the present invention. Please refer to FIG. The display driver includes a control unit 501 and m drive circuits 503-1 to 503-m. The m drive circuits 503-1 to 503-m are cascade-connected. If each of the driving circuits 503-1 to 503-m can drive n LEDs, the display driver in FIG. 5 can drive m × n LEDs. Each drive circuit 503-1 to 503-m includes a data input (DAI) terminal and a data output (DAO) terminal. The shift registers from the drive circuits 503-1 to 503-m can shift input data bit by bit from the data input (DAI) terminal to the data output (DAO) terminal. The data input terminal of the first drive circuit 503-1 is connected to the scan data terminal of the control unit 501. The data output terminal of the first drive circuit 503-1 is connected to the data input terminal of the second drive circuit 503-2. The data output terminal of the second drive circuit 503-2 is connected to the data input terminal of a third drive circuit (not shown in FIG. 3). And so on. The data output terminal of the last drive circuit 503-m is connected to the reception terminal of the control unit 501. The control unit 501 serially transmits the scan data carrying the image data to be displayed to the drive circuits 503-1 to 503-m via the scan data terminal. One bit of the scan data is transmitted every clock (CLK).

  In FIG. 5, a smart detect (SDT) signal is used. When the smart detection (SDT) signal transmitted by the control unit 501 is received by the drive circuits 503-1 to 503-m, the smart detection process is started, and the drive circuits 503-1 to 503-m When the first latch (LAT) signal following the smart detection signal is received, the smart detection process is terminated. When a smart detection (SDT) signal is received by drive circuits 503-1 through 503-m, the drive buffer devices from drive circuits 503-1 through 503-m drive all LEDs and turn on. Here, the drive buffer device reduces the brightness of all the LEDs when emitting all the LEDs, so that even if image display is interrupted in the display device, human eyes cannot be detected, and the smart While detection is in progress, so-called invisible detection can be achieved. During the light emission of all the LEDs, the detection devices from the drive circuits 503-1 to 503-m detect the state of the LEDs and also transmit the state data carrying the LED state data to the drive circuits 503-1 to 503. Load up to -m shift registers. These LED state data are sent to the control unit 501 in synchronization with the clock (CLK) signal following the smart detection (SDT) signal via the data output (DAO) terminals from the drive circuits 503-1 to 503-m. Shift out serially. Since the LED status data is serially shifted out to the controller 501 in synchronization with the clock (CLK) signal, the controller 501 pinpoints the exact location of these abnormal LEDs. Clock (CLK) signals may be counted.

  FIG. 6 is a schematic block diagram of the internal connection of the drive circuit, such as 503-1 of FIG. 5, having smart detection capability according to the second embodiment of the present invention. Please refer to FIG. For example, the driving circuit 503-1 for driving n LEDs includes n shift registers 601-1 to 601-n, n latch registers 603-1 to 603-n, and a driving buffer device 605. An LED status detection circuit 607, a data input (DAI) terminal, a data output (DAO) terminal, a clock (CLK) input terminal, a latch (LAT) input terminal, and a smart detection (SDT) input terminal. It has.

  In the n shift registers 601-1 to 601-n, the data output terminal of the i-th shift register is connected to the data input terminal of the (i + 1) -th shift register. Here, i is an integer and 0 <i <n.

  In the n latch registers 603-1 to 603-n, the output terminal of the jth latch register is connected to the drive buffer device 605 for driving the jth LED, and the jth latch register. The input terminal of the register is connected to the output terminal of the jth shift register. Here, j is an integer and 0 <j <= n.

  The drive buffer device 605 has its input terminal connected to the output terminals of n latch registers 603-1 to 603-n, and its output terminal connected to n LEDs.

  The detection device 607 has its input terminal connected to the LED and its output terminal connected to n shift registers 601-1 to 601-n.

  The data input (DAI) terminal of the drive circuit 503-1 is connected to the input terminal of the first shift register 601-1. The data output (DAO) terminal of the drive circuit 503-1 is connected to the output terminal of the nth shift register 601-n. The clock (CLK) input terminal provides a clock signal to the driving circuit 503-1. A latch (LAT) input terminal is connected to n latch registers 603-1 to 603-n. A smart detection (SDT) input terminal is connected to the detection device 607.

  The CLK, LAT, and SDT signals are transmitted from the control unit to the drive circuit 503-1.

  Similarly, in FIG. 6, when the smart detection (SDT) signal is received by the drive circuit 503-1, the smart detection process is started and the first latch (LAT) signal following the smart detection signal is transmitted to the drive circuit 503. When received by -1, the smart detection process is terminated. When the smart detection (SDT) signal is received by the driving circuit 503-1, the driving buffer device 605 drives all n LEDs 609-1 to 609-n and turns on. The detection device 607 may directly control the drive buffer device 605 to drive and turn on all n LEDs 609-1 to 609-n, or the detection device 607 may control all n LEDs 609- In order to control the drive buffer device 605 to drive from 1 to 609-n and to turn on, for example, 1 may be loaded into n shift registers 601-1 to 601-n. When the drive buffer device 605 emits n LEDs 609-1 to 609-n under smart detection, the human eye does not detect the interruption of the image in the display device while the smart detection is in progress. As possible, the drive buffer device 605 reduces the brightness of all n LEDs 609-1 to 609-n. When all n LEDs are emitting light, the detection device 607 detects the states of the n LEDs 609-1 to 609-n, and stores the status data of the n LEDs in the n shift registers. Load from 601-1 to 601-n. In synchronization with the clock (CLK) signal following the smart detection (SDT) signal, these LED status data are serially shifted out through the data output (DAO) terminal.

  FIG. 7 is a flowchart illustrating an LED state detection method having a smart detection function according to the second embodiment of the present invention. Please refer to FIG. First, the control unit transmits a smart detection signal to the detection device (S701). Next, the detection device controls the drive buffer device to drive and turn on all LEDs (S703). The detection device can detect the states of all LEDs in order to obtain the state data (S705). Next, the detection device refreshes the shift register with the state data (S707). Finally, the state data is shifted to the control unit, and the control unit can determine which LED is in an abnormal state based on the state data (S709).

  FIG. 8 is a timing diagram of the smart detection process according to the second embodiment of the present invention. Clock (CLK), data input (DAI), latch (LAT), smart detect (SDT) and data output (DAO) signals are shown in the timing diagram. Please refer to FIG. As an embodiment, a driving circuit capable of driving eight LEDs is used. When a smart detection (SDT) signal is received by the drive circuit, the smart detection process is started and when the first latch (LAT) signal following the smart detection (SDT) signal is received by the drive circuit The smart detection process is terminated.

  All eight LEDs are turned on, and the state of all eight LEDs is detected when the drive circuit receives the SDT signal. Next, the status data of the eight LEDs are loaded into the eight shift registers and shifted out to the next device, which may be a control unit or another drive circuit, via the DAO signal. As shown in FIG. 8, the DAO signal is synchronized with the rising edge of the clock (CLK) signal. If logic “1” represents a normal LED state and logic “0” represents an abnormal LED state, the DAO signal in FIG. 8 indicates that the second LED and the fifth LED are abnormal. Here, the order of the eight LEDs is the order from the data input (DAI) terminal to the data output (DAO) terminal of the driving circuit.

  In the above embodiment of the present invention, an LED display was used as an example, but it should be noted that the method and display driver disclosed in the present invention can be applied to any kind of flat panel display.

  For those skilled in the art, various modifications and variations can be made to the configuration of the present invention without departing from the scope and spirit of the present invention. In view of the above, if modifications and variations of the present invention apply to the claims of the present application and equivalents thereof, it is understood that the present invention covers those modifications and variations.

FIG. 1 is a schematic block diagram of a display driver for conventional pixel state detection. FIG. 2 is a schematic block diagram of a display driver for LED state detection according to the first embodiment of the present invention. FIG. 3 is a schematic block diagram of the internal connection of the LED driving circuit according to the first embodiment of the present invention. FIG. 4 is a flowchart illustrating an LED state detection method according to the first embodiment of the present invention. FIG. 5 is a schematic block diagram of a display driver for LED state detection having a smart detection function according to a second embodiment of the present invention. FIG. 6 is a schematic block diagram of internal connections of an LED driving circuit having a smart detection function according to a second embodiment of the present invention. FIG. 7 is a flowchart illustrating an LED state detection method having a smart detection function according to the second embodiment of the present invention. FIG. 8 is a timing diagram of a smart detection process according to the second embodiment of the present invention.

Explanation of symbols

201 Control Unit 203-1 Drive Circuit 203-2 Drive Circuit 203-m Drive Circuit

Claims (15)

A method for pixel status detection of a flat panel display comprising a display driver having a register, for driving a pixel in the flat panel display,
Providing scan data to the register;
Using the scan data to drive the pixels;
Detecting a pixel state to obtain state data;
Refreshing the register with the status data;
Comparing the scan data with the state data to determine whether the pixel is in an abnormal state. The register includes n shift registers for driving n pixels, and each shift register includes:
A data input terminal;
A data output terminal;
A clock terminal,
The data output terminal of the i-th shift register is connected to the data input terminal of the (i + 1) -th shift register;
The clock terminal of the register receives a clock signal;
The method of claim 1, wherein the data input terminal of the first shift register receives the scan data. Detecting a pixel state to obtain the state data comprises:
Detecting the state of active pixels in all pixels;
k is a natural number and 0 <= k <= n,
The method of claim 2, further comprising storing an abnormal state bit in the kth bit of the state data when the kth pixel is detected as being in an abnormal state. Method.   The method of claim 3, wherein refreshing the register with the state data is refreshing the kth shift register with the kth bit of the state data.   The method of claim 1, wherein the pixel is a light emitting diode. A method for detecting a pixel state of a flat panel display, comprising:
Let n be a natural number,
The flat panel display having n pixels comprises a display driver having n shift registers for storing scan data for driving the n pixels,
Enabling the n pixels by the driver;
detecting n pixel states to obtain n state data;
Refreshing the n shift registers with the n state data;
Determining, from the n state data, which of the n pixels are in an abnormal state. Each shift register
A data input terminal;
A data output terminal;
A clock terminal,
The data output terminal of the i-th shift register is connected to the data input terminal of the (i + 1) -th shift register, the clock terminal of the register receives a clock signal, and the data of the first shift register The method according to claim 6, wherein the data input terminal receives n-bit scan data sequentially during a scan period according to the clock signal. Detecting the pixel state to obtain n-bit state data comprises
k is a natural number and 0 <= k <= n,
7. The method of claim 6, comprising storing an abnormal state bit in the kth bit of the state data when the kth pixel is in an abnormal state and is detected. . Refreshing the register with status data comprises:
9. The method of claim 8, wherein the step of refreshing the kth shift register with the kth bit of the status data.   The method of claim 6, wherein the pixel is a light emitting diode. A display driver to which a plurality of pixels of a display are connected, comprising m drive circuits,
A data input terminal;
A data output terminal;
N drive terminals each connected to n pixels in the pixel;
n shift registers;
a detection device having n detection terminals and n output terminals;
A control unit having a receiving terminal and a scanning data terminal,
m, n and i are natural numbers, and 0 <i <= n,
The data output terminal of the i-th drive circuit is connected to the data input terminal of the (i + 1) -th drive circuit;
Each shift register has an input terminal and an output terminal, and the output terminal of the i-th shift register is connected to the input terminal and the i-th drive terminal of the (i + 1) -th shift register. And
In order to detect the state of the n pixels and output the state data to the shift register, the detection terminals of the detection device are respectively connected to the drive terminals and the output of the detection device Each terminal is connected to the shift register,
The scan data terminal is connected to the data input terminal of the first drive circuit,
In order to receive the state data sequentially, the receiving terminal is connected to the data output terminal of the mth driving circuit;
The display driver according to claim 1, wherein the data input terminal of the first drive circuit sequentially receives operation data from the scan data terminal of the control unit by a clock signal. n latch registers,
Each of the latch registers is
A latch input terminal;
A latch output terminal;
A latch enable terminal for receiving the latch enable signal, and when receiving the latch enable signal, the latch register latches the data received from the latch input terminal to the latch output terminal,
j is a natural number, and 0 <j <= n,
The latch output terminal of the jth latch register is connected to the jth drive terminal, and the latch input terminal of the jth latch register is connected to the jth shift register. The display driver according to claim 11, wherein:   The display driver according to claim 12, further comprising a drive buffer connected between the jth latch register and the jth drive terminal.   The detection device includes a smart detection terminal that receives a smart detection signal to control the detection device to output n-bit specific data to n shift registers, respectively. 12. The display of claim 11, enabling the pixel with data, wherein the detection device detects the n pixels and outputs n specific result data to the shift register. driver. The display driver according to claim 11, wherein the plurality of pixels are a plurality of light emitting diodes.

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