JP2009009625A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a decrease in a potential difference between bit line pairs (True/Bar) of a sense amplifier by crosstalk of bit line pairs via a column selector. <P>SOLUTION: A semiconductor storage device has a plurality of memory cells arranged in matrix, a plurality of bit line pairs connected to the plurality of memory cells, a plurality of column selectors that are provided corresponding to the plurality of bit line pairs and that select an arbitrary bit line pair out of the plurality of bit line pairs, and a plurality of decoupling circuits that are provided corresponding to the plurality of column selectors and that connect the column selector which selects the arbitrary bit line pair to the sense amplifier. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device.

  At present, in a synchronous RAM (Random Access Memory), a sense amplifier is used in a read circuit in order to reduce current consumption and improve operation speed. Usually, the memory cells constituting the RAM are arranged in a matrix, and an arbitrary memory cell is selected by a row selection signal (word signal) and a column selection signal (column signal).

  First, data (True / Bar) of the selected memory cell is output to a bit line pair (True / Bar) that is a read data line connected to the memory cell, and passes through a column selector. Next, the column bit line pair (True / Bar), which is an output from the column selector, is propagated to the sense amplifier bit line pair (True / Bar) via the decoupling circuit. Further, the sense amplifier amplifies the potential difference between the sense amplifier bit lines (True / Bar). The amplified potential difference is output to the output circuit of the apparatus as data held in the memory. Therefore, the sense amplifier is less likely to malfunction as the potential difference between the sense amplifier bit line pair is increased. Here, the column bit line pair means a bit line pair from the column selector to the decoupling circuit (hereinafter the same in this specification). The sense amplifier bit line pair is a bit line pair connected to the sense amplifier from the decoupling circuit (hereinafter the same in this specification). At present, it is designed with an emphasis on ensuring operation by preventing potential malfunction by increasing the potential difference between the sense amplifier bit line pair (for example, shortening the wiring length of the bit line or reducing the MOS transistor in the memory cell) Increasing the ON current of).

  Here, since the bit line capacitance of the memory cell has been reduced due to the recent miniaturization of the manufacturing process, the potential difference between the bit line pair of the memory cell can be increased in a short time. For this reason, the potential difference between the sense amplifier bit line pair is also increased, and the operation speed has been improved.

  However, this process miniaturization reduced the bit line capacitance, but increased the parasitic capacitance between the bit line and the column bit line. As a result, the ratio of the parasitic capacitance between the bit line and the column bit line in the capacitance of the bit line itself has increased. Therefore, the parasitic capacitance between the bit line and the column bit line increases the influence of crosstalk between the bit line and the column bit line, and the potential fluctuation of the bit line of the memory cell is caused between the column bit lines via the crosstalk. Propagation problems occurred. Due to this problem, the potential difference between the sense amplifier bit line pairs input to the sense amplifier becomes small, and it is necessary to reduce the operation speed. The prior art will be described below based on this problem.

  FIG. 6 shows a conventional circuit configuration as described in Patent Document 1, and FIG. 7 shows an example of an operation timing chart thereof. As shown in FIG. 6, in the prior art, data held in a memory cell by a word line W11 or W12 that is a row direction selection signal of the memory cell and a column line Y10 or Y11 that is a column selection signal of the memory cell. Is transmitted to the column bit line pair YD1 / YD1_ through the column selector 13a or the column selector 13b via the bit line pair B10 / B10_ of the 0th column or the bit line pair B11 / B11_ of the first column. Further, the data propagates to the sense amplifier bit line pair D1 / D1_ through the decoupling circuit 15. Crosstalk X1a, X1b occurs between the bit line pair B10, B10_ and the column bit line pair YD1, YD1_, and between the bit line pair B11, B11_ and the column bit line pair YD1, YD1_, respectively.

  Here, as described above, the crosstalk X1a and X1b existed before, but the capacity of the bit line pair B10 / B10_ in the 0th column and the capacity of the bit line pair B11 / B11_ in the 1st column. Since the ratio of the parasitic capacitance to the size was small, the problem of crosstalk X1a and X1b did not occur.

  However, due to the miniaturization of the process, the parasitic capacitance between the bit line pair B10 / B10_ in the 0th column and the column bit line pair YD1 / YD1_ and between the bit line pair B11 / B11_ in the first column and the column bit line pair YD1 / YD1_ On the contrary, the capacitance of the bit line pair B10 / B10_ in the 0th column and the bit line pair B11 / B11_ itself in the 1st column is decreased. For this reason, the ratio of the parasitic capacitance to the capacitance of the bit line pair B10 / B10_ of the 0th column and the bit line pair B11 / B11_ itself of the 1st column is increased, and the problem of crosstalk X1a and X1b that cannot be found cannot be ignored. It was.

  Here, the mechanism of occurrence of problems under the above conditions will be described with reference to FIGS. As an example of the circuit operation of FIG. 6, consider an operation of reading data from the memory cell 11 c when the memory cell 11 c is at “L” level and the memory cell 11 d is at “H” level. In this case, the word line W11 becomes “H” level, and the data held in the memory cells 11c and 11d are output to the bit line pairs B10 / B10_ and B11 / B11_, respectively.

  The data of the bit line pair B10 / B10_ is transmitted to the column bit lines YD1 / YD1_ because the column line Y10 is at "H" level and the transfer gate of the column selector 13a is turned on. On the other hand, the data of the bit line pair B11 / B11_ is not transmitted to the column bit lines YD1 / YD1_ because the column gate Y11 is originally at the “L” level and the transfer gate of the column selector 13b remains off. However, as described above, since the crosstalk X1b exists, the gentle potential drop (potential fluctuation) of the bit line B11_ propagates to the column bit line YD1_ on the “H” level side via the crosstalk X1b. , The potential is slightly lower than the “H” level. When this is shown in the timing chart of FIG. 7, it means that the waveform of D1_ is originally expected to be 55, but the actual operation is 56 waveforms. As a result, the potential difference between the sense amplifier bit line pair D1 / D1_ is reduced. Therefore, since the potential difference between the sense amplifier bit line pair D1 / D1_ is reduced by the crosstalk X1a and X1b and the circuit may malfunction, a separate test for detecting malfunction due to crosstalk is required when selecting a good product. The problem is that the final product cost increases.

Here, in order to recover the reduced potential difference between the sense amplifier bit line pair D1 / D1_, it is necessary to delay the position at time T52 in FIG. However, if the time T52 is delayed, the operation after the time T52 is also delayed, so the operation speed is reduced. For this, it is only necessary to reduce the parasitic capacitance, and it is conceivable to increase the wiring interval between the bit line pair B10 / B10_ and the bit line pair B11 / B11_ and the column bit line pair YD1 / YD1_. However, this method increases the area of the semiconductor memory device because the wiring interval is widened, and the cost is increased, resulting in a problem that the product competitiveness is lowered.
Japanese Patent Laid-Open No. 08-329682

  In order to improve the above problem, the bit line pair connected to the sense amplifier by the crosstalk existing between the bit line pair sandwiching the column selector (above-mentioned, between the bit line pair and the column bit line pair) ( A circuit configuration that reduces the decrease in potential difference between the sense amplifier bit line pair (between True / Bar), as described above, is required.

  A semiconductor memory device according to the present invention is provided corresponding to each of a plurality of memory cells arranged in a matrix, a plurality of bit line pairs connected to the plurality of memory cells, and the plurality of bit line pairs. A plurality of column selectors for selecting an arbitrary bit line pair from among the plurality of bit line pairs, and a column selector for selecting the arbitrary bit line pair provided corresponding to each of the plurality of column selectors. And a plurality of decoupling circuits for connecting to the sense amplifier.

  According to the semiconductor memory device of the present invention, the influence of crosstalk existing between the bit line pairs sandwiching the column selector can be reduced by providing a decoupling circuit corresponding to each column selector.

  According to the present invention, it is possible to prevent a potential difference between a bit line pair (True / Bar) connected to a sense amplifier from being reduced due to the influence of crosstalk between bit line pairs sandwiching a column selector.

<Embodiment 1 of the Invention>
Hereinafter, a specific first embodiment to which the present invention is applied will be described in detail with reference to the drawings. FIG. 1 shows a circuit configuration according to the first embodiment of the present invention. In the first embodiment, the present invention such as an SRAM is applied to a semiconductor memory device.

  As shown in FIG. 1, the circuit according to the first embodiment includes a bit line pair B10 / B10_ in the 0th column and a bit line pair B11 / B11_ in the 1st column. In addition, a column bit line pair YD10 / YD10_ corresponding to the bit line pair B10 / B10_ in the 0th column is provided between a column selector 13a described later and a decoupling circuit 15a, and the column selector 13b described later and the decoupling circuit 15b are also described. A column bit line pair YD11 / YD11_ corresponding to the bit line pair B11 / B11_ in the first column is provided therebetween. Further, it has a sense amplifier bit line pair D1 / D1_ connected from the decoupling circuits 15a and 15b to a sense amplifier 16 described later. Here, the bit line pairs, column bit line pairs, and sense amplifier bit line pairs described above are bit line pairs in a broad sense.

  The circuit of the first embodiment has memory cells 11a, 11c, 11b, and 11d connected to the bit line pairs B10 / B10_ and B11 / B11_, and each memory cell is a word that is a row selection signal. Selection is made by the line W11 or W12 and the column line Y10 or Y11 which is a column selection signal of the memory cell. Here, for example, the memory cell 11c includes switching NMOS transistors Q11 and Q12 whose gates are connected to the word line W11, and inverters Q13 and Q14 that hold memory data. Other memory cells have the same configuration.

  The circuit according to the first embodiment includes precharge circuits 12a, 12b, 14a, 14b, and 17, column selectors 13a and 13b, decoupling circuits 15a and 15b, and a sense amplifier 16.

  The precharge circuits 12a and 12b are connected to bit line pairs B10 / B10_ and B11 / B11_. The precharge circuits 14a and 14b are connected to the column bit line pair YD10 / YD10_ and YD11 / YD11_. The precharge circuit 17 is connected to the sense amplifier bit line pair D1 / D1_. For example, the precharge circuits 12a, 12b, and 17 precharge the bit lines and sense amplifier bit lines connected to the “H” level in response to the “L” level precharge signal P1, for example. For example, the precharge circuit 14a precharges the connected column bit line YD10 / 10_ to the “H” level in response to the column selection signal of the “L” level column line Y10. Similarly, the precharge circuit 14b precharges the connected column bit line YD11 / 11_ to the “H” level in response to, for example, a column selection signal of the “L” level column line Y11. The precharge circuits 12a, 12b, 14a, 14b, and 17 all have the same circuit configuration.

  The column selectors 13a and 13b are respectively connected between the bit line pair B10 / B10_ and the column bit line pair YD10 / YD10_, and between the bit line pair B11 / B11_ and the column bit line pair YD11 / YD11_. The column selectors 13a and 13b, for example, turn on the internal transfer gates by the “H” level column signal Y10 or Y11 to connect the bit lines and the column bit lines, respectively.

  The decoupling circuits 15a and 15b are respectively connected between the column bit line pair YD10 / YD10_ and the sense amplifier bit line pair D1 / D1_, and between the column bit line pair YD11 / YD11_ and the sense amplifier bit line pair D1 / D1_.

  For example, when the decoupling control signal DC10 in the 0th column and the decoupling control signal DC11 in the 1st column are at the “H” level, the decoupling circuits 15a and 15b turn on the internal transfer gates and set the column bit line pair YD10. / YD10_, YD11 / YD11_ and a sense amplifier bit line pair D1 / D1_. Here, the decoupling control signals DC10 and DC11 are logically set so that the word line W11 and the word line 12 are at the “H” level and the “L” level is set only while the sense amplifier control signal S1 is at the “L” level. Controlled by circuits 18 and 19.

  The sense amplifier 16 is connected to the sense amplifier bit line pair D1 / D1_. The sense amplifier 16 amplifies and outputs the potential difference between the sense amplifier bit line pair D1 / D1_ in accordance with the sense amplifier control signal S1 (for example, at “H” level). The amplified potential difference of the sense amplifier bit line pair D1 / D1_ is sent to an output circuit (not shown) of the device.

  The crosstalk X1a indicates crosstalk caused by a parasitic capacitance between the column bit line pair YD10 / YD10_ in the same column as the bit line pair B10 / B10_. Similarly, the crosstalk X1b indicates crosstalk caused by a parasitic capacitance between the column bit line pair YD11 / YD11_ in the same column as the bit line pair B11 / B11_.

  Further, in this embodiment, in order to avoid complication of the figure, the memory cell array has only two columns in the column direction. However, a plurality of memory cells are further arranged in the column direction and the row direction to form a matrix. You may arrange in. In this case, a column line for selecting a plurality of memory cells in units of columns and a word line for selecting in units of rows, a bit line pair for transmitting data of each memory cell, a column bit line pair, and the like. A plurality of column selectors, decoupling circuits, etc. are required in accordance with the number of memories.

  Next, the operation of the circuit of the first embodiment will be described. Here, in the circuit configuration of FIG. 1, the memory cell 11a / 11c holds the “L” level, the memory cell 11b / 11d holds the “H” level, and the data of the memory cell 11c is read.

  First, in an operation waiting state, the word lines W11 and W12, the column lines Y10 and Y11, the precharge signal P1, and the sense amplifier control signal S1 are all at the “L” level. The bit line pair B10 / B10_ in the 0th column is a precharge circuit 12a, the bit line pair B11 / B11_ in the 1st column is a precharge circuit 12b, and the column bit line pair YD10 / YD10_ in the 0th column is a precharge circuit 14a. The column bit line pair YD11 / YD11_ in the first column is precharged to the “H” level by the precharge circuit 14b, and the sense amplifier bit line pair D1 / D1_ is precharged to the “H” level.

  Next, in order to select the memory cell 11c, the word line W11 is changed to "H" level, the precharge signal P1 is changed to "H" level, and the column line Y10 is changed to "H" level.

  In response to the “H” level of the word line W11, the NMOS transistors Q11 and Q12 in the memory cell 11c are turned on, and the retained data in the memory cell 11c is transferred to the bit line pair B10 / B10_ in the 0th column via the NMOS transistor. Propagate to. At the same time, a similar operation occurs in the memory cell 11d connected to the word line W11, and the data held in the memory cell 11d propagates to the bit line pair B11 / B11_ in the first column.

  At the same time, the transfer gate in the column selector 13a is turned on in response to the “H” level of the column line Y10 which is a column selection signal of the memory cell, and the bit line pair B10 / 0 of the 0th column is turned on via the transfer gate. B10_ and column bit line pair YD10 / YD10_ are connected. Therefore, the data of the bit line pair B10 / B10_ in the 0th column is propagated to the column bit line pair YD10 / YD10_ in the 0th column.

  Here, the column selector 13b in the first column is in an OFF state by the column line Y11. Further, the column bit line pair YD11 / YD11_ in the first column is precharged to the “H” level by the precharge circuit 14b controlled by the column line Y11. Further, the column bit line pair YD11 / YD11_ and the sense amplifier bit line pair D1 / D1_ in the first column are blocked by the decoupling circuit 15b in the first column.

  Here, since the sense amplifier control signal S1 is at the “L” level and the transfer gate in the decoupling circuit 15a in the 0th column is in the ON state, the column bit line pair in the 0th column is passed through the transfer gate. YD10 / YD10_ and sense amplifier bit line pair D1 / D1_ are connected, and data of column bit line pair YD10 / YD10_ propagates to sense amplifier bit line pair D1 / D1_.

  Further, at this time, the precharge signal P1 causes the precharge circuit 12a / 12b of the bit line pair B10 / B10_ in the 0th column and the bit line pair B11 / B11_ in the first column, and the precharge circuit of the sense amplifier bit line pair D1 / D1_. 17 is in an OFF state. Further, the precharge circuit 14a of the bit line pair YD10 / YD10_ in the 0th column is also turned off by the “H” level column line Y10. Therefore, due to the current capability of the NMOS transistors Q11 and Q12 in the memory cell 11c, a gradual potential decrease to the “L” level occurs in the bit lines B10 and B11_. The potential decrease of the bit line B10 (the bit line B10_ remains at the “H” level) is propagated to the column bit line pair YD10 because the transfer gate of the column selector 13a is ON as described above.

  On the other hand, in the prior art, as has been a problem, the potential decrease of the bit line B11_ (the bit line B11 remains at the “H” level) despite the fact that the transfer gate of the column selector 13b is OFF. , And propagated to the column bit line pair YD11 via the crosstalk X1b. As a result, in the prior art, the potential difference between the sense amplifier bit line pair D1 / D1_ is further reduced. However, in the present invention, the column bit line pair YD11 / YD11_ in the first column that is not selected is in the ON state because the precharge circuit 14b controlled by the column line Y11 is in the ON state. Since the potential of / YD11_ is precharged to the “H” level, there is no potential fluctuation. Therefore, unlike the prior art, the potential difference between the sense amplifier bit line pair D1 / D1_ does not decrease as a result of the influence of the potential fluctuation of the bit line pair B11 / B11_ in the first column.

  Next, the sense amplifier 16 is operated by changing the sense amplifier control signal S1 to the “H” level. This amplifies the potential difference between the sense amplifier bit line pair D1 / D1_ and simultaneously turns off the transfer gate in the decoupling circuit 15a to turn off the column bit line pair YD10 / YD10_ in the 0th column and the sense amplifier bit line pair. D1 / D1_ is blocked so that the potential change of the amplified sense amplifier bit line pair D1 / D1_ does not propagate to the bit line pair B10 / B10_ in the 0th column.

  Next, the potential difference between the sense amplifier bit line pair D1 / D1_ is amplified to determine the output. Thereafter, the word line W11, the column line Y10, the precharge signal P1, and the sense amplifier control signal S1 are set to the “L” level, and the bit line pairs B10 / B10_, B11 / B11_, the column bit line pairs YD10 / YD10_, YD11 / YD11_ The sense amplifier bit line pair D1 / D1_ is precharged to “H” level by the precharge circuit, returned to the operation waiting state, and a series of operations is completed.

  FIG. 2 shows a timing chart of the operation described above. In FIG. 2, the operation is waiting at time T20. Therefore, the word lines W11 and W12, the column lines Y10 and Y11, the precharge signal P1, and the sense amplifier control signal S1 are all at the “L” level. Therefore, the bit line pairs B10 / B10_, B11 / B11_, the column bit line pairs YD10 / YD10_, YD11 / YD11_, and the sense amplifier bit line pair D1 / D1_ are at the “H” level.

  At time T21, in response to the change of the word line W11 as the row selection signal of the memory cell, the column line Y10 as the column selection signal, and the precharge signal P1 to the “H” level, the bit line B10 in the 0th column, 1 column The bit line B11_ of the eye gradually changes from the “H” level to the “L” level (arrow 21 in FIG. 2).

  At the same time, in response to the “H” level of the column line Y10 which is a column selection signal of the memory cell, the potential of the bit line pair B10 / B10_ is propagated to the column bit line pair YD10 / YD10_ of the 0th column. At the same time, the decoupling control signal DC10 becomes “L” level by the “L” level of the sense amplifier control signal S1. Therefore, the potential of the bit line pair B10 / B10_ propagated to the column bit line pair YD10 / YD10_ in the 0th column propagates to the sense amplifier bit line pair D1 / D1_. Therefore, the potentials of the column bit line pair YD10 / YD10_ and the sense amplifier bit line pair D1 / D1_ change (arrow 22 in FIG. 2).

  During the above operation, the column bit line pair YD11 / YD11_ in the first column remains precharged to the “H” level by the column line Y11, and therefore the column bit line pair YD11 in the first column due to the crosstalk X1b in FIG. The potential decrease of / YD11_ does not occur. Further, since the column line Y11 is at the “L” level, the decoupling control signal DC11 remains at the “H” level.

  At time T22 in FIG. 2, the sense amplifier control signal S1 changes to "H" level, and the potential difference between the sense amplifier bit line pair D1 / D1_ is amplified. Here, since the sense amplifier control signal S1 is at “H” level, the amplified potential of the sense amplifier bit line pair D1 / D1_ is not propagated to the column bit line pair YD10 / YD10_ in the 0th column (arrow in FIG. 2). 23).

  At time T23 in FIG. 2, the word line W11, the column line Y10, the precharge signal P1 and the amplifier control signal S1 are at the “L” level, and the bit line pair B10 / B10_ in the 0th column and the bit line pair B11 in the 1st column / B11_, the column bit line pair YD10 / YD10_ in the 0th column, the column bit line pair YD11 / YD11_ in the 1st column, and the sense amplifier bit line pair D1 / D1_ receive the “L” level of the precharge signal P1 and become “H” ”Level (arrow 24 in FIG. 2).

  At time T24 in FIG. 2, the state is the same as time T20 in FIG. The above is the description of the operation.

  In the first embodiment according to the present invention, the column bit line pair of the unselected column is precharged by the above-described operation, and the column bit of the column not selected by the decoupling circuit provided for each column of the memory cell is further selected. The line pair is disconnected from the sense amplifier bit line pair. As described above, since the output of the decoupling circuit is used as the input of the sense amplifier bit line pair, the sense due to the crosstalk generated between the bit line pair of the unselected column and the column bit line pair generated in the prior art. A decrease in potential difference between the amplifier bit line pair can be eliminated. Therefore, since the time required to recover the reduced potential difference between the sense amplifier bit line pair D1 / D1_, which has been a problem in the prior art, is not required, the operation speed can be increased compared to the prior art.

  In addition, since the sense amplifier malfunction does not occur due to a decrease in the potential difference between the sense amplifier bit line pair due to crosstalk, which is a problem of the prior art, it is necessary to perform a sense amplifier malfunction confirmation test due to crosstalk when selecting a good product. As a result, the final product cost is reduced.

<Embodiment 2 of the Invention>
Hereinafter, a specific second embodiment to which the present invention is applied will be described in detail with reference to the drawings. In the second embodiment, as in the first embodiment, the present invention is applied to a semiconductor memory device.

  FIG. 3 shows a circuit configuration diagram of the second embodiment of the present invention. The difference from the first embodiment is the configuration in the decoupling circuit. Other configurations are the same as those in the first embodiment, and a description thereof will be omitted. Further, the configurations denoted by the same reference numerals as those in FIG. 1 are the same as or similar to those in FIG.

  As shown in FIG. 3, the decoupling circuit 35a / 35b having the circuit configuration of the second embodiment is composed of only a PMOS transistor whose gate receives a decoupling control signal DC10 / DC11. That is, the transfer gate portion in the decoupling circuit 15a / 15b of the first embodiment is replaced with a PMOS transistor.

  With such a circuit configuration of the second embodiment, the capacity of the sense amplifier bit line pair D1 / D1_ can be reduced, and even when the current capability of the NMOS / PMOS transistor in the memory cell is low, the sense amplifier bit line pair D1 / D1. The potential difference between D1_ can be increased.

  As for the operation, the word lines W11 / W12 that are memory cell row selection signals and the column lines Y10 / Y11 that are memory cell column selection signals are at “H” level, and the amplifier control signal S1. Is a potential difference between the sense amplifier bit line pair D1 / D1_ during the “L” level. However, since the capacitance value connected to the path from the bit line pair B10 / B10_ to the sense amplifier bit line pair D1 / D1_ through the column bit line pair YD10 / YD10_ is smaller than that in the first embodiment, The potential difference between the sense amplifier bit line pair D1 / D1_ that can be secured within the same time as in the first embodiment can be made larger than that in the first embodiment. The capacity actually reduced is the NMOS transistor in the decoupling circuit 15a / 15b in FIG. 1 with respect to the first embodiment.

  In the circuit of the first embodiment, transfer gates are used for the decoupling circuits 15a / 15b, but as can be seen from the operation timing chart of FIG. 2, the column bit line pair YD10 / YD10_ and the column bit line pair YD11 / YD11_ There is no amplitude from the “H” level to the “L” level. Therefore, it can be seen that only the PMOS transistor that propagates the “H” level is sufficient. Therefore, for the reason described above, only the PMOS transistor can be provided like the decoupling circuit 35a / 35b shown in FIG. 3 as in the present embodiment, and the operation speed can be improved compared to the first embodiment. Become.

  FIG. 4 shows a circuit configuration diagram in consideration of the development of the read port in the 2-port RAM with respect to the circuit configuration of FIG.

  The difference from the circuit configuration shown in FIG. 3 is that the circuit in the column selector 43a / 43b is changed. Although the column selectors 13a / 13b in FIG. 3 are configured by transfer gates, in the present embodiment, they are configured by only PMOS transistors.

  In the circuit configuration of FIG. 4, since only the read operation is performed at the read port in the 2-port RAM, the bit line pair B10 / B10_ in the 0th column and the bit line pair B11 / B11_ in the 1st column are shown in the timing chart of FIG. Thus, since there is no amplitude from the “H” level to the “L” level, the column selector 43a / 43b can be configured by only a PMOS transistor that propagates the “H” level. With the above configuration, the capacitance value from the bit line pair to the sense amplifier bit line pair via the column bit line pair is reduced, and the speed is further increased compared to the first and second embodiments (the circuit configuration of FIG. 3). Is possible.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, as in the circuit configuration shown in FIG. 5, the control signal of the column selector 13a / 13b of FIG. 1 is changed from the column line Y10 and the column line Y11 to the decoupling control signals DC10 and DC11 of the decoupling circuit 15a / 15b. Circuit elements may be reduced. The circuit configuration of FIG. 5 is a circuit configuration obtained by reducing the control circuit with respect to the first embodiment, and the product cost can be reduced by reducing the circuit area.

An example of a circuit configuration of the semiconductor memory device according to the first embodiment An example of a timing chart of the semiconductor memory device according to the first embodiment Example of circuit configuration of semiconductor memory device according to second embodiment An example of another circuit configuration of the semiconductor memory device according to the second embodiment Example of circuit configuration of semiconductor memory device according to other embodiment Example of circuit configuration of semiconductor memory device according to prior art Example of timing chart of semiconductor memory device according to prior art

Explanation of symbols

11a, 11b, 11c, 11d Memory cells B10, B10_, B11, B11_ Bit lines YD10, YD10_, YD11, YD11_ Column bit lines D1, D1_ Sense amplifier bit lines W11, W12 Word lines (row selection signals)
Y11, Y12 Column line (column selection signal)
P1 Precharge signal line (precharge signal)
S1 sense amplifier control signal line (sense amplifier control signal)
DC10, DC10_, DC11, DC11_ decoupling control signal line (decoupling control signal)
12a, 12b, 14a, 14b, 16 Precharge circuits 13a, 13b Column selectors 15a, 15b Decoupling circuits X1a, X1b Crosstalk

Claims (5)

A plurality of memory cells arranged in a matrix;
A plurality of bit line pairs connected to the plurality of memory cells;
A plurality of column selectors provided corresponding to each of the plurality of bit line pairs, for selecting an arbitrary bit line pair among the plurality of bit line pairs;
A semiconductor memory device having a plurality of decoupling circuits provided corresponding to each of the plurality of column selectors and connecting a column selector for selecting the arbitrary bit line pair to a sense amplifier;   2. The semiconductor according to claim 1, further comprising: a plurality of precharge circuits connected to the bit line pairs between the plurality of column selectors and the plurality of decoupling circuits provided corresponding to each of the plurality of column selectors. Storage device.   The semiconductor memory device according to claim 2, wherein the plurality of column selectors, the plurality of decoupling circuits, and the plurality of precharge circuits are selectively controlled according to a column selection signal.   The plurality of precharge circuits precharge the bit line pairs between the plurality of column selectors not selected and the plurality of decoupling circuits provided corresponding to the plurality of column selectors, respectively. A semiconductor device according to 1.   5. The semiconductor device according to claim 3, wherein the plurality of decoupling circuits are further controlled by a sense amplifier control signal that controls the sense amplifier.

Images